[PATCH 0/2] Add description for the RISC-V relocatable modifiers in as doc

[PATCH 0/2] Add description for the RISC-V relocatable modifiers in as doc

[Nelson Chu]

Hi binutils,

I am completing the documentation for RISC-V recently.  Kito remind me that
James Clarke had sent a good patch for adding the %got_pcrel_hi operator
to assembler.  But the patch is pending for a long time since the binutils'
copyright assignment.  Since LLVM side already use the new modifier, I think
GNU side should be sync with them.  Therefore, I add some description about
RISC-V relocatable modifiers in the as doc, including James' patch.

Hi James,

Please feel free to tell me that if you are OK for this, or you want to send
the patch again by yourselves.

Thanks for all
Nelson

[PATCH 2/2] RISC-V: Support assembler modifier %got_pcrel_hi.

[Nelson Chu]

	gas/
	* config/tc-riscv.c: Support the modifier %got_pcrel_hi.
	* doc/c-riscv.texi: Add documentation.
	* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
	modifier %got_pcrel_hi.
	* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
	* testsuite/gas/riscv/relax-reloc.d: Likewise.
	* testsuite/gas/riscv/relax-reloc.s: Likewise.
---
 gas/config/tc-riscv.c                    |  1 +
 gas/doc/c-riscv.texi                     | 12 ++++++++++++
 gas/testsuite/gas/riscv/no-relax-reloc.d |  4 +++-
 gas/testsuite/gas/riscv/no-relax-reloc.s |  7 +++++--
 gas/testsuite/gas/riscv/relax-reloc.d    |  7 +++++--
 gas/testsuite/gas/riscv/relax-reloc.s    |  7 +++++--
 6 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ddd4d14..168561e 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1308,6 +1308,7 @@ static const struct percent_op_match percent_op_utype[] =
 {
   {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
   {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
+  {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
   {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
   {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
   {"%hi", BFD_RELOC_RISCV_HI20},
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 8212a17..72605e7 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -249,6 +249,18 @@ Or you can use the pseudo lla/lw/sw/... instruction to do this.
 	lla  a0, @var{symbol}
 @end smallexample
 
+@item %got_pcrel_hi(@var{symbol}
+The high 20-bit of relative address between pc and the GOT entry of
+@var{symbol}.  This is usually used with the %pcrel_lo to access the GOT entry.
+
+@smallexample
+@var{label}:
+	auipc           a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
+	addi/load/store a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I/S
+@end smallexample
+
+Also, the pseudo la instruction with PIC has the similar behavior.
+
 @item %tprel_add(@var{symbol}
 This is used purely to associate the R_RISCV_TPREL_ADD relocation for
 TLS relaxation.
diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.d b/gas/testsuite/gas/riscv/no-relax-reloc.d
index 62f28e0..c2ca1aa 100644
--- a/gas/testsuite/gas/riscv/no-relax-reloc.d
+++ b/gas/testsuite/gas/riscv/no-relax-reloc.d
@@ -9,4 +9,6 @@ RELOCATION RECORDS FOR .*
 0+4 R_RISCV_LO12_I.*
 0+8 R_RISCV_PCREL_HI20.*
 0+c R_RISCV_PCREL_LO12_I.*
-0+10 R_RISCV_CALL.*
+0+10 R_RISCV_GOT_HI20.*
+0+14 R_RISCV_PCREL_LO12_I.*
+0+18 R_RISCV_CALL.*
diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.s b/gas/testsuite/gas/riscv/no-relax-reloc.s
index 7f1a484..2aab995 100644
--- a/gas/testsuite/gas/riscv/no-relax-reloc.s
+++ b/gas/testsuite/gas/riscv/no-relax-reloc.s
@@ -2,7 +2,10 @@ target:
 	lui	a5,%hi(target)
 	lw	a5,%lo(target)(a5)
 
-        .LA0: auipc     a5,%pcrel_hi(bar)
-        lw      a0,%pcrel_lo(.LA0)(a5)
+	.LA0: auipc     a5,%pcrel_hi(symbol1)
+	lw      a0,%pcrel_lo(.LA0)(a5)
+
+	.LA1: auipc     a5,%got_pcrel_hi(symbol2)
+	lw      a0,%pcrel_lo(.LA1)(a5)
 
 	call target
diff --git a/gas/testsuite/gas/riscv/relax-reloc.d b/gas/testsuite/gas/riscv/relax-reloc.d
index f5f592c..623218e 100644
--- a/gas/testsuite/gas/riscv/relax-reloc.d
+++ b/gas/testsuite/gas/riscv/relax-reloc.d
@@ -13,5 +13,8 @@ RELOCATION RECORDS FOR .*
 0+8 R_RISCV_RELAX.*
 0+c R_RISCV_PCREL_LO12_I.*
 0+c R_RISCV_RELAX.*
-0+10 R_RISCV_CALL.*
-0+10 R_RISCV_RELAX.*
+0+10 R_RISCV_GOT_HI20.*
+0+14 R_RISCV_PCREL_LO12_I.*
+0+14 R_RISCV_RELAX.*
+0+18 R_RISCV_CALL.*
+0+18 R_RISCV_RELAX.*
diff --git a/gas/testsuite/gas/riscv/relax-reloc.s b/gas/testsuite/gas/riscv/relax-reloc.s
index 7f1a484..2aab995 100644
--- a/gas/testsuite/gas/riscv/relax-reloc.s
+++ b/gas/testsuite/gas/riscv/relax-reloc.s
@@ -2,7 +2,10 @@ target:
 	lui	a5,%hi(target)
 	lw	a5,%lo(target)(a5)
 
-        .LA0: auipc     a5,%pcrel_hi(bar)
-        lw      a0,%pcrel_lo(.LA0)(a5)
+	.LA0: auipc     a5,%pcrel_hi(symbol1)
+	lw      a0,%pcrel_lo(.LA0)(a5)
+
+	.LA1: auipc     a5,%got_pcrel_hi(symbol2)
+	lw      a0,%pcrel_lo(.LA1)(a5)
 
 	call target
-- 
2.7.4

[PATCH 1/2] RISC-V: Add description for RISC-V Modifiers to as doc.

[Nelson Chu]

	gas/
	* doc/c-riscv.texi (relocation modifiers): Add documentation.
	(RISC-V-Formats): Update the section name from "Instruction Formats"
	to "RISC-V Instruction Formats".
---
 gas/doc/c-riscv.texi | 103 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 599b5cf..8212a17 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -17,6 +17,7 @@
 @menu
 * RISC-V-Options::        RISC-V Options
 * RISC-V-Directives::     RISC-V Directives
+* RISC-V-Modifiers::      RISC-V Assembler Modifiers
 * RISC-V-Formats::        RISC-V Instruction Formats
 * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
 @end menu
@@ -207,8 +208,108 @@ The @var{tag} is either an attribute number, or one of the following:
 
 @end table
 
+@node RISC-V-Modifiers
+@section RISC-V Assembler Modifiers
+
+RISC-V assembler supports following modifiers for relocatable address
+used in RISC-V instruction operands.  However, we also support some
+pseudo instructions to reduce the use of error-prone for these modifiers.
+
+@table @code
+@item %lo(@var{symbol})
+The low 12-bit of absolute address for @var{symbol}.
+
+@item %hi(@var{symbol})
+The high 20-bit of absolute address for @var{symbol}.  This is usually
+used with the %lo to represent a 32-bit absolute address.
+
+@smallexample
+	lui             a0, %hi(@var{symbol})     // R_RISCV_HI20
+	addi/load/store a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I/S
+@end smallexample
+
+@item %pcrel_lo(@var{label})
+The low 12-bit of relative address between pc and @var{symbol}.
+The @var{symbol} is related to the high part instrcution which marked
+by @var{label}.
+
+@item %pcrel_hi(@var{symbol})
+The high 20-bit of relative address between pc and @var{symbol}.
+This is usually used with the %pcrel_lo to represent a 4GB pc-relative range.
+
+@smallexample
+@var{label}:
+	auipc           a0, %pcrel_hi(@var{symbol})    // R_RISCV_PCREL_HI20
+	addi/load/store a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I/S
+@end smallexample
+
+Or you can use the pseudo lla/lw/sw/... instruction to do this.
+
+@smallexample
+	lla  a0, @var{symbol}
+@end smallexample
+
+@item %tprel_add(@var{symbol}
+This is used purely to associate the R_RISCV_TPREL_ADD relocation for
+TLS relaxation.
+
+@item %tprel_lo(@var{symbol})
+The low 12-bit of relative address between tp and @var{symbol}
+
+@item %tprel_hi(@var{symbol})
+The high 20-bit of relative address between tp and @var{symbol}.  This is
+usually used with the %tprel_lo and %tprel_add to access the thread local
+variable @var{symbol} in TLS Local Exec.
+
+@smallexample
+	lui        a5, %tprel_hi(@var{symbol})          // R_RISCV_TPREL_HI20
+	add        a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD
+	load/store t0, %tprel_lo(@var{symbol})(a5)      // R_RISCV_TPREL_LO12_I/S
+@end smallexample
+
+@item %tls_ie_pcrel_hi(@var{symbol})
+The high 20-bit of relative address between pc and GOT entry.  It is usually
+used with the %pcrel_lo to access the thread local variable @var{symbol} in
+TLS Inital Exec.
+
+@smallexample
+	la.tls.ie  a5, @var{symbol}
+	add        a5, a5, tp
+	load/store t0, 0(a5)
+@end smallexample
+
+The pseudo la.tls.ie instruction can be expended to
+
+@smallexample
+@var{label}:
+	auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20
+	ld/lw a5, %pcrel_lo(@var{label})(a5)     // R_RISCV_PCREL_LO12_I/S
+@end smallexample
+
+@item %tls_gd_pcrel_hi(@var{symbol})
+The high 20-bit of relative address between pc and GOT entry.  It is usually
+used with the %pcrel_lo to access the thread local variable @var{symbol} in
+TLS Global Dynamic.
+
+@smallexample
+	la.tls.gd  a0, @var{symbol}
+	call       __tls_get_addr@@plt
+	mv         a5, a0
+	load/store t0, 0(a5)
+@end smallexample
+
+The pseudo la.tls.gd instruction can be expended to
+
+@smallexample
+@var{label}:
+	auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20
+	addi  a0, a0, %pcrel_lo(@var{label})     // R_RISCV_PCREL_LO12_I/S
+@end smallexample
+
+@end table
+
 @node RISC-V-Formats
-@section Instruction Formats
+@section RISC-V Instruction Formats
 @cindex instruction formats, risc-v
 @cindex RISC-V instruction formats
 
-- 
2.7.4

Re: [PATCH 1/2] RISC-V: Add description for RISC-V Modifiers to as doc.

[Jim Wilson]

On Tue, Mar 3, 2020 at 2:22 AM Nelson Chu <nelson.chu@sifive.com> wrote:

Overall I think this looks good, it just needs a few typos fixed and
some improvement from a native English speaker.

> +RISC-V assembler supports following modifiers for relocatable address

I'd suggest "The RISC-V assembler supports the following modifiers for
relocatable addresses".

> +used in RISC-V instruction operands.  However, we also support some
> +pseudo instructions to reduce the use of error-prone for these modifiers.

"the use of error-prone for these modifiers" is awkward.  I'd suggest
"error-prone usage of these modifiers".  Or alternatively reword the
sentence, this could be something like "However, we also support some
pseudo instructions that are easier to use than these modifiers"

> +
> +@table @code
> +@item %lo(@var{symbol})
> +The low 12-bit of absolute address for @var{symbol}.

The general rule is that if it is an adjective if is hyphenated and
singular, but if it is a noun it is unhyphenated and plural.  At least
this is the gcc doc rule, I don't know if binutils handles it
differently.  So this should be "low 12 bits" or maybe "low 12-bit
value", but the first one is fine.

> +
> +@item %hi(@var{symbol})
> +The high 20-bit of absolute address for @var{symbol}.  This is usually
> +used with the %lo to represent a 32-bit absolute address.

"high 20 bits" but "32-bit" is correct.
"the %lo" looks awkward, I'd suggest "%lo" or "the %lo modifier"

> +
> +@smallexample
> +       lui             a0, %hi(@var{symbol})     // R_RISCV_HI20
> +       addi/load/store a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I/S
> +@end smallexample
> +
> +@item %pcrel_lo(@var{label})
> +The low 12-bit of relative address between pc and @var{symbol}.
> +The @var{symbol} is related to the high part instrcution which marked
> +by @var{label}.

12-bit -> 12 bits
instrcution -> instruction
"which marked" -> "which is marked"

> +
> +@item %pcrel_hi(@var{symbol})
> +The high 20-bit of relative address between pc and @var{symbol}.
> +This is usually used with the %pcrel_lo to represent a 4GB pc-relative range.

20-bit -> 20 bits
the %pcrel_lo -> %pcrel_lo or "the %pcrel_lo modifier"

The range is signed.  You might want to mention that, maybe use +/-2GB
instead of 4GB.

> +
> +@smallexample
> +@var{label}:
> +       auipc           a0, %pcrel_hi(@var{symbol})    // R_RISCV_PCREL_HI20
> +       addi/load/store a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I/S
> +@end smallexample
> +
> +Or you can use the pseudo lla/lw/sw/... instruction to do this.
> +
> +@smallexample
> +       lla  a0, @var{symbol}
> +@end smallexample
> +
> +@item %tprel_add(@var{symbol}
> +This is used purely to associate the R_RISCV_TPREL_ADD relocation for
> +TLS relaxation.

This one is only valid as the fourth operand to the normally 3 operand
add instruction.  It is probably worth mentioning that.  I see you do
have an example below, but I think it should still be pointed out.

> +
> +@item %tprel_lo(@var{symbol})
> +The low 12-bit of relative address between tp and @var{symbol}

12-bit -> 12 bits

> +
> +@item %tprel_hi(@var{symbol})
> +The high 20-bit of relative address between tp and @var{symbol}.  This is
> +usually used with the %tprel_lo and %tprel_add to access the thread local
> +variable @var{symbol} in TLS Local Exec.

20-bit -> 20 bits
"the %tprel_lo and %tprel_add" -: "%tprel_lo and %tprel_add" or "the
%tprel_lo and %tprel_add modifiers"

> +
> +@smallexample
> +       lui        a5, %tprel_hi(@var{symbol})          // R_RISCV_TPREL_HI20
> +       add        a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD
> +       load/store t0, %tprel_lo(@var{symbol})(a5)      // R_RISCV_TPREL_LO12_I/S
> +@end smallexample
> +
> +@item %tls_ie_pcrel_hi(@var{symbol})
> +The high 20-bit of relative address between pc and GOT entry.  It is usually
> +used with the %pcrel_lo to access the thread local variable @var{symbol} in
> +TLS Inital Exec.

20-bit -> 20 bits
"the %pcrel_lo" -> "%pcrel_lo" or "the %pcrel_lo modifier"
Inital -> Initial

> +
> +@smallexample
> +       la.tls.ie  a5, @var{symbol}
> +       add        a5, a5, tp
> +       load/store t0, 0(a5)
> +@end smallexample
> +
> +The pseudo la.tls.ie instruction can be expended to
> +
> +@smallexample
> +@var{label}:
> +       auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20
> +       ld/lw a5, %pcrel_lo(@var{label})(a5)     // R_RISCV_PCREL_LO12_I/S
> +@end smallexample
> +
> +@item %tls_gd_pcrel_hi(@var{symbol})
> +The high 20-bit of relative address between pc and GOT entry.  It is usually
> +used with the %pcrel_lo to access the thread local variable @var{symbol} in
> +TLS Global Dynamic.

20-bit -> 20 bits
"the %pcrel_lo" -> "%pcrel_lo" or "the %pcrel_lo modifier"

> +
> +@smallexample
> +       la.tls.gd  a0, @var{symbol}
> +       call       __tls_get_addr@@plt
> +       mv         a5, a0
> +       load/store t0, 0(a5)
> +@end smallexample
> +
> +The pseudo la.tls.gd instruction can be expended to
> +
> +@smallexample
> +@var{label}:
> +       auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20
> +       addi  a0, a0, %pcrel_lo(@var{label})     // R_RISCV_PCREL_LO12_I/S
> +@end smallexample
> +
> +@end table
> +
>  @node RISC-V-Formats
> -@section Instruction Formats
> +@section RISC-V Instruction Formats
>  @cindex instruction formats, risc-v
>  @cindex RISC-V instruction formats
>
> --
> 2.7.4
>

Jim

Re: [PATCH 2/2] RISC-V: Support assembler modifier %got_pcrel_hi.

[Jim Wilson]

On Tue, Mar 3, 2020 at 2:22 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
>         gas/
>         * config/tc-riscv.c: Support the modifier %got_pcrel_hi.
>         * doc/c-riscv.texi: Add documentation.
>         * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
>         modifier %got_pcrel_hi.
>         * testsuite/gas/riscv/no-relax-reloc.s: Likewise.
>         * testsuite/gas/riscv/relax-reloc.d: Likewise.
>         * testsuite/gas/riscv/relax-reloc.s: Likewise.

This looks good.  I'd just suggest some minor doc fixes to be
consistent with suggestions for the first patch.

> +@item %got_pcrel_hi(@var{symbol}
> +The high 20-bit of relative address between pc and the GOT entry of
> +@var{symbol}.  This is usually used with the %pcrel_lo to access the GOT entry.

20-bit -> 20 bits
"the %pcrel_lo" -> "%pcrel_lo" or "the %pcrel_lo modifier"

> +@smallexample
> +@var{label}:
> +       auipc           a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
> +       addi/load/store a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I/S
> +@end smallexample
> +
> +Also, the pseudo la instruction with PIC has the similar behavior.

"the similar" -> "similar" or "the same"

Jim

Re: [PATCH 2/2] RISC-V: Support assembler modifier %got_pcrel_hi.

[Fangrui Song]

On 2020-03-03, Jim Wilson wrote:
>On Tue, Mar 3, 2020@2:22 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>>
>>         gas/
>>         * config/tc-riscv.c: Support the modifier %got_pcrel_hi.
>>         * doc/c-riscv.texi: Add documentation.
>>         * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
>>         modifier %got_pcrel_hi.
>>         * testsuite/gas/riscv/no-relax-reloc.s: Likewise.
>>         * testsuite/gas/riscv/relax-reloc.d: Likewise.
>>         * testsuite/gas/riscv/relax-reloc.s: Likewise.
>
>This looks good.  I'd just suggest some minor doc fixes to be
>consistent with suggestions for the first patch.
>
>> +@item %got_pcrel_hi(@var{symbol}
>> +The high 20-bit of relative address between pc and the GOT entry of
>> +@var{symbol}.  This is usually used with the %pcrel_lo to access the GOT entry.
>
>20-bit -> 20 bits
>"the %pcrel_lo" -> "%pcrel_lo" or "the %pcrel_lo modifier"
>
>> +@smallexample
>> +@var{label}:
>> +       auipc           a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
>> +       addi/load/store a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I/S
>> +@end smallexample
>> +
>> +Also, the pseudo la instruction with PIC has the similar behavior.
>
>"the similar" -> "similar" or "the same"
>
>Jim

What if %got_pcrel_hi refers to a STB_LOCAL symbol? For example,

auipc a0, %got_pcrel_hi(.L1)

It may be worth a test.

FWIW, llvm-mc -triple=riscv64 -filetype=obj a.s # create a R_RISCV_GOT_HI20 referencing .L1
There is no special treatment.

Re: [PATCH 2/2] RISC-V: Support assembler modifier %got_pcrel_hi.

[Nelson Chu]

Hi MaskRay,

On Wed, Mar 4, 2020 at 8:07 AM Fangrui Song <i@maskray.me> wrote:
>
> What if %got_pcrel_hi refers to a STB_LOCAL symbol? For example,
>
> auipc a0, %got_pcrel_hi(.L1)
>
> It may be worth a test.
>
> FWIW, llvm-mc -triple=riscv64 -filetype=obj a.s # create a R_RISCV_GOT_HI20 referencing .L1
> There is no special treatment.

Consider the following case tmp.s:

        .option pic
        .option norelax
        .global foo
foo:
        la a0, foo
.L1:
        auipc a0, %got_pcrel_hi(foo)
        ld a0, %pcrel_lo(.L1)(a0)
.L2:
        auipc a0, %got_pcrel_hi(.L1)
        addi a0, a0, %pcrel_lo(.L2)

        la a0, .L1

$ ~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
tmp.s -o tmp.o
$ ~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-objdump
-dr tmp.o

tmp.o:     file format elf64-littleriscv


Disassembly of section .text:

0000000000000000 <foo>:
   0:   00000517                auipc   a0,0x0
                        0: R_RISCV_GOT_HI20     foo
   4:   00053503                ld      a0,0(a0) # 0 <foo>
                        4: R_RISCV_PCREL_LO12_I .L0

0000000000000008 <.L1>:
   8:   00000517                auipc   a0,0x0
                        8: R_RISCV_GOT_HI20     foo
   c:   00053503                ld      a0,0(a0) # 8 <.L1>
                        c: R_RISCV_PCREL_LO12_I .L1

0000000000000010 <.L2>:
  10:   00000517                auipc   a0,0x0
                        10: R_RISCV_GOT_HI20    .L1
  14:   00050513                mv      a0,a0
                        14: R_RISCV_PCREL_LO12_I        .L2
  18:   00000517                auipc   a0,0x0
                        18: R_RISCV_GOT_HI20    .L1
  1c:   00053503                ld      a0,0(a0) # 18 <.L2+0x8>
                        1c: R_RISCV_PCREL_LO12_I        .L0

`foo` is a global symbol.  `.L1` and `.L2` are local symbols.  I think
the current upstream GNU assembler treats them all the same for LA
macro with pic and %got_pcrel_hi.  So yes, the behavior should be the
same as llvm-mc.  BTW I get the same result for the linux toolchain.

Thanks
Nelson