From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Nelson Chu <nelson@rivosinc.com>
Cc: Jan Beulich <jbeulich@suse.com>, binutils@sourceware.org
Subject: Re: [PATCH 2/2] RISC-V: Better support for long instructions
Date: Fri, 25 Nov 2022 11:33:11 +0900 [thread overview]
Message-ID: <1d6c238d-883b-85db-2f5d-b3d186c8163f@irq.a4lg.com> (raw)
In-Reply-To: <CAPpQWtB=Q2i5k0q9OQgPBYx_jeDpmCmOnQw40bZx8fKgJtvM=g@mail.gmail.com>
On 2022/11/25 10:38, Nelson Chu wrote:
> On Wed, Nov 23, 2022 at 4:40 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>>
>> Nelson assigned you as the person who makes the final judgement for this
>> series and I want to hear your thoughts/decision about PATCH v2 2/2.
>
> I'm not a natural language speaker, so I thought this should be a
> little bit of a misunderstanding. "Assigned" isn't a suitable word
> here, Jan is one of the global binutils maintainers, so he definitely
Yes. After sending the message, I noticed that I used a "too strong"
word here. Nelson's understandings are correct and thanks for your support.
I just submitted the PATCH v3 and I hope that Jan likes it.
Thanks,
Tsukasa
> has the right to approve anything by himself, including the target
> stuff. Not only for these two patches, I will definitely respect all
> of his suggestions, just like he always respects the decision from
> target maintainers. Therefore, I am glad he has time to help review
> and do lots of risc-v stuff, and also thanks to everyone who helped
> risc-v, of course including you :)
>
> Thanks
> Nelson
>
next prev parent reply other threads:[~2022-11-25 2:33 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-19 7:10 [PATCH 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-19 7:10 ` [PATCH 1/2] RISC-V: Make .insn tests stricter Tsukasa OI
2022-11-21 7:32 ` Jan Beulich
2022-11-23 8:20 ` Tsukasa OI
2022-11-23 8:56 ` Jan Beulich
2022-11-19 7:10 ` [PATCH 2/2] RISC-V: Better support for long instructions Tsukasa OI
2022-11-21 7:37 ` Jan Beulich
2022-11-23 8:40 ` Tsukasa OI
2022-11-23 8:44 ` Jan Beulich
2022-11-23 8:51 ` Tsukasa OI
2022-11-25 1:38 ` Nelson Chu
2022-11-25 2:33 ` Tsukasa OI [this message]
2022-11-22 0:43 ` [PATCH 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Nelson Chu
2022-11-23 8:30 ` [PATCH v2 " Tsukasa OI
2022-11-23 8:30 ` [PATCH v2 1/2] RISC-V: Make .insn tests stricter Tsukasa OI
2022-11-23 8:30 ` [PATCH v2 2/2] RISC-V: Better support for long instructions Tsukasa OI
2022-11-23 9:04 ` Jan Beulich
2022-11-24 2:34 ` Tsukasa OI
2022-11-24 7:31 ` Jan Beulich
2022-11-24 7:35 ` Tsukasa OI
2022-11-25 2:17 ` [PATCH v3 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 2:17 ` [PATCH v3 1/2] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 8:03 ` Jan Beulich
2022-11-25 2:17 ` [PATCH v3 2/2] RISC-V: Better support for long instructions (assembler) Tsukasa OI
2022-11-25 8:15 ` Jan Beulich
2022-11-25 8:39 ` Tsukasa OI
2022-11-25 9:04 ` Jan Beulich
2022-11-25 9:18 ` Tsukasa OI
2022-11-25 9:56 ` Jan Beulich
2022-11-25 11:07 ` Tsukasa OI
2022-11-25 11:41 ` [PATCH v3 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 11:41 ` [PATCH v3 1/3] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 1/3] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 2/3] RISC-V: Better support for long instructions (assembler) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 3/3] RISC-V: Better support for long instructions (tests) Tsukasa OI
2022-11-25 13:08 ` [PATCH v4 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Jan Beulich
2022-11-28 1:53 ` Nelson Chu
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