From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>
Subject: Re: [PATCH 1/2] RISC-V: Make .insn tests stricter
Date: Wed, 23 Nov 2022 17:20:08 +0900 [thread overview]
Message-ID: <5ae888a2-70d6-707b-7e3d-b6e055004479@irq.a4lg.com> (raw)
In-Reply-To: <6a9c59f1-ff0b-45b9-c4cc-d795b93a5c9f@suse.com>
On 2022/11/21 16:32, Jan Beulich wrote:
> On 19.11.2022 08:10, Tsukasa OI wrote:
>> To make sure that all instruction bits are dumped through ".byte", this
>> commit makes matching patterns stricter (to cover all instruction bits).
>
> Hmm, it was deliberate to omit the .<n>byte part of the disassembly,
> very specifically because of the inconsistency of using <n> only in
> some cases. Personally I would agree with such tightening of the
> expectations only if the disassembler was first improved. But of
> course it's the maintainers judgement ...
>
> Jan
Hi,
I can agree most of your opinion except... even if we fix this
inconsistency later (I won't, though), I think we can change the tests
once we have changed the disassembler. So I don't find any problems
making tests tighter.
Nelson assigned you as the person who makes the final judgement and I
want to hear your thoughts/decision about PATCH 1/2.
p.s.
I made a small change to PATCH 2/2 and I'll reply your feedback to PATCH
2/2 after PATCH v2 is submitted (PATCH v2 1/2 is unchanged from v1).
Thanks,
Tsukasa
>
>> --- a/gas/testsuite/gas/riscv/insn-na.d
>> +++ b/gas/testsuite/gas/riscv/insn-na.d
>> @@ -61,15 +61,15 @@ Disassembly of section .text:
>> [^:]+:[ ]+022180d7[ ]+vadd\.vv[ ]+v1,v2,v3
>> [^:]+:[ ]+0001[ ]+c\.addi[ ]+zero,0
>> [^:]+:[ ]+00000013[ ]+addi[ ]+zero,zero,0
>> -[^:]+:[ ]+001f 0000 0000[ ].*
>> -[^:]+:[ ]+0000003f 00000000[ ].*
>> -[^:]+:[ ]+007f 0000 0000 0000 0000[ ]+[._a-z].*
>> -[^:]+:[ ]+0000107f 00000000 00000000[ ]+[._a-z].*
>> -[^:]+:[ ]+607f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000[ ]+[._a-z].*
>> +[^:]+:[ ]+001f 0000 0000[ ]+\.byte[ ]+0x1f, 0x00, 0x00, 0x00, 0x00, 0x00
>> +[^:]+:[ ]+0000003f 00000000[ ]+\.8byte[ ]+0x3f
>> +[^:]+:[ ]+007f 0000 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>> +[^:]+:[ ]+0000107f 00000000 00000000[ ]+\.byte[ ]+0x7f, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>> +[^:]+:[ ]+607f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>> [^:]+:[ ]+0001[ ]+c\.addi[ ]+zero,0
>> [^:]+:[ ]+00000013[ ]+addi[ ]+zero,zero,0
>> -[^:]+:[ ]+001f 0000 0000[ ].*
>> -[^:]+:[ ]+0000003f 00000000[ ].*
>> -[^:]+:[ ]+007f 0000 0000 0000 0000[ ]+[._a-z].*
>> -[^:]+:[ ]+0000107f 00000000 00000000[ ]+[._a-z].*
>> -[^:]+:[ ]+607f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000[ ]+[._a-z].*
>> +[^:]+:[ ]+001f 0000 0000[ ]+\.byte[ ]+0x1f, 0x00, 0x00, 0x00, 0x00, 0x00
>> +[^:]+:[ ]+0000003f 00000000[ ]+\.8byte[ ]+0x3f
>> +[^:]+:[ ]+007f 0000 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>> +[^:]+:[ ]+0000107f 00000000 00000000[ ]+\.byte[ ]+0x7f, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>> +[^:]+:[ ]+607f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>> diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
>> index 2e5d35b39702..cf84f177af39 100644
>> --- a/gas/testsuite/gas/riscv/insn.d
>> +++ b/gas/testsuite/gas/riscv/insn.d
>> @@ -83,12 +83,12 @@ Disassembly of section .text:
>> [^:]+:[ ]+0000 0000 0000 ?
>> [^:]+:[ ]+0001[ ]+nop
>> [^:]+:[ ]+00000013[ ]+nop
>> -[^:]+:[ ]+001f 0000 0000[ ].*
>> -[^:]+:[ ]+0000003f 00000000[ ].*
>> -[^:]+:[ ]+007f 0000 0000 0000[ ]+[._a-z].*
>> +[^:]+:[ ]+001f 0000 0000[ ]+\.byte[ ]+0x1f, 0x00, 0x00, 0x00, 0x00, 0x00
>> +[^:]+:[ ]+0000003f 00000000[ ]+\.8byte[ ]+0x3f
>> +[^:]+:[ ]+007f 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>> [^:]+:[ ]+0000 ?
>> -[^:]+:[ ]+0000107f 00000000[ ]+[._a-z].*
>> +[^:]+:[ ]+0000107f 00000000[ ]+\.byte[ ]+0x7f, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>> [^:]+:[ ]+00000000 ?
>> -[^:]+:[ ]+607f 0000 0000 0000[ ]+[._a-z].*
>> +[^:]+:[ ]+607f 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>> [^:]+:[ ]+0000 0000 0000 0000 ?
>> [^:]+:[ ]+0000 0000 0000 ?
>
next prev parent reply other threads:[~2022-11-23 8:20 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-19 7:10 [PATCH 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-19 7:10 ` [PATCH 1/2] RISC-V: Make .insn tests stricter Tsukasa OI
2022-11-21 7:32 ` Jan Beulich
2022-11-23 8:20 ` Tsukasa OI [this message]
2022-11-23 8:56 ` Jan Beulich
2022-11-19 7:10 ` [PATCH 2/2] RISC-V: Better support for long instructions Tsukasa OI
2022-11-21 7:37 ` Jan Beulich
2022-11-23 8:40 ` Tsukasa OI
2022-11-23 8:44 ` Jan Beulich
2022-11-23 8:51 ` Tsukasa OI
2022-11-25 1:38 ` Nelson Chu
2022-11-25 2:33 ` Tsukasa OI
2022-11-22 0:43 ` [PATCH 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Nelson Chu
2022-11-23 8:30 ` [PATCH v2 " Tsukasa OI
2022-11-23 8:30 ` [PATCH v2 1/2] RISC-V: Make .insn tests stricter Tsukasa OI
2022-11-23 8:30 ` [PATCH v2 2/2] RISC-V: Better support for long instructions Tsukasa OI
2022-11-23 9:04 ` Jan Beulich
2022-11-24 2:34 ` Tsukasa OI
2022-11-24 7:31 ` Jan Beulich
2022-11-24 7:35 ` Tsukasa OI
2022-11-25 2:17 ` [PATCH v3 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 2:17 ` [PATCH v3 1/2] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 8:03 ` Jan Beulich
2022-11-25 2:17 ` [PATCH v3 2/2] RISC-V: Better support for long instructions (assembler) Tsukasa OI
2022-11-25 8:15 ` Jan Beulich
2022-11-25 8:39 ` Tsukasa OI
2022-11-25 9:04 ` Jan Beulich
2022-11-25 9:18 ` Tsukasa OI
2022-11-25 9:56 ` Jan Beulich
2022-11-25 11:07 ` Tsukasa OI
2022-11-25 11:41 ` [PATCH v3 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 11:41 ` [PATCH v3 1/3] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 1/3] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 2/3] RISC-V: Better support for long instructions (assembler) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 3/3] RISC-V: Better support for long instructions (tests) Tsukasa OI
2022-11-25 13:08 ` [PATCH v4 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Jan Beulich
2022-11-28 1:53 ` Nelson Chu
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