From: Jan Beulich <jbeulich@suse.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>
Subject: Re: [PATCH 2/2] RISC-V: Better support for long instructions
Date: Wed, 23 Nov 2022 09:44:45 +0100 [thread overview]
Message-ID: <621c26e6-2d72-26f5-b6d4-efd9523a9d2f@suse.com> (raw)
In-Reply-To: <133194e3-cde8-ac92-6e31-c3be609e352b@irq.a4lg.com>
On 23.11.2022 09:40, Tsukasa OI wrote:
> c.f. PATCH v2 2/2
> <https://sourceware.org/pipermail/binutils/2022-November/124598.html>
>
> On 2022/11/21 16:37, Jan Beulich wrote:
>> On 19.11.2022 08:10, Tsukasa OI wrote:
>>> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>>>
>>> Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit
>>> instructions with .insn") tried to start supporting long instructions but
>>> it was insufficient.
>>>
>>> 1. It heavily depended on the bignum internals (radix of 2^16),
>>> 2. It generates "value conflicts with instruction length" even if a big
>>> number instruction encoding does not exceed its expected length,
>>> 3. Because long opcode was handled separately (from struct riscv_cl_insn),
>>> some information like DWARF line number correspondence was missing and
>>> 4. On the disassembler, disassembler dump was limited up to 64-bit.
>>> For long (unknown) instructions, instruction bits are incorrectly
>>> zeroed out.
>>
>> Just FTR - of these 1 and 4 were deliberate (as in: deemed acceptable), the
>> former the keep the code reasonably simple and the latter because focus was
>> solely on the assembler.
>
> I thought it's possible that 1 was a deliberate choice. I don't want to
> depend on some internal structure that could change easily (as long as
> this is a reasonable choice). To be honest, I didn't like my
> "extracting prefix of an instruction" logic in PATCH v1 but I found a
> good function: generic_bignum_to_int32 and decided use it on PATCH v2
> (as a result, PATCH v2 2/2 is a bit simpler than PATCH v1).
FAOD by saying "deliberate" I have by no means meant to say that I'm not
happy to see you improve the state of things. I was merely trying to give
some background.
Jan
> For 4, resolving from the start would be better but since my current
> focus is the RISC-V disassembler, I'm happy to resolve it (fortunately,
> it didn't require large changes).
>
> Nelson assigned you as the person who makes the final judgement for this
> series and I want to hear your thoughts/decision about PATCH v2 2/2.
>
> Thanks,
> Tsukasa
next prev parent reply other threads:[~2022-11-23 8:44 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-19 7:10 [PATCH 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-19 7:10 ` [PATCH 1/2] RISC-V: Make .insn tests stricter Tsukasa OI
2022-11-21 7:32 ` Jan Beulich
2022-11-23 8:20 ` Tsukasa OI
2022-11-23 8:56 ` Jan Beulich
2022-11-19 7:10 ` [PATCH 2/2] RISC-V: Better support for long instructions Tsukasa OI
2022-11-21 7:37 ` Jan Beulich
2022-11-23 8:40 ` Tsukasa OI
2022-11-23 8:44 ` Jan Beulich [this message]
2022-11-23 8:51 ` Tsukasa OI
2022-11-25 1:38 ` Nelson Chu
2022-11-25 2:33 ` Tsukasa OI
2022-11-22 0:43 ` [PATCH 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Nelson Chu
2022-11-23 8:30 ` [PATCH v2 " Tsukasa OI
2022-11-23 8:30 ` [PATCH v2 1/2] RISC-V: Make .insn tests stricter Tsukasa OI
2022-11-23 8:30 ` [PATCH v2 2/2] RISC-V: Better support for long instructions Tsukasa OI
2022-11-23 9:04 ` Jan Beulich
2022-11-24 2:34 ` Tsukasa OI
2022-11-24 7:31 ` Jan Beulich
2022-11-24 7:35 ` Tsukasa OI
2022-11-25 2:17 ` [PATCH v3 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 2:17 ` [PATCH v3 1/2] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 8:03 ` Jan Beulich
2022-11-25 2:17 ` [PATCH v3 2/2] RISC-V: Better support for long instructions (assembler) Tsukasa OI
2022-11-25 8:15 ` Jan Beulich
2022-11-25 8:39 ` Tsukasa OI
2022-11-25 9:04 ` Jan Beulich
2022-11-25 9:18 ` Tsukasa OI
2022-11-25 9:56 ` Jan Beulich
2022-11-25 11:07 ` Tsukasa OI
2022-11-25 11:41 ` [PATCH v3 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 11:41 ` [PATCH v3 1/3] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 1/3] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 2/3] RISC-V: Better support for long instructions (assembler) Tsukasa OI
2022-11-25 11:42 ` [PATCH v4 3/3] RISC-V: Better support for long instructions (tests) Tsukasa OI
2022-11-25 13:08 ` [PATCH v4 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Jan Beulich
2022-11-28 1:53 ` Nelson Chu
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