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From: Jan Beulich <jbeulich@suse.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>
Subject: Re: [PATCH v3 1/2] RISC-V: Better support for long instructions (disassembler)
Date: Fri, 25 Nov 2022 09:03:13 +0100	[thread overview]
Message-ID: <79b8472b-579b-8253-a572-da1b8bf123e6@suse.com> (raw)
In-Reply-To: <66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com>

On 25.11.2022 03:17, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit
> instructions with .insn") tried to start supporting long instructions but
> it was insufficient.
> 
> 1.  On the disassembler, disassembler dump was limited up to 64-bit.
>     For long (unknown) instructions, instruction bits are incorrectly
>     zeroed out.
> 
> To solve these problems, this commit adds packet argument to support dumping
> instructions longer than 64-bits.  This commit will be tested on the next
> commit "RISC-V: Better support for long instructions (assembler)".
> 
> opcodes/ChangeLog:
> 
> 	* riscv-dis.c (riscv_disassemble_insn): Print unknown instruction
> 	using the new argument packet.
> 	(riscv_disassemble_data): Add unused argument packet.
> 	(print_insn_riscv): Pass packet to the disassemble function.

Looks okay to me; just one style nit:

> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -641,7 +641,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
>     this is little-endian code.  */
>  
>  static int
> -riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
> +riscv_disassemble_insn (bfd_vma memaddr,
> +			insn_t word,
> +			const bfd_byte *packet,

Just like you have it here, please add ...

> @@ -1037,7 +1040,7 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
>    bfd_vma dump_size;
>    int status;
>    enum riscv_seg_mstate mstate;
> -  int (*riscv_disassembler) (bfd_vma, insn_t, struct disassemble_info *);
> +  int (*riscv_disassembler) (bfd_vma, insn_t, const bfd_byte*, struct disassemble_info *);

... a blank before * here. I guess you will also want to wrap this
(now long) line.

No need to submit a v4 just for that, i.e. feel free to simply commit
with the adjustment (after giving Nelson a little bit of time, just
in case).

Jan

  reply	other threads:[~2022-11-25  8:03 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-19  7:10 [PATCH 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-19  7:10 ` [PATCH 1/2] RISC-V: Make .insn tests stricter Tsukasa OI
2022-11-21  7:32   ` Jan Beulich
2022-11-23  8:20     ` Tsukasa OI
2022-11-23  8:56       ` Jan Beulich
2022-11-19  7:10 ` [PATCH 2/2] RISC-V: Better support for long instructions Tsukasa OI
2022-11-21  7:37   ` Jan Beulich
2022-11-23  8:40     ` Tsukasa OI
2022-11-23  8:44       ` Jan Beulich
2022-11-23  8:51         ` Tsukasa OI
2022-11-25  1:38       ` Nelson Chu
2022-11-25  2:33         ` Tsukasa OI
2022-11-22  0:43 ` [PATCH 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Nelson Chu
2022-11-23  8:30 ` [PATCH v2 " Tsukasa OI
2022-11-23  8:30   ` [PATCH v2 1/2] RISC-V: Make .insn tests stricter Tsukasa OI
2022-11-23  8:30   ` [PATCH v2 2/2] RISC-V: Better support for long instructions Tsukasa OI
2022-11-23  9:04     ` Jan Beulich
2022-11-24  2:34       ` Tsukasa OI
2022-11-24  7:31         ` Jan Beulich
2022-11-24  7:35           ` Tsukasa OI
2022-11-25  2:17   ` [PATCH v3 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25  2:17     ` [PATCH v3 1/2] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25  8:03       ` Jan Beulich [this message]
2022-11-25  2:17     ` [PATCH v3 2/2] RISC-V: Better support for long instructions (assembler) Tsukasa OI
2022-11-25  8:15       ` Jan Beulich
2022-11-25  8:39         ` Tsukasa OI
2022-11-25  9:04           ` Jan Beulich
2022-11-25  9:18             ` Tsukasa OI
2022-11-25  9:56               ` Jan Beulich
2022-11-25 11:07                 ` Tsukasa OI
2022-11-25 11:41     ` [PATCH v3 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 11:41       ` [PATCH v3 1/3] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 11:42     ` [PATCH v4 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Tsukasa OI
2022-11-25 11:42       ` [PATCH v4 1/3] RISC-V: Better support for long instructions (disassembler) Tsukasa OI
2022-11-25 11:42       ` [PATCH v4 2/3] RISC-V: Better support for long instructions (assembler) Tsukasa OI
2022-11-25 11:42       ` [PATCH v4 3/3] RISC-V: Better support for long instructions (tests) Tsukasa OI
2022-11-25 13:08       ` [PATCH v4 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Jan Beulich
2022-11-28  1:53         ` Nelson Chu

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