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From: jiawei <jiawei@iscas.ac.cn>
To: binutils@sourceware.org
Cc: kito.cheng@sifive.com, nelson.chu@sifive.com, jimw@sifive.com,
	philipp.tomsich@vrull.eu, mjos@pqshield.com,
	ben.marshall@pqshield.com, cmuellner@ventanamicro.com,
	palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com,
	siyu@isrc.iscas.ac.cn, schwab@linux-m68k.org, jbeulich@suse.com,
	jiawei <jiawei@iscas.ac.cn>
Subject: [PATCH v4 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
Date: Mon, 15 Nov 2021 11:03:43 +0800	[thread overview]
Message-ID: <20211115030343.276103-4-jiawei@iscas.ac.cn> (raw)
In-Reply-To: <20211115030343.276103-1-jiawei@iscas.ac.cn>

Add testcases for Scalar Crypto extension, with total testcase contain all instructions  in k-ext/k-ext-64 and sub-extension testcase for zbk* zk*. Also add testcase for new CSR name 'seed' which is the Entropy Source in zkr.
---
 gas/testsuite/gas/riscv/k-ext-64.d            | 47 +++++++++++++++++++
 gas/testsuite/gas/riscv/k-ext-64.s            | 38 +++++++++++++++
 gas/testsuite/gas/riscv/k-ext.d               | 44 +++++++++++++++++
 gas/testsuite/gas/riscv/k-ext.s               | 35 ++++++++++++++
 .../gas/riscv/priv-reg-fail-version-1p10.d    |  2 +-
 .../gas/riscv/priv-reg-fail-version-1p11.d    |  2 +-
 .../gas/riscv/priv-reg-fail-version-1p9p1.d   |  2 +-
 .../gas/riscv/priv-reg-version-1p10.d         |  1 +
 .../gas/riscv/priv-reg-version-1p11.d         |  1 +
 .../gas/riscv/priv-reg-version-1p9p1.d        |  1 +
 gas/testsuite/gas/riscv/priv-reg.s            |  3 ++
 gas/testsuite/gas/riscv/zbkb-32.d             | 22 +++++++++
 gas/testsuite/gas/riscv/zbkb-32.s             | 13 +++++
 gas/testsuite/gas/riscv/zbkb-64.d             | 24 ++++++++++
 gas/testsuite/gas/riscv/zbkb-64.s             | 15 ++++++
 gas/testsuite/gas/riscv/zbkc-32.d             | 12 +++++
 gas/testsuite/gas/riscv/zbkc-64.d             | 12 +++++
 gas/testsuite/gas/riscv/zbkc.s                |  3 ++
 gas/testsuite/gas/riscv/zbkx-32.d             | 12 +++++
 gas/testsuite/gas/riscv/zbkx-64.d             | 12 +++++
 gas/testsuite/gas/riscv/zbkx.s                |  3 ++
 gas/testsuite/gas/riscv/zknd-32.d             | 12 +++++
 gas/testsuite/gas/riscv/zknd-32.s             |  3 ++
 gas/testsuite/gas/riscv/zknd-64.d             | 15 ++++++
 gas/testsuite/gas/riscv/zknd-64.s             |  6 +++
 gas/testsuite/gas/riscv/zkne-32.d             | 12 +++++
 gas/testsuite/gas/riscv/zkne-32.s             |  3 ++
 gas/testsuite/gas/riscv/zkne-64.d             | 14 ++++++
 gas/testsuite/gas/riscv/zkne-64.s             |  5 ++
 gas/testsuite/gas/riscv/zknh-32.d             | 20 ++++++++
 gas/testsuite/gas/riscv/zknh-32.s             | 11 +++++
 gas/testsuite/gas/riscv/zknh-64.d             | 18 +++++++
 gas/testsuite/gas/riscv/zknh-64.s             |  9 ++++
 gas/testsuite/gas/riscv/zksed-32.d            | 12 +++++
 gas/testsuite/gas/riscv/zksed-64.d            | 12 +++++
 gas/testsuite/gas/riscv/zksed.s               |  3 ++
 gas/testsuite/gas/riscv/zksh-32.d             | 12 +++++
 gas/testsuite/gas/riscv/zksh-64.d             | 12 +++++
 gas/testsuite/gas/riscv/zksh.s                |  3 ++
 39 files changed, 483 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
 create mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
 create mode 100644 gas/testsuite/gas/riscv/k-ext.d
 create mode 100644 gas/testsuite/gas/riscv/k-ext.s
 create mode 100644 gas/testsuite/gas/riscv/zbkb-32.d
 create mode 100644 gas/testsuite/gas/riscv/zbkb-32.s
 create mode 100644 gas/testsuite/gas/riscv/zbkb-64.d
 create mode 100644 gas/testsuite/gas/riscv/zbkb-64.s
 create mode 100644 gas/testsuite/gas/riscv/zbkc-32.d
 create mode 100644 gas/testsuite/gas/riscv/zbkc-64.d
 create mode 100644 gas/testsuite/gas/riscv/zbkc.s
 create mode 100644 gas/testsuite/gas/riscv/zbkx-32.d
 create mode 100644 gas/testsuite/gas/riscv/zbkx-64.d
 create mode 100644 gas/testsuite/gas/riscv/zbkx.s
 create mode 100644 gas/testsuite/gas/riscv/zknd-32.d
 create mode 100644 gas/testsuite/gas/riscv/zknd-32.s
 create mode 100644 gas/testsuite/gas/riscv/zknd-64.d
 create mode 100644 gas/testsuite/gas/riscv/zknd-64.s
 create mode 100644 gas/testsuite/gas/riscv/zkne-32.d
 create mode 100644 gas/testsuite/gas/riscv/zkne-32.s
 create mode 100644 gas/testsuite/gas/riscv/zkne-64.d
 create mode 100644 gas/testsuite/gas/riscv/zkne-64.s
 create mode 100644 gas/testsuite/gas/riscv/zknh-32.d
 create mode 100644 gas/testsuite/gas/riscv/zknh-32.s
 create mode 100644 gas/testsuite/gas/riscv/zknh-64.d
 create mode 100644 gas/testsuite/gas/riscv/zknh-64.s
 create mode 100644 gas/testsuite/gas/riscv/zksed-32.d
 create mode 100644 gas/testsuite/gas/riscv/zksed-64.d
 create mode 100644 gas/testsuite/gas/riscv/zksed.s
 create mode 100644 gas/testsuite/gas/riscv/zksh-32.d
 create mode 100644 gas/testsuite/gas/riscv/zksh-64.d
 create mode 100644 gas/testsuite/gas/riscv/zksh.s

diff --git a/gas/testsuite/gas/riscv/k-ext-64.d b/gas/testsuite/gas/riscv/k-ext-64.d
new file mode 100644
index 00000000000..06f47566ac8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext-64.d
@@ -0,0 +1,47 @@
+#as: -march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
+#source: k-ext-64.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+.*:[ 	]+.*[ 	]+rorw[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+rolw[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+roriw[ 	]+a0,a1,0x2
+[ 	]+.*:[ 	]+.*[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+pack[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+packh[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+packw[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+brev8[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+rev8[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+clmul[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+clmulh[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+xperm4[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+xperm8[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+aes64ds[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+aes64dsm[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+aes64im[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+aes64ks1i[ 	]+a0,a1,0x4
+[ 	]+.*:[ 	]+.*[ 	]+aes64ks2[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+aes64es[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+aes64esm[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha256sig0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sig1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sum0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sum1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha512sum0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha512sum1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sm4ed[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+sm4ks[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+sm3p0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sm3p1[ 	]+a0,a0
diff --git a/gas/testsuite/gas/riscv/k-ext-64.s b/gas/testsuite/gas/riscv/k-ext-64.s
new file mode 100644
index 00000000000..302b82ea005
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext-64.s
@@ -0,0 +1,38 @@
+target:
+        ror     a0, a1, a2
+        rol     a0, a1, a2
+        rori    a0, a1, 2
+        rorw    a0, a1, a2
+        rolw    a0, a1, a2
+        roriw   a0, a1, 2
+        andn    a0, a1, a2
+        orn     a0, a1, a2
+        xnor    a0, a1, a2
+        pack    a0, a1, a2
+        packh   a0, a1, a2
+        packw   a0, a1, a2
+        brev8   a0, a0
+        rev8    a0, a0
+        clmul   a0, a1, a2
+        clmulh  a0, a1, a2
+        xperm4  a0, a1, a2
+        xperm8  a0, a1, a2
+        aes64ds     a0, a1, a2
+        aes64dsm    a0, a1, a2
+        aes64im     a0, a0
+        aes64ks1i   a0, a1, 4
+        aes64ks2    a0, a1, a2
+        aes64es     a0, a1, a2
+        aes64esm    a0, a1, a2
+        sha256sig0  a0, a0
+        sha256sig1  a0, a0
+        sha256sum0  a0, a0
+        sha256sum1  a0, a0
+        sha512sig0  a0, a0
+        sha512sig1  a0, a0
+        sha512sum0  a0, a0
+        sha512sum1  a0, a0
+        sm4ed   a0, a1, a2, 2
+        sm4ks   a0, a1, a2, 2
+        sm3p0   a0, a0
+        sm3p1   a0, a0
diff --git a/gas/testsuite/gas/riscv/k-ext.d b/gas/testsuite/gas/riscv/k-ext.d
new file mode 100644
index 00000000000..3ba65aadc74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext.d
@@ -0,0 +1,44 @@
+#as: -march=rv32i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
+#source: k-ext.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+.*:[ 	]+.*[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+pack[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+packh[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+brev8[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+rev8[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+zip[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+unzip[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+clmul[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+clmulh[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+xperm4[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+xperm8[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+aes32dsi[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+aes32dsmi[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+aes32esi[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+aes32esmi[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+sha256sig0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sig1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sum0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sum1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig0h[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig0l[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig1h[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig1l[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha512sum0r[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha512sum1r[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sm4ed[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+sm4ks[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+sm3p0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sm3p1[ 	]+a0,a0
diff --git a/gas/testsuite/gas/riscv/k-ext.s b/gas/testsuite/gas/riscv/k-ext.s
new file mode 100644
index 00000000000..8eb27684710
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext.s
@@ -0,0 +1,35 @@
+target:
+        ror     a0, a1, a2
+        rol     a0, a1, a2
+        rori    a0, a1, 2
+        andn    a0, a1, a2
+        orn     a0, a1, a2
+        xnor    a0, a1, a2
+        pack    a0, a1, a2
+        packh   a0, a1, a2
+        brev8   a0, a0
+        rev8    a0, a0
+        zip     a0, a0
+        unzip   a0, a0
+        clmul   a0, a1, a2
+        clmulh  a0, a1, a2
+        xperm4  a0, a1, a2
+        xperm8  a0, a1, a2
+        aes32dsi    a0, a1, a2, 2
+        aes32dsmi   a0, a1, a2, 2
+        aes32esi    a0, a1, a2, 2
+        aes32esmi   a0, a1, a2, 2
+        sha256sig0  a0, a0
+        sha256sig1  a0, a0
+        sha256sum0  a0, a0
+        sha256sum1  a0, a0
+        sha512sig0h    a0, a1, a2
+        sha512sig0l    a0, a1, a2
+        sha512sig1h    a0, a1, a2
+        sha512sig1l    a0, a1, a2
+        sha512sum0r    a0, a1, a2
+        sha512sum1r    a0, a1, a2
+        sm4ed   a0, a1, a2, 2
+        sm4ks   a0, a1, a2, 2
+        sm3p0   a0, a0
+        sm3p1   a0, a0
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
index 07cf05a9c29..5f2a387e0e0 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 -march-attr
+#as: -march=rv32ifzkr -mcsr-check -mpriv-spec=1.10 -march-attr
 #source: priv-reg.s
 #warning_output: priv-reg-fail-version-1p10.l
 #readelf: -A
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
index bf4b1db3ed6..5b13b2f8edc 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 -march-attr
+#as: -march=rv32ifzkr -mcsr-check -mpriv-spec=1.11 -march-attr
 #source: priv-reg.s
 #warning_output: priv-reg-fail-version-1p11.l
 #readelf: -A
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
index e2c33d81dc8..c5d413a5129 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 -march-attr
+#as: -march=rv32ifzkr -mcsr-check -mpriv-spec=1.9.1 -march-attr
 #source: priv-reg.s
 #warning_output: priv-reg-fail-version-1p9p1.l
 #readelf: -A
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
index 3ad8eebe851..78c683d3dea 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
 [     	]+[0-9a-f]+:[  	]+7a102573[    	]+csrr[        	]+a0,tdata1
 [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
 [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
+[     	]+[0-9a-f]+:[  	]+01502573[    	]+csrr[        	]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
index 5824bc5e1f6..6c1cc70479b 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
 [     	]+[0-9a-f]+:[  	]+7a102573[    	]+csrr[        	]+a0,tdata1
 [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
 [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
+[     	]+[0-9a-f]+:[  	]+01502573[    	]+csrr[        	]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
index 569b9587e29..3d2ab74eb35 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
 [     	]+[0-9a-f]+:[  	]+7a102573[    	]+csrr[        	]+a0,tdata1
 [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
 [     	]+[0-9a-f]+:[  	]+7a302573[    	]+csrr[        	]+a0,tdata3
+[     	]+[0-9a-f]+:[  	]+01502573[    	]+csrr[        	]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
index c40d28862b7..85ff2a6f466 100644
--- a/gas/testsuite/gas/riscv/priv-reg.s
+++ b/gas/testsuite/gas/riscv/priv-reg.s
@@ -282,3 +282,6 @@
 	csr etrigger		# 0x7a1, alias to tdata1
 	csr textra32		# 0x7a3, alias to tdata3
 	csr textra64		# 0x7a3, alias to tdata3
+
+	# Scalar crypto
+	csr seed		# 0x015, Entropy Source
diff --git a/gas/testsuite/gas/riscv/zbkb-32.d b/gas/testsuite/gas/riscv/zbkb-32.d
new file mode 100644
index 00000000000..75a9259c5d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-32.d
@@ -0,0 +1,22 @@
+#as: -march=rv32i_zbkb
+#source: zbkb-32.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+.*:[ 	]+.*[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+pack[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+packh[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+brev8[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+rev8[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+zip[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+unzip[ 	]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zbkb-32.s b/gas/testsuite/gas/riscv/zbkb-32.s
new file mode 100644
index 00000000000..6f917154517
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-32.s
@@ -0,0 +1,13 @@
+target:
+        ror     a0, a1, a2
+        rol     a0, a1, a2
+        rori    a0, a1, 2
+        andn    a0, a1, a2
+        orn     a0, a1, a2
+        xnor    a0, a1, a2
+        pack    a0, a1, a2
+        packh   a0, a1, a2
+        brev8   a0, a0
+        rev8    a0, a0
+        zip     a0, a0
+        unzip     a0, a0
diff --git a/gas/testsuite/gas/riscv/zbkb-64.d b/gas/testsuite/gas/riscv/zbkb-64.d
new file mode 100644
index 00000000000..2f51db19f06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-64.d
@@ -0,0 +1,24 @@
+#as: -march=rv64i_zbkb
+#source: zbkb-64.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+.*:[ 	]+.*[ 	]+rorw[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+rolw[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+roriw[ 	]+a0,a1,0x2
+[ 	]+.*:[ 	]+.*[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+pack[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+packh[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+packw[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+brev8[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+rev8[ 	]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zbkb-64.s b/gas/testsuite/gas/riscv/zbkb-64.s
new file mode 100644
index 00000000000..b5cf79f890e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-64.s
@@ -0,0 +1,15 @@
+target:
+        ror     a0, a1, a2
+        rol     a0, a1, a2
+        rori    a0, a1, 2
+        rorw    a0, a1, a2
+        rolw    a0, a1, a2
+        roriw   a0, a1, 2
+        andn    a0, a1, a2
+        orn     a0, a1, a2
+        xnor    a0, a1, a2
+        pack    a0, a1, a2
+        packh   a0, a1, a2
+        packw   a0, a1, a2
+        brev8   a0, a0
+        rev8    a0, a0
diff --git a/gas/testsuite/gas/riscv/zbkc-32.d b/gas/testsuite/gas/riscv/zbkc-32.d
new file mode 100644
index 00000000000..7052f4be451
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkc-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zbkc
+#source: zbkc.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+clmul[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+clmulh[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkc-64.d b/gas/testsuite/gas/riscv/zbkc-64.d
new file mode 100644
index 00000000000..1620ea9c8db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkc-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zbkc
+#source: zbkc.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+clmul[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+clmulh[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkc.s b/gas/testsuite/gas/riscv/zbkc.s
new file mode 100644
index 00000000000..2a987746e7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkc.s
@@ -0,0 +1,3 @@
+target:
+        clmul   a0, a1, a2
+        clmulh  a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zbkx-32.d b/gas/testsuite/gas/riscv/zbkx-32.d
new file mode 100644
index 00000000000..3306ab42e32
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkx-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zbkx
+#source: zbkx.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+xperm4[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+xperm8[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkx-64.d b/gas/testsuite/gas/riscv/zbkx-64.d
new file mode 100644
index 00000000000..95cca8e9049
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkx-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zbkx
+#source: zbkx.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+xperm4[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+xperm8[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkx.s b/gas/testsuite/gas/riscv/zbkx.s
new file mode 100644
index 00000000000..8c3077105fe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkx.s
@@ -0,0 +1,3 @@
+target:
+        xperm4  a0, a1, a2
+        xperm8  a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknd-32.d b/gas/testsuite/gas/riscv/zknd-32.d
new file mode 100644
index 00000000000..4571261e494
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zknd
+#source: zknd-32.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+aes32dsi[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+aes32dsmi[ 	]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zknd-32.s b/gas/testsuite/gas/riscv/zknd-32.s
new file mode 100644
index 00000000000..0d09badd1c6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-32.s
@@ -0,0 +1,3 @@
+target:
+        aes32dsi    a0, a1, a2, 2
+        aes32dsmi   a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zknd-64.d b/gas/testsuite/gas/riscv/zknd-64.d
new file mode 100644
index 00000000000..e12b3ef204b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-64.d
@@ -0,0 +1,15 @@
+#as: -march=rv64i_zknd
+#source: zknd-64.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+aes64ds[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+aes64dsm[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+aes64im[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+aes64ks1i[ 	]+a0,a1,0x4
+[ 	]+.*:[ 	]+.*[ 	]+aes64ks2[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zknd-64.s b/gas/testsuite/gas/riscv/zknd-64.s
new file mode 100644
index 00000000000..4846e93c16f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-64.s
@@ -0,0 +1,6 @@
+target:
+        aes64ds     a0, a1, a2
+        aes64dsm    a0, a1, a2
+        aes64im     a0, a0
+        aes64ks1i   a0, a1, 4
+        aes64ks2    a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zkne-32.d b/gas/testsuite/gas/riscv/zkne-32.d
new file mode 100644
index 00000000000..2f5735971cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zkne
+#source: zkne-32.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+aes32esi[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+aes32esmi[ 	]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zkne-32.s b/gas/testsuite/gas/riscv/zkne-32.s
new file mode 100644
index 00000000000..f864fc1778b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-32.s
@@ -0,0 +1,3 @@
+target:
+        aes32esi    a0, a1, a2, 2
+        aes32esmi   a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zkne-64.d b/gas/testsuite/gas/riscv/zkne-64.d
new file mode 100644
index 00000000000..6f6e9c31116
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-64.d
@@ -0,0 +1,14 @@
+#as: -march=rv64i_zkne
+#source: zkne-64.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+aes64es[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+aes64esm[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+aes64ks1i[ 	]+a0,a1,0x4
+[ 	]+.*:[ 	]+.*[ 	]+aes64ks2[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zkne-64.s b/gas/testsuite/gas/riscv/zkne-64.s
new file mode 100644
index 00000000000..9b5612001af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-64.s
@@ -0,0 +1,5 @@
+target:
+        aes64es     a0, a1, a2
+        aes64esm    a0, a1, a2
+        aes64ks1i   a0, a1, 4
+        aes64ks2    a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknh-32.d b/gas/testsuite/gas/riscv/zknh-32.d
new file mode 100644
index 00000000000..ac4b2447629
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-32.d
@@ -0,0 +1,20 @@
+#as: -march=rv32i_zknh
+#source: zknh-32.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+sha256sig0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sig1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sum0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sum1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig0h[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig0l[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig1h[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig1l[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha512sum0r[ 	]+a0,a1,a2
+[ 	]+.*:[ 	]+.*[ 	]+sha512sum1r[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zknh-32.s b/gas/testsuite/gas/riscv/zknh-32.s
new file mode 100644
index 00000000000..dc2cd3c6657
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-32.s
@@ -0,0 +1,11 @@
+target:
+        sha256sig0  a0, a0
+        sha256sig1  a0, a0
+        sha256sum0  a0, a0
+        sha256sum1  a0, a0
+        sha512sig0h    a0, a1, a2
+        sha512sig0l    a0, a1, a2
+        sha512sig1h    a0, a1, a2
+        sha512sig1l    a0, a1, a2
+        sha512sum0r    a0, a1, a2
+        sha512sum1r    a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknh-64.d b/gas/testsuite/gas/riscv/zknh-64.d
new file mode 100644
index 00000000000..890d5d826f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-64.d
@@ -0,0 +1,18 @@
+#as: -march=rv64i_zknh
+#source: zknh-64.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+sha256sig0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sig1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sum0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha256sum1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha512sig1[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha512sum0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sha512sum1[ 	]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zknh-64.s b/gas/testsuite/gas/riscv/zknh-64.s
new file mode 100644
index 00000000000..897dc0ba32e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-64.s
@@ -0,0 +1,9 @@
+target:
+        sha256sig0  a0, a0
+        sha256sig1  a0, a0
+        sha256sum0  a0, a0
+        sha256sum1  a0, a0
+        sha512sig0  a0, a0
+        sha512sig1  a0, a0
+        sha512sum0  a0, a0
+        sha512sum1  a0, a0
diff --git a/gas/testsuite/gas/riscv/zksed-32.d b/gas/testsuite/gas/riscv/zksed-32.d
new file mode 100644
index 00000000000..228130ae4c1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksed-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zksed
+#source: zksed.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+sm4ed[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+sm4ks[ 	]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zksed-64.d b/gas/testsuite/gas/riscv/zksed-64.d
new file mode 100644
index 00000000000..9a4efdff649
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksed-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zksed
+#source: zksed.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+sm4ed[ 	]+a0,a1,a2,0x2
+[ 	]+.*:[ 	]+.*[ 	]+sm4ks[ 	]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zksed.s b/gas/testsuite/gas/riscv/zksed.s
new file mode 100644
index 00000000000..ee95c7a8584
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksed.s
@@ -0,0 +1,3 @@
+target:
+        sm4ed   a0, a1, a2, 2
+        sm4ks   a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zksh-32.d b/gas/testsuite/gas/riscv/zksh-32.d
new file mode 100644
index 00000000000..ab22b3f1f4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksh-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zksh
+#source: zksh.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+sm3p0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sm3p1[ 	]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zksh-64.d b/gas/testsuite/gas/riscv/zksh-64.d
new file mode 100644
index 00000000000..91a3f16e511
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksh-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zksh
+#source: zksh.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+.*:[ 	]+.*[ 	]+sm3p0[ 	]+a0,a0
+[ 	]+.*:[ 	]+.*[ 	]+sm3p1[ 	]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zksh.s b/gas/testsuite/gas/riscv/zksh.s
new file mode 100644
index 00000000000..b321c26f2b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksh.s
@@ -0,0 +1,3 @@
+target:
+        sm3p0   a0, a0
+        sm3p1   a0, a0
-- 
2.25.1


  parent reply	other threads:[~2021-11-15  3:04 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-15  3:03 [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-15  3:03 ` [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
2022-02-21 13:24   ` Jan Beulich
2022-02-21 14:14     ` jiawei
2022-02-21 14:16       ` Philipp Tomsich
2022-02-21 14:25         ` Jan Beulich
2022-02-21 14:44         ` Tsukasa OI
2022-02-21 14:50           ` Kito Cheng
2021-11-15  3:03 ` [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set jiawei
2022-01-04  8:04   ` Jan Beulich
2022-01-04  8:38     ` 陈嘉炜
2022-01-04  8:49       ` Jan Beulich
2022-01-04 13:13         ` Markku-Juhani O. Saarinen
2021-11-15  3:03 ` jiawei [this message]
2021-12-21 16:06   ` [PATCH v4 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases Jan Beulich
2021-11-16  4:07 ` [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension Nelson Chu

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