From: Jan Beulich <jbeulich@suse.com>
To: jiawei <jiawei@iscas.ac.cn>
Cc: kito.cheng@sifive.com, nelson.chu@sifive.com, jimw@sifive.com,
philipp.tomsich@vrull.eu, mjos@pqshield.com,
ben.marshall@pqshield.com, cmuellner@ventanamicro.com,
palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com,
siyu@isrc.iscas.ac.cn, schwab@linux-m68k.org,
binutils@sourceware.org
Subject: Re: [PATCH v4 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
Date: Tue, 21 Dec 2021 17:06:28 +0100 [thread overview]
Message-ID: <c7f4b99f-0ac8-4a32-752c-19fd7ebbd34c@suse.com> (raw)
In-Reply-To: <20211115030343.276103-4-jiawei@iscas.ac.cn>
On 15.11.2021 04:03, jiawei wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/k-ext-64.d
> @@ -0,0 +1,47 @@
> +#as: -march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
> +#source: k-ext-64.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
> +[ ]+.*:[ ]+.*[ ]+rorw[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+rolw[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+roriw[ ]+a0,a1,0x2
> +[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+packw[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+aes64ds[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+aes64dsm[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+aes64im[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
> +[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+aes64es[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+aes64esm[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha512sig0[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha512sig1[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha512sum0[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha512sum1[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
> +[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
> +[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
Since most (all) other insn-specific tests are different in this regard,
I wonder whether it is on purpose that the actual encodings get omitted
here (or to be precise, skipped by way of using .* ). Since these tests
serve as both assembler and disassembler ones, I think checking that the
correct encodings get produced (and consumed) would be at least helpful.
Jan
next prev parent reply other threads:[~2021-12-21 16:06 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-15 3:03 [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-15 3:03 ` [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
2022-02-21 13:24 ` Jan Beulich
2022-02-21 14:14 ` jiawei
2022-02-21 14:16 ` Philipp Tomsich
2022-02-21 14:25 ` Jan Beulich
2022-02-21 14:44 ` Tsukasa OI
2022-02-21 14:50 ` Kito Cheng
2021-11-15 3:03 ` [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set jiawei
2022-01-04 8:04 ` Jan Beulich
2022-01-04 8:38 ` 陈嘉炜
2022-01-04 8:49 ` Jan Beulich
2022-01-04 13:13 ` Markku-Juhani O. Saarinen
2021-11-15 3:03 ` [PATCH v4 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
2021-12-21 16:06 ` Jan Beulich [this message]
2021-11-16 4:07 ` [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension Nelson Chu
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