* [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros
@ 2022-03-15 23:40 Alan Modra
2022-03-15 23:40 ` [PATCH 2/5] PowerPC32 " Alan Modra
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Alan Modra @ 2022-03-15 23:40 UTC (permalink / raw)
To: binutils
The extended instructions implemented in powerpc_macros aren't used by
the disassembler. That means instructions like "sldi r3,r3,2" appear
in disassembly as "rldicr r3,r3,2,61", which is annoying since many
other extended instructions are shown.
Note that some of the instructions moved out of the macro table to the
opcode table won't appear in disassembly, because they are aliases
rather than a subset of the underlying raw instruction. If enabled,
rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all
occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many
occurrences in the case of clrlsldi if n <= b was added to the extract
functions.)
The patch also fixes a small bug in opcode sanity checking.
include/
* opcode/ppc.h (PPC_OPSHIFT_SH6): Define.
opcodes/
* ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn),
(insert_crdn, extract_crdn, insert_rrdn, extract_rrdn),
(insert_sldn, extract_sldn, insert_srdn, extract_srdn),
(insert_erdb, extract_erdb, insert_csldn, extract_csldb),
(insert_irdb, extract_irdn): New functions.
(ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb):
Define and add associated powerpc_operands entries.
(powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi",
"sldi", "extldi", "clrlsldi", "insrdi" and corresponding record
(ie. dot suffix) forms.
(powerpc_macros): Delete same from here.
gas/
* config/tc-ppc.c (insn_validate): Don't modify value passed
to operand->insert for PPC_OPERAND_PLUS1 when calculating mask.
Handle PPC_OPSHIFT_SH6.
* testsuite/gas/ppc/prefix-reloc.d: Update.
* testsuite/gas/ppc/simpshft.d: Update.
ld/
* testsuite/ld-powerpc/elfv2so.d: Update.
* testsuite/ld-powerpc/notoc.d: Update.
* testsuite/ld-powerpc/notoc3.d: Update.
* testsuite/ld-powerpc/tlsdesc2.d: Update.
* testsuite/ld-powerpc/tlsget.d: Update.
* testsuite/ld-powerpc/tlsget2.d: Update.
* testsuite/ld-powerpc/tlsopt5.d: Update.
* testsuite/ld-powerpc/tlsopt6.d: Update.
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 89bc7d3f9b9..cf11f7adc6c 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1589,10 +1589,10 @@ insn_validate (const struct powerpc_opcode *op)
val = -1;
if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
val = -val;
- else if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
- val += 1;
mask = (*operand->insert) (0, val, ppc_cpu, &errmsg);
}
+ else if (operand->shift == (int) PPC_OPSHIFT_SH6)
+ mask = (0x1f << 11) | 0x2;
else if (operand->shift >= 0)
mask = operand->bitm << operand->shift;
else
diff --git a/gas/testsuite/gas/ppc/prefix-reloc.d b/gas/testsuite/gas/ppc/prefix-reloc.d
index b442419904f..e79f4aa07f5 100644
--- a/gas/testsuite/gas/ppc/prefix-reloc.d
+++ b/gas/testsuite/gas/ppc/prefix-reloc.d
@@ -10,7 +10,7 @@ Disassembly of section \.text:
0: (00 00 00 06|06 00 00 00) pli r9,0
4: (00 00 20 39|39 20 00 00)
0: R_PPC64_D34_HA30 ext
- 8: (46 17 29 79|79 29 17 46) rldicr r9,r9,34,29
+ 8: (46 17 29 79|79 29 17 46) sldi r9,r9,34
c: (00 00 00 06|06 00 00 00) paddi r9,r9,0
10: (00 00 29 39|39 29 00 00)
c: R_PPC64_D34_LO ext
diff --git a/gas/testsuite/gas/ppc/simpshft.d b/gas/testsuite/gas/ppc/simpshft.d
index b4cccd57920..b88752c8a38 100644
--- a/gas/testsuite/gas/ppc/simpshft.d
+++ b/gas/testsuite/gas/ppc/simpshft.d
@@ -7,19 +7,19 @@
Disassembly of section .text:
0+ <.text>:
- 0: (e0 0f 64 78|78 64 0f e0) rldicl r4,r3,1,63
+ 0: (e0 0f 64 78|78 64 0f e0) srdi r4,r3,63
4: (0e f8 83 78|78 83 f8 0e) rldimi r3,r4,63,0
- 8: (e4 45 a5 78|78 a5 45 e4) rldicr r5,r5,8,55
+ 8: (e4 45 a5 78|78 a5 45 e4) sldi r5,r5,8
c: (20 00 64 78|78 64 00 20) clrldi r4,r3,32
10: (fe 0f 64 54|54 64 0f fe) rlwinm r4,r3,1,31,31
14: (00 f8 83 50|50 83 f8 00) rlwimi r3,r4,31,0,0
18: (2e 40 a5 54|54 a5 40 2e) rlwinm r5,r5,8,0,23
1c: (3e 04 64 54|54 64 04 3e) clrlwi r4,r3,16
- 20: (04 00 64 78|78 64 00 04) rldicr r4,r3,0,0
- 24: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63
- 28: (06 f8 64 78|78 64 f8 06) rldicr r4,r3,63,0
+ 20: (04 00 64 78|78 64 00 04) clrrdi r4,r3,63
+ 24: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0
+ 28: (06 f8 64 78|78 64 f8 06) sldi r4,r3,63
2c: (e6 ff 64 78|78 64 ff e6) rldicr r4,r3,63,63
- 30: (42 f8 64 78|78 64 f8 42) rldicl r4,r3,63,1
+ 30: (42 f8 64 78|78 64 f8 42) srdi r4,r3,1
34: (e2 ff 64 78|78 64 ff e2) rldicl r4,r3,63,63
38: (0c 00 64 78|78 64 00 0c) rldimi r4,r3,0,0
3c: (0c 08 64 78|78 64 08 0c) rldimi r4,r3,1,0
@@ -32,17 +32,17 @@ Disassembly of section .text:
58: (02 f8 64 78|78 64 f8 02) rotldi r4,r3,63
5c: (00 08 64 78|78 64 08 00) rotldi r4,r3,1
60: (10 20 65 78|78 65 20 10) rotld r5,r3,r4
- 64: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63
- 68: (06 f8 64 78|78 64 f8 06) rldicr r4,r3,63,0
+ 64: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0
+ 68: (06 f8 64 78|78 64 f8 06) sldi r4,r3,63
6c: (00 00 64 78|78 64 00 00) rotldi r4,r3,0
- 70: (42 f8 64 78|78 64 f8 42) rldicl r4,r3,63,1
- 74: (e0 0f 64 78|78 64 0f e0) rldicl r4,r3,1,63
+ 70: (42 f8 64 78|78 64 f8 42) srdi r4,r3,1
+ 74: (e0 0f 64 78|78 64 0f e0) srdi r4,r3,63
78: (00 00 64 78|78 64 00 00) rotldi r4,r3,0
7c: (40 00 64 78|78 64 00 40) clrldi r4,r3,1
80: (e0 07 64 78|78 64 07 e0) clrldi r4,r3,63
- 84: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63
- 88: (a4 07 64 78|78 64 07 a4) rldicr r4,r3,0,62
- 8c: (04 00 64 78|78 64 00 04) rldicr r4,r3,0,0
+ 84: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0
+ 88: (a4 07 64 78|78 64 07 a4) clrrdi r4,r3,1
+ 8c: (04 00 64 78|78 64 00 04) clrrdi r4,r3,63
90: (08 00 64 78|78 64 00 08) rldic r4,r3,0,0
94: (48 00 64 78|78 64 00 48) rldic r4,r3,0,1
98: (e8 07 64 78|78 64 07 e8) rldic r4,r3,0,63
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index a236b6b469c..463965dab58 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -336,9 +336,11 @@ extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;
/* Use with the shift field of a struct powerpc_operand to indicate
- that BITM and SHIFT cannot be used to determine where the operand
- goes in the insn. */
-#define PPC_OPSHIFT_INV (-1U << 31)
+ that BITM and SHIFT cannot be used to determine where the operand
+ goes in the insn. */
+#define PPC_OPSHIFT_INV (1U << 30)
+/* A special case, 6-bit SH field. */
+#define PPC_OPSHIFT_SH6 (2U << 30)
/* Values defined for the flags field of a struct powerpc_operand.
Keep the register bits low: They need to fit in an unsigned short. */
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d
index 4018f0536c6..0005710f621 100644
--- a/ld/testsuite/ld-powerpc/elfv2so.d
+++ b/ld/testsuite/ld-powerpc/elfv2so.d
@@ -80,7 +80,7 @@ Disassembly of section \.text:
.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
-.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
+.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
.*: (4e 80 04 20|20 04 80 4e) bctr
diff --git a/ld/testsuite/ld-powerpc/notoc.d b/ld/testsuite/ld-powerpc/notoc.d
index 3555be7334c..69f17217779 100644
--- a/ld/testsuite/ld-powerpc/notoc.d
+++ b/ld/testsuite/ld-powerpc/notoc.d
@@ -23,7 +23,7 @@ Disassembly of section \.text:
.*: (a6 03 88 7d|7d 88 03 a6) mtlr r12
.*: (ff 7f 80 3d|3d 80 7f ff) lis r12,32767
.*: (ff ff 8c 61|61 8c ff ff) ori r12,r12,65535
-.*: (c6 07 9c 79|79 9c 07 c6) rldicr r28,r12,32,31
+.*: (c6 07 9c 79|79 9c 07 c6) sldi r28,r12,32
.*: (ff ef 8c 65|65 8c ef ff) oris r12,r12,61439
.*: (28 ff 8c 61|61 8c ff 28) ori r12,r12,65320
.*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12
diff --git a/ld/testsuite/ld-powerpc/notoc3.d b/ld/testsuite/ld-powerpc/notoc3.d
index 134bba31bfd..24cf9bb19c0 100644
--- a/ld/testsuite/ld-powerpc/notoc3.d
+++ b/ld/testsuite/ld-powerpc/notoc3.d
@@ -20,7 +20,7 @@ Disassembly of section \.text:
.*: (00 00 6b 61|61 6b 00 00) ori r11,r11,0
.*: (ff ef 13 06|06 13 ef ff) pla r12,-268435736 # 0
.*: (e8 fe 80 39|39 80 fe e8)
-.*: (46 17 6b 79|79 6b 17 46) rldicr r11,r11,34,29
+.*: (46 17 6b 79|79 6b 17 46) sldi r11,r11,34
.*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12
.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
.*: (20 04 80 4e|4e 80 04 20) bctr
diff --git a/ld/testsuite/ld-powerpc/tlsdesc2.d b/ld/testsuite/ld-powerpc/tlsdesc2.d
index c271c949b01..cd2663a18c4 100644
--- a/ld/testsuite/ld-powerpc/tlsdesc2.d
+++ b/ld/testsuite/ld-powerpc/tlsdesc2.d
@@ -59,7 +59,7 @@ Disassembly of section \.text:
.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
-.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
+.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
.*: (4e 80 04 20|20 04 80 4e) bctr
diff --git a/ld/testsuite/ld-powerpc/tlsget.d b/ld/testsuite/ld-powerpc/tlsget.d
index f419fca4d29..f16febcdb9c 100644
--- a/ld/testsuite/ld-powerpc/tlsget.d
+++ b/ld/testsuite/ld-powerpc/tlsget.d
@@ -80,7 +80,7 @@ Disassembly of section \.text:
.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
-.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
+.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
.*: (4e 80 04 20|20 04 80 4e) bctr
diff --git a/ld/testsuite/ld-powerpc/tlsget2.d b/ld/testsuite/ld-powerpc/tlsget2.d
index 13dc64b595e..910e048e7b9 100644
--- a/ld/testsuite/ld-powerpc/tlsget2.d
+++ b/ld/testsuite/ld-powerpc/tlsget2.d
@@ -67,7 +67,7 @@ Disassembly of section \.text:
.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
-.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
+.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
.*: (4e 80 04 20|20 04 80 4e) bctr
diff --git a/ld/testsuite/ld-powerpc/tlsopt5.d b/ld/testsuite/ld-powerpc/tlsopt5.d
index efd6debc555..2ea1f7f7970 100644
--- a/ld/testsuite/ld-powerpc/tlsopt5.d
+++ b/ld/testsuite/ld-powerpc/tlsopt5.d
@@ -55,7 +55,7 @@ Disassembly of section \.text:
.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11
.*: (d4 ff 0c 38|38 0c ff d4) addi r0,r12,-44
.*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\)
-.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2
+.*: (82 f0 00 78|78 00 f0 82) srdi r0,r0,2
.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
.*: (08 00 6b e9|e9 6b 00 08) ld r11,8\(r11\)
.*: (20 04 80 4e|4e 80 04 20) bctr
diff --git a/ld/testsuite/ld-powerpc/tlsopt6.d b/ld/testsuite/ld-powerpc/tlsopt6.d
index 15def719cba..38a2068bbdf 100644
--- a/ld/testsuite/ld-powerpc/tlsopt6.d
+++ b/ld/testsuite/ld-powerpc/tlsopt6.d
@@ -73,7 +73,7 @@ Disassembly of section \.text:
.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11
.*: (d4 ff 0c 38|38 0c ff d4) addi r0,r12,-44
.*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\)
-.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2
+.*: (82 f0 00 78|78 00 f0 82) srdi r0,r0,2
.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
.*: (08 00 6b e9|e9 6b 00 08) ld r11,8\(r11\)
.*: (20 04 80 4e|4e 80 04 20) bctr
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index a424dd924de..20844875740 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1166,6 +1166,63 @@ extract_mb6 (uint64_t insn,
return ((insn >> 6) & 0x1f) | (insn & 0x20);
}
+/* The n operand of extrdi, which sets MB field. */
+
+static uint64_t
+insert_erdn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ return insert_mb6 (insn, -value, dialect, errmsg);
+}
+
+static int64_t
+extract_erdn (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ return (~extract_mb6 (insn, dialect, invalid) & 63) + 1;
+}
+
+/* The n operand of extldi, which sets ME field. */
+
+static uint64_t
+insert_eldn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ return insert_mb6 (insn, value - 1, dialect, errmsg);
+}
+
+static int64_t
+extract_eldn (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ return extract_mb6 (insn, dialect, invalid) + 1;
+}
+
+/* The n operand of clrrdi, which set ME field. */
+
+static uint64_t
+insert_crdn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ return insert_mb6 (insn, 63 - value, dialect, errmsg);
+}
+
+static int64_t
+extract_crdn (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ return 63 - extract_mb6 (insn, dialect, invalid);
+}
+
/* The NB field in an X form instruction. The value 32 is stored as
0. */
@@ -1551,6 +1608,143 @@ extract_sh6 (uint64_t insn,
return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
}
+/* The n operand of rotrdi, which writes to SH field. */
+
+static uint64_t
+insert_rrdn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ return insert_sh6 (insn, -value, dialect, errmsg);
+}
+
+static int64_t
+extract_rrdn (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ return -extract_sh6 (insn, dialect, invalid) & 63;
+}
+
+/* The n operand of sldi, which writes to SH and ME fields. */
+
+static uint64_t
+insert_sldn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ insn = insert_sh6 (insn, value, dialect, errmsg);
+ return insert_crdn (insn, value, dialect, errmsg);
+}
+
+static int64_t
+extract_sldn (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ int64_t sh = extract_sh6 (insn, dialect, invalid);
+ int64_t me = extract_crdn (insn, dialect, invalid);
+ if (me != sh)
+ *invalid = 1;
+ return sh;
+}
+
+/* The n operand of srdi, which writes to SH and MB fields. */
+
+static uint64_t
+insert_srdn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ insn = insert_rrdn (insn, value, dialect, errmsg);
+ return insert_mb6 (insn, value, dialect, errmsg);
+}
+
+static int64_t
+extract_srdn (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ int64_t sh = extract_rrdn (insn, dialect, invalid);
+ int64_t mb = extract_mb6 (insn, dialect, invalid);
+ if (mb != sh)
+ *invalid = 1;
+ return sh;
+}
+
+/* The b operand of extrdi, which sets SH field. */
+
+static uint64_t
+insert_erdb (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ int64_t n = extract_erdn (insn, dialect, NULL);
+ return insert_sh6 (insn, value + n, dialect, errmsg);
+}
+
+static int64_t
+extract_erdb (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ int64_t sh = extract_sh6 (insn, dialect, invalid);
+ int64_t n = extract_erdn (insn, dialect, invalid);
+ return (sh - n) & 63;
+}
+
+/* The b and n operands of clrlsldi. */
+
+static uint64_t
+insert_csldn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ uint64_t mb6 = 0x3f << 5;
+ int64_t b = extract_mb6 (insn, dialect, NULL);
+ insn = insert_mb6 (insn & ~mb6, b - value, dialect, errmsg);
+ return insert_sh6 (insn, value, dialect, errmsg);
+}
+
+static int64_t
+extract_csldb (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ int64_t sh = extract_sh6 (insn, dialect, invalid);
+ int64_t mb = extract_mb6 (insn, dialect, invalid);
+ return (mb + sh) & 63;
+}
+
+/* The b and n operands of insrdi. */
+
+static uint64_t
+insert_irdb (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ uint64_t sh6 = (0x1f << 11) | 2;
+ int64_t n = extract_sh6 (insn, dialect, NULL);
+ insn = insert_sh6 (insn & ~sh6, -(value + n), dialect, errmsg);
+ return insert_mb6 (insn, value, dialect, errmsg);
+}
+
+static int64_t
+extract_irdn (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ int64_t sh = extract_sh6 (insn, dialect, invalid);
+ int64_t mb = extract_mb6 (insn, dialect, invalid);
+ return (~(mb + sh) & 63) + 1;
+}
+
/* The SPR field in an XFX form instruction. This is flipped--the
lower 5 bits are stored in the upper 5 and vice- versa. */
@@ -2754,9 +2948,18 @@ const struct powerpc_operand powerpc_operands[] =
#define MB6_MASK (0x3f << 5)
{ 0x3f, 5, insert_mb6, extract_mb6, 0 },
+#define ELDn MB6 + 1
+ { 0x3f, 5, insert_eldn, extract_eldn, PPC_OPERAND_PLUS1 },
+
+#define ERDn ELDn + 1
+ { 0x3f, 5, insert_erdn, extract_erdn, 0 },
+
+#define CRDn ERDn + 1
+ { 0x3f, 5, insert_crdn, extract_crdn, 0 },
+
/* The NB field in an X form instruction. The value 32 is stored as
0. */
-#define NB MB6 + 1
+#define NB CRDn + 1
{ 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
/* The NBI field in an lswi instruction, which has special value
@@ -2942,9 +3145,33 @@ const struct powerpc_operand powerpc_operands[] =
#define SH6_MASK ((0x1f << 11) | (1 << 1))
{ 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
+#define RRDn SH6 + 1
+ { 0x3f, PPC_OPSHIFT_INV, insert_rrdn, extract_rrdn, 0 },
+
+#define SLDn RRDn + 1
+ { 0x3f, PPC_OPSHIFT_INV, insert_sldn, extract_sldn, 0 },
+
+#define SRDn SLDn + 1
+ { 0x3f, PPC_OPSHIFT_INV, insert_srdn, extract_srdn, 0 },
+
+#define ERDb SRDn + 1
+ { 0x3f, PPC_OPSHIFT_INV, insert_erdb, extract_erdb, 0 },
+
+#define CSLDn ERDb + 1
+ { 0x3f, PPC_OPSHIFT_SH6, insert_csldn, extract_sh6, 0 },
+
+#define CSLDb CSLDn + 1
+ { 0x3f, 5, insert_mb6, extract_csldb, 0 },
+
+#define IRDn CSLDb + 1
+ { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_irdn, PPC_OPERAND_PLUS1 },
+
+#define IRDb IRDn + 1
+ { 0x3f, 5, insert_irdb, extract_mb6, 0 },
+
/* The SH field of some variants of the tlbre and tlbwe
instructions, and the ELEV field of the e_sc instruction. */
-#define SHO SH6 + 1
+#define SHO IRDb + 1
#define ELEV SHO
{ 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
@@ -6244,20 +6471,36 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, SH6}},
+{"rotrdi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RRDn}},
{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, MB6}},
+{"srdi", MD(30,0,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SRDn}},
{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
+{"extrdi", MD(30,0,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, ERDn, ERDb}},
{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, SH6}},
+{"rotrdi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RRDn}},
{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, MB6}},
+{"srdi.", MD(30,0,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SRDn}},
{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
+{"extrdi.", MD(30,0,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, ERDn, ERDb}},
+{"clrrdi", MD(30,1,0), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, CRDn}},
+{"sldi", MD(30,1,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SLDn}},
{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
+{"extldi", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, ELDn, SH6}},
+{"clrrdi.", MD(30,1,1), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, CRDn}},
+{"sldi.", MD(30,1,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SLDn}},
{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
+{"extldi.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, ELDn, SH6}},
{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
+{"clrlsldi", MD(30,2,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, CSLDb, CSLDn}},
{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
+{"clrlsldi.", MD(30,2,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, CSLDb, CSLDn}},
{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
+{"insrdi", MD(30,3,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, IRDn, IRDb}},
{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
+{"insrdi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, IRDn, IRDb}},
{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RB}},
{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
@@ -9949,23 +10192,6 @@ const unsigned int vle_num_opcodes =
support extracting the whole word (32 bits in this case). */
const struct powerpc_macro powerpc_macros[] = {
-{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
-{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
-{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
-{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
-{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
-{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
-{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
-{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
-{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
-{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
-{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
-{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
-{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
-{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
-{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
-{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
-
{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/5] PowerPC32 extended instructions in powerpc_macros
2022-03-15 23:40 [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros Alan Modra
@ 2022-03-15 23:40 ` Alan Modra
2022-03-15 23:40 ` [PATCH 3/5] PowerPC VLE " Alan Modra
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Alan Modra @ 2022-03-15 23:40 UTC (permalink / raw)
To: binutils
As for PowerPC64, move instructions to the main opcode table.
opcodes/
* ppc-opc.c (insert_crwn, extract_crwn, insert_elwn, extract_elwn),
(insert_erwn, extract_erwn, insert_erwb, extract_erwb),
(insert_cslwn, extract_cslwb, insert_ilwb, extract_ilwn),
(insert_irwb, extract_irwn, insert_rrwn, extract_rrwn),
(insert_slwn, extract_slwn, insert_srwn, extract_srwn): New functions.
(CRWn, ELWn, ERWn, ERWb, CSLWb, CSLWn, ILWn, ILWb, IRWn, IRWb),
(RRWn, SLWn, SRWn): Define and add powerpc_operands entries.
(MMB_MASK, MME_MASK, MSHMB_MASK): Define.
(powerpc_opcodes): Add "inslwi", "insrwi", "rotrwi", "clrrwi",
"slwi", "srwi", "extlwi", "extrwi", "sli", "sri" and corresponding
record (ie. dot suffix) forms.
(powerpc_macros): Delete same.
gas/
* testsuite/gas/ppc/476.d: Update.
* testsuite/gas/ppc/simpshft.d: Update.
diff --git a/gas/testsuite/gas/ppc/476.d b/gas/testsuite/gas/ppc/476.d
index 0b75d75ae2d..70ea88d001e 100644
--- a/gas/testsuite/gas/ppc/476.d
+++ b/gas/testsuite/gas/ppc/476.d
@@ -59,7 +59,7 @@ Disassembly of section \.text:
.*: (4c 86 00 21|21 00 86 4c) bnelrl cr1
.*: (48 00 00 00|00 00 00 48) b c8 <ppc476\+0xc8>
.*: (48 00 00 01|01 00 00 48) bl cc <ppc476\+0xcc>
-.*: (54 83 00 36|36 00 83 54) rlwinm r3,r4,0,0,27
+.*: (54 83 00 36|36 00 83 54) clrrwi r3,r4,4
.*: (7c 03 20 00|00 20 03 7c) cmpw r3,r4
.*: (7f 83 20 00|00 20 83 7f) cmpw cr7,r3,r4
.*: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
@@ -401,10 +401,10 @@ Disassembly of section \.text:
.*: (4c 00 00 4c|4c 00 00 4c) rfmci
.*: (50 83 65 36|36 65 83 50) rlwimi r3,r4,12,20,27
.*: (50 83 65 37|37 65 83 50) rlwimi\. r3,r4,12,20,27
-.*: (54 83 00 36|36 00 83 54) rlwinm r3,r4,0,0,27
-.*: (54 83 d1 be|be d1 83 54) rlwinm r3,r4,26,6,31
+.*: (54 83 00 36|36 00 83 54) clrrwi r3,r4,4
+.*: (54 83 d1 be|be d1 83 54) srwi r3,r4,6
.*: (54 83 20 26|26 20 83 54) rlwinm r3,r4,4,0,19
-.*: (54 83 00 37|37 00 83 54) rlwinm\. r3,r4,0,0,27
+.*: (54 83 00 37|37 00 83 54) clrrwi\. r3,r4,4
.*: (5c 83 28 3e|3e 28 83 5c) rotlw r3,r4,r5
.*: (5c 83 28 3f|3f 28 83 5c) rotlw\. r3,r4,r5
.*: (5c 83 28 3e|3e 28 83 5c) rotlw r3,r4,r5
@@ -418,7 +418,7 @@ Disassembly of section \.text:
.*: (7c 83 86 71|71 86 83 7c) srawi\. r3,r4,16
.*: (7c 83 2c 30|30 2c 83 7c) srw r3,r4,r5
.*: (7c 83 2c 31|31 2c 83 7c) srw\. r3,r4,r5
-.*: (54 83 d1 be|be d1 83 54) rlwinm r3,r4,26,6,31
+.*: (54 83 d1 be|be d1 83 54) srwi r3,r4,6
.*: (99 61 00 02|02 00 61 99) stb r11,2\(r1\)
.*: (9d 81 00 03|03 00 81 9d) stbu r12,3\(r1\)
.*: (7d ae 79 ee|ee 79 ae 7d) stbux r13,r14,r15
diff --git a/gas/testsuite/gas/ppc/simpshft.d b/gas/testsuite/gas/ppc/simpshft.d
index b88752c8a38..70b8e02797f 100644
--- a/gas/testsuite/gas/ppc/simpshft.d
+++ b/gas/testsuite/gas/ppc/simpshft.d
@@ -11,9 +11,9 @@ Disassembly of section .text:
4: (0e f8 83 78|78 83 f8 0e) rldimi r3,r4,63,0
8: (e4 45 a5 78|78 a5 45 e4) sldi r5,r5,8
c: (20 00 64 78|78 64 00 20) clrldi r4,r3,32
- 10: (fe 0f 64 54|54 64 0f fe) rlwinm r4,r3,1,31,31
+ 10: (fe 0f 64 54|54 64 0f fe) srwi r4,r3,31
14: (00 f8 83 50|50 83 f8 00) rlwimi r3,r4,31,0,0
- 18: (2e 40 a5 54|54 a5 40 2e) rlwinm r5,r5,8,0,23
+ 18: (2e 40 a5 54|54 a5 40 2e) slwi r5,r5,8
1c: (3e 04 64 54|54 64 04 3e) clrlwi r4,r3,16
20: (04 00 64 78|78 64 00 04) clrrdi r4,r3,63
24: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0
@@ -48,11 +48,11 @@ Disassembly of section .text:
98: (e8 07 64 78|78 64 07 e8) rldic r4,r3,0,63
9c: (a8 0f 64 78|78 64 0f a8) rldic r4,r3,1,62
a0: (0a f8 64 78|78 64 f8 0a) rldic r4,r3,63,0
- a4: (00 00 64 54|54 64 00 00) rlwinm r4,r3,0,0,0
+ a4: (00 00 64 54|54 64 00 00) clrrwi r4,r3,31
a8: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
- ac: (00 f8 64 54|54 64 f8 00) rlwinm r4,r3,31,0,0
+ ac: (00 f8 64 54|54 64 f8 00) slwi r4,r3,31
b0: (3e f8 64 54|54 64 f8 3e) rotlwi r4,r3,31
- b4: (7e f8 64 54|54 64 f8 7e) rlwinm r4,r3,31,1,31
+ b4: (7e f8 64 54|54 64 f8 7e) srwi r4,r3,1
b8: (fe ff 64 54|54 64 ff fe) rlwinm r4,r3,31,31,31
bc: (00 00 64 50|50 64 00 00) rlwimi r4,r3,0,0,0
c0: (3e 00 64 50|50 64 00 3e) rlwimi r4,r3,0,0,31
@@ -68,20 +68,20 @@ Disassembly of section .text:
e8: (3e 08 64 54|54 64 08 3e) rotlwi r4,r3,1
ec: (3e 20 65 5c|5c 65 20 3e) rotlw r5,r3,r4
f0: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
- f4: (3c 08 64 54|54 64 08 3c) rlwinm r4,r3,1,0,30
- f8: (00 f8 64 54|54 64 f8 00) rlwinm r4,r3,31,0,0
+ f4: (3c 08 64 54|54 64 08 3c) slwi r4,r3,1
+ f8: (00 f8 64 54|54 64 f8 00) slwi r4,r3,31
fc: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
- 100: (7e f8 64 54|54 64 f8 7e) rlwinm r4,r3,31,1,31
- 104: (fe 0f 64 54|54 64 0f fe) rlwinm r4,r3,1,31,31
+ 100: (7e f8 64 54|54 64 f8 7e) srwi r4,r3,1
+ 104: (fe 0f 64 54|54 64 0f fe) srwi r4,r3,31
108: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
10c: (7e 00 64 54|54 64 00 7e) clrlwi r4,r3,1
110: (fe 07 64 54|54 64 07 fe) clrlwi r4,r3,31
114: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
- 118: (3c 00 64 54|54 64 00 3c) rlwinm r4,r3,0,0,30
- 11c: (00 00 64 54|54 64 00 00) rlwinm r4,r3,0,0,0
+ 118: (3c 00 64 54|54 64 00 3c) clrrwi r4,r3,1
+ 11c: (00 00 64 54|54 64 00 00) clrrwi r4,r3,31
120: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
124: (7e 00 64 54|54 64 00 7e) clrlwi r4,r3,1
128: (fe 07 64 54|54 64 07 fe) clrlwi r4,r3,31
12c: (bc 0f 64 54|54 64 0f bc) rlwinm r4,r3,1,30,30
- 130: (00 f8 64 54|54 64 f8 00) rlwinm r4,r3,31,0,0
+ 130: (00 f8 64 54|54 64 f8 00) slwi r4,r3,31
#pass
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 20844875740..45d07196309 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1058,6 +1058,165 @@ extract_esync (uint64_t insn,
return value;
}
+/* The n operand of clrrwi, which sets the ME field to 31 - n. */
+
+static uint64_t
+insert_crwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((~value & 0x1f) << 1);
+}
+
+static int64_t
+extract_crwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ~(insn >> 1) & 0x1f;
+}
+
+/* The n operand of extlwi, which sets the ME field to n - 1. */
+
+static uint64_t
+insert_elwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | (((value - 1) & 0x1f) << 1);
+}
+
+static int64_t
+extract_elwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 1) & 0x1f) + 1;
+}
+
+/* The n operand of extrwi, sets MB = 32 - n. */
+
+static uint64_t
+insert_erwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((-value & 0x1f) << 6);
+}
+
+static int64_t
+extract_erwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return (~(insn >> 6) & 0x1f) + 1;
+}
+
+/* The b operand of extrwi, sets SH = b + n. */
+
+static uint64_t
+insert_erwb (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ int64_t n = extract_erwn (insn, dialect, NULL);
+ return insn | (((n + value) & 0x1f) << 11);
+}
+
+static int64_t
+extract_erwb (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ int64_t n = extract_erwn (insn, dialect, NULL);
+ return ((insn >> 11) - n) & 0x1f;
+}
+
+/* The n and b operands of clrlslwi. */
+
+static uint64_t
+insert_cslwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ uint64_t mb = 0x1f << 6;
+ int64_t b = (insn >> 6) & 0x1f;
+ return ((insn & ~mb) | ((value & 0x1f) << 11) | (((b - value) & 0x1f) << 6)
+ | ((~value & 0x1f) << 1));
+}
+
+static int64_t
+extract_cslwb (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t sh = (insn >> 11) & 0x1f;
+ int64_t mb = (insn >> 6) & 0x1f;
+ int64_t me = (insn >> 1) & 0x1f;
+ if (sh != 31 - me)
+ *invalid = 1;
+ return (mb + sh) & 0x1f;
+}
+
+/* The n and b operands of inslwi. */
+
+static uint64_t
+insert_ilwb (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ uint64_t me = 0x1f << 1;
+ int64_t n = (insn >> 1) & 0x1f;
+ return ((insn & ~me) | ((-value & 0x1f) << 11) | ((value & 0x1f) << 6)
+ | (((value + n - 1) & 0x1f) << 1));
+}
+
+static int64_t
+extract_ilwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t sh = (insn >> 11) & 0x1f;
+ int64_t mb = (insn >> 6) & 0x1f;
+ int64_t me = (insn >> 1) & 0x1f;
+ if (((sh + mb) & 0x1f) != 0)
+ *invalid = 1;
+ return ((me - mb) & 0x1f) + 1;
+}
+
+/* The n and b operands of insrwi. */
+
+static uint64_t
+insert_irwb (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ uint64_t me = 0x1f << 1;
+ int64_t n = (insn >> 1) & 0x1f;
+ return ((insn & ~me) | ((-(value + n) & 0x1f) << 11) | ((value & 0x1f) << 6)
+ | (((value + n - 1) & 0x1f) << 1));
+}
+
+static int64_t
+extract_irwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t sh = (insn >> 11) & 0x1f;
+ int64_t mb = (insn >> 6) & 0x1f;
+ int64_t me = (insn >> 1) & 0x1f;
+ if (((sh + me + 1) & 0x1f) != 0)
+ *invalid = 1;
+ return ((me - mb) & 0x1f) + 1;
+}
+
/* The MB and ME fields in an M form instruction expressed as a single
operand which is itself a bitmask. The extraction function always
marks it as invalid, since we never want to recognize an
@@ -1589,6 +1748,71 @@ extract_oimm (uint64_t insn,
return ((insn >> 4) & 0x1f) + 1;
}
+/* The n operand of rotrwi, sets SH = 32 - n. */
+
+static uint64_t
+insert_rrwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((-value & 0x1f) << 11);
+}
+
+static int64_t
+extract_rrwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return 31 & -(insn >> 11);
+}
+
+/* The n operand of slwi, sets SH = n and ME = 31 - n. */
+
+static uint64_t
+insert_slwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x1f) << 11) | ((~value & 0x1f) << 1);
+}
+
+static int64_t
+extract_slwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t sh = (insn >> 11) & 0x1f;
+ int64_t nme = ~(insn >> 1) & 0x1f;
+ if (sh != nme)
+ *invalid = 1;
+ return sh;
+}
+
+/* The n operand of srwi, sets SH = 32 - n and MB = n. */
+
+static uint64_t
+insert_srwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((-value & 0x1f) << 11) | ((value & 0x1f) << 6);
+}
+
+static int64_t
+extract_srwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t nsh = -(insn >> 11) & 0x1f;
+ int64_t mb = (insn >> 6) & 0x1f;
+ if (nsh != mb)
+ *invalid = 1;
+ return nsh;
+}
+
/* The SH field in an MD form instruction. This is split. */
static uint64_t
@@ -2933,11 +3157,41 @@ const struct powerpc_operand powerpc_operands[] =
#define ME_MASK (0x1f << 1)
{ 0x1f, 1, NULL, NULL, 0 },
+#define CRWn ME + 1
+ { 0x1f, 1, insert_crwn, extract_crwn, 0 },
+
+#define ELWn CRWn + 1
+ { 0x1f, 1, insert_elwn, extract_elwn, PPC_OPERAND_PLUS1 },
+
+#define ERWn ELWn + 1
+ { 0x1f, 6, insert_erwn, extract_erwn, 0 },
+
+#define ERWb ERWn + 1
+ { 0x1f, 11, insert_erwb, extract_erwb, 0 },
+
+#define CSLWb ERWb + 1
+ { 0x1f, 6, NULL, extract_cslwb, 0 },
+
+#define CSLWn CSLWb + 1
+ { 0x1f, 11, insert_cslwn, NULL, 0 },
+
+#define ILWn CSLWn + 1
+ { 0x1f, 1, NULL, extract_ilwn, PPC_OPERAND_PLUS1 },
+
+#define ILWb ILWn + 1
+ { 0x1f, 6, insert_ilwb, NULL, 0 },
+
+#define IRWn ILWb + 1
+ { 0x1f, 1, NULL, extract_irwn, PPC_OPERAND_PLUS1 },
+
+#define IRWb IRWn + 1
+ { 0x1f, 6, insert_irwb, NULL, 0 },
+
/* The MB and ME fields in an M form instruction expressed a single
operand which is a bitmask indicating which bits to select. This
is a two operand form using PPC_OPERAND_NEXT. See the
description in opcode/ppc.h for what this means. */
-#define MBE ME + 1
+#define MBE IRWb + 1
{ 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
{ -1, 0, insert_mbe, extract_mbe, 0 },
@@ -3130,7 +3384,16 @@ const struct powerpc_operand powerpc_operands[] =
#define UIM5 SH
{ 0x1f, 11, NULL, NULL, 0 },
-#define EVUIMM_LT8 SH + 1
+#define RRWn SH + 1
+ { 0x1f, 11, insert_rrwn, extract_rrwn, 0 },
+
+#define SLWn RRWn + 1
+ { 0x1f, 11, insert_slwn, extract_slwn, 0 },
+
+#define SRWn SLWn + 1
+ { 0x1f, 11, insert_srwn, extract_srwn, 0 },
+
+#define EVUIMM_LT8 SRWn + 1
{ 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 },
#define EVUIMM_LT16 EVUIMM_LT8 + 1
@@ -3823,12 +4086,21 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
(M ((op), (rc)) \
| ((((uint64_t)(me)) & 0x1f) << 1))
+/* An M_MASK with the MB field fixed. */
+#define MMB_MASK (M_MASK | MB_MASK)
+
+/* An M_MASK with the ME field fixed. */
+#define MME_MASK (M_MASK | ME_MASK)
+
/* An M_MASK with the MB and ME fields fixed. */
#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
/* An M_MASK with the SH and ME fields fixed. */
#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
+/* An M_MASK with the SH and MB fields fixed. */
+#define MSHMB_MASK (M_MASK | SH_MASK | MB_MASK)
+
/* An MD form instruction. */
#define MD(op, xop, rc) \
(OP (op) \
@@ -6425,18 +6697,40 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
+{"inslwi", M(20,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ILWn, ILWb}},
+{"insrwi", M(20,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, IRWn, IRWb}},
{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
+{"inslwi.", M(20,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ILWn, ILWb}},
+{"insrwi.", M(20,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, IRWn, IRWb}},
{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SH}},
+{"rotrwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RRWn}},
{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, MB}},
+{"clrrwi", M(21,0), MSHMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CRWn}},
+{"slwi", M(21,0), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SLWn}},
+{"srwi", MME(21,31,0), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SRWn}},
{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
+{"extlwi", M(21,0), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ELWn, SH}},
+{"extrwi", MME(21,31,0), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ERWn, ERWb}},
+{"clrlslwi", M(21,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CSLWb, CSLWn}},
+{"sli", M(21,0), MMB_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SLWn}},
+{"sri", MME(21,31,0), MME_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SRWn}},
{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SH}},
+{"rotrwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RRWn}},
{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, MB}},
+{"clrrwi.", M(21,1), MSHMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CRWn}},
+{"slwi.", M(21,1), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SLWn}},
+{"srwi.", MME(21,31,1), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SRWn}},
{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
+{"extlwi.", M(21,1), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ELWn, SH}},
+{"extrwi.", MME(21,31,1), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ERWn, ERWb}},
+{"clrlslwi.", M(21,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CSLWb, CSLWn}},
+{"sli.", M(21,1), MMB_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SLWn}},
+{"sri.", MME(21,31,1), MME_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SRWn}},
{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
@@ -10192,29 +10486,6 @@ const unsigned int vle_num_opcodes =
support extracting the whole word (32 bits in this case). */
const struct powerpc_macro powerpc_macros[] = {
-{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
-{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
-{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
-{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
-{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
-{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
-{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
-{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
-{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
-{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
-{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
-{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
-{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
-{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
-{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
-{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
-{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
-{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
-{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
-{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
-{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
-{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
-
{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/5] PowerPC VLE extended instructions in powerpc_macros
2022-03-15 23:40 [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros Alan Modra
2022-03-15 23:40 ` [PATCH 2/5] PowerPC32 " Alan Modra
@ 2022-03-15 23:40 ` Alan Modra
2022-03-15 23:40 ` [PATCH 4/5] PowerPC SPE/SPE2 aliases " Alan Modra
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Alan Modra @ 2022-03-15 23:40 UTC (permalink / raw)
To: binutils
This moves VLE insn out of the macro table. "e_slwi" and "e_srwi"
already exist in vle_opcodes as distinct instructions rather than
encodings of e_rlwinm.
opcodes/
* ppc-opc.c (vle_opcodes): Typo fix e_rlwinm operand.
Add "e_inslwi", "e_insrwi", "e_rotlwi", "e_rotrwi", "e_clrlwi",
"e_clrrwi", "e_extlwi", "e_extrwi", and "e_clrlslwi".
(powerpc_macros): Delete same. Delete "e_slwi" and "e_srwi" too.
gas/
* testsuite/gas/ppc/vle-simple-5.d: Update.
diff --git a/gas/testsuite/gas/ppc/vle-simple-5.d b/gas/testsuite/gas/ppc/vle-simple-5.d
index 817df09d1cd..faae5f34abf 100644
--- a/gas/testsuite/gas/ppc/vle-simple-5.d
+++ b/gas/testsuite/gas/ppc/vle-simple-5.d
@@ -7,14 +7,14 @@
Disassembly of section .text:
0+0 <.text>:
- 0: 74 42 00 01 e_rlwinm r2,r2,0,0,0
+ 0: 74 42 00 01 e_clrrwi r2,r2,31
4: 74 62 7d bf e_rlwinm r2,r3,15,22,31
8: 74 a4 f8 48 e_rlwimi r4,r5,31,1,4
c: 74 e6 c9 4c e_rlwimi r6,r7,25,5,6
- 10: 74 41 50 3f e_rlwinm r1,r2,10,0,31
- 14: 74 83 c0 3f e_rlwinm r3,r4,24,0,31
+ 10: 74 41 50 3f e_rotlwi r1,r2,10
+ 14: 74 83 c0 3f e_rotlwi r3,r4,24
18: 7c 62 f8 70 e_slwi r2,r3,31
1c: 7c 25 f4 70 e_srwi r5,r1,30
- 20: 74 64 07 7f e_rlwinm r4,r3,0,29,31
- 24: 74 41 00 07 e_rlwinm r1,r2,0,0,3
+ 20: 74 64 07 7f e_clrlwi r4,r3,29
+ 24: 74 41 00 07 e_clrrwi r1,r2,28
28: 74 e6 d8 49 e_rlwinm r6,r7,27,1,4
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 45d07196309..12c1c414b7d 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -10366,7 +10366,16 @@ const struct powerpc_opcode vle_opcodes[] = {
{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
-{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
+{"e_inslwi", M(29,0), M_MASK, PPCVLE, EXT, {RA, RS, ILWn, ILWb}},
+{"e_insrwi", M(29,0), M_MASK, PPCVLE, EXT, {RA, RS, IRWn, IRWb}},
+{"e_rotlwi", MME(29,31,1), MMBME_MASK, PPCVLE, EXT, {RA, RS, SH}},
+{"e_rotrwi", MME(29,31,1), MMBME_MASK, PPCVLE, EXT, {RA, RS, RRWn}},
+{"e_clrlwi", MME(29,31,1), MSHME_MASK, PPCVLE, EXT, {RA, RS, MB}},
+{"e_clrrwi", M(29,1), MSHMB_MASK, PPCVLE, EXT, {RA, RS, CRWn}},
+{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RS, SH, MBE, ME}},
+{"e_extlwi", M(29,1), MMB_MASK, PPCVLE, EXT, {RA, RS, ELWn, SH}},
+{"e_extrwi", MME(29,31,1), MME_MASK, PPCVLE, EXT, {RA, RS, ERWn, ERWb}},
+{"e_clrlslwi", M(29,1), M_MASK, PPCVLE, EXT, {RA, RS, CSLWb, CSLWn}},
{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, EXT, {B15}},
@@ -10486,18 +10495,6 @@ const unsigned int vle_num_opcodes =
support extracting the whole word (32 bits in this case). */
const struct powerpc_macro powerpc_macros[] = {
-{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
-{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
-{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
-{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
-{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
-{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
-{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
-{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
-{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
-{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
-{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
-
/* old SPE instructions have new names with the same opcodes */
{"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"},
{"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"},
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/5] PowerPC SPE/SPE2 aliases in powerpc_macros
2022-03-15 23:40 [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros Alan Modra
2022-03-15 23:40 ` [PATCH 2/5] PowerPC32 " Alan Modra
2022-03-15 23:40 ` [PATCH 3/5] PowerPC VLE " Alan Modra
@ 2022-03-15 23:40 ` Alan Modra
2022-03-15 23:40 ` [PATCH 5/5] Delete PowerPC macro insn support Alan Modra
2022-03-18 21:40 ` [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros Peter Bergner
4 siblings, 0 replies; 6+ messages in thread
From: Alan Modra @ 2022-03-15 23:40 UTC (permalink / raw)
To: binutils
* ppc-opc.c (powerpc_macros): Move "evsadd", "evssub", "evsabs",
"evsnabs", "evsneg", "evsmul", "evsdiv", "evscmpgt", "evsgmplt",
"evsgmpeq", "evscfui", "evscfsi", "evscfuf", "evscfsf", "evsctui",
"evsctsi", "evsctuf", "evsctsf", "evsctuiz", "evsctsiz",
"evststgt", "evststlt", "evststeq"..
(powerpc_opcodes): ..to here.
(powerpc_macros): Move "evdotphsssi", "evdotphsssia", "evdotpwsssi",
and "evdotpwsssia"..
(spe2_opcodes): ..to here.
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 12c1c414b7d..df0d5417d23 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -5254,48 +5254,71 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
{"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"evsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"evssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
+{"evsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
+{"evsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
+{"evsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}},
{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"vmuleud", VX (4, 712), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"evsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"evsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evsgmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evsgmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"vinsdlx", VX (4, 719), VX_MASK, POWER10, 0, {VD, RA, RB}},
{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"evsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
+{"evststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
@@ -10495,36 +10518,6 @@ const unsigned int vle_num_opcodes =
support extracting the whole word (32 bits in this case). */
const struct powerpc_macro powerpc_macros[] = {
-/* old SPE instructions have new names with the same opcodes */
-{"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"},
-{"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"},
-{"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"},
-{"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"},
-{"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"},
-{"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"},
-{"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"},
-{"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"},
-{"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"},
-{"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"},
-{"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"},
-{"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"},
-{"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"},
-{"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"},
-{"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"},
-{"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"},
-{"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"},
-{"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"},
-{"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"},
-{"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"},
-{"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"},
-{"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"},
-{"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"},
-
-/* SPE2 instructions which just are mapped to SPE2 */
-{"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"},
-{"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"},
-{"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"},
-{"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"}
};
const int powerpc_num_macros =
@@ -10622,6 +10615,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
{"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
@@ -10645,6 +10639,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
{"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
@@ -10717,6 +10712,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
{"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwsssi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
@@ -10732,6 +10728,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
{"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwsssia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 5/5] Delete PowerPC macro insn support
2022-03-15 23:40 [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros Alan Modra
` (2 preceding siblings ...)
2022-03-15 23:40 ` [PATCH 4/5] PowerPC SPE/SPE2 aliases " Alan Modra
@ 2022-03-15 23:40 ` Alan Modra
2022-03-18 21:40 ` [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros Peter Bergner
4 siblings, 0 replies; 6+ messages in thread
From: Alan Modra @ 2022-03-15 23:40 UTC (permalink / raw)
To: binutils
Let's hope this stays dead, but it's here as a patch separate from
those that removed use of powerpc_macros just in case it needs to be
resurrected.
include/
* opcode/ppc.h (struct powerpc_macro): Delete declaration.
(powerpc_macros, powerpc_num_macros): Likewise..
opcodes/
* ppc-opc.c (powerpc_macros, powerpc_num_macros): Delete.
gas/
* config/tc-ppc.c (ppc_macro): Delete function.
(ppc_macro_hash): Delete.
(ppc_setup_opcodes, md_assemble): Delete macro support.
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index cf11f7adc6c..1aa5fcc8b82 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -85,7 +85,6 @@ static int set_target_endian = 0;
static bool reg_names_p = TARGET_REG_NAMES_P;
-static void ppc_macro (char *, const struct powerpc_macro *);
static void ppc_byte (int);
#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
@@ -980,9 +979,6 @@ static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64;
/* Opcode hash table. */
static htab_t ppc_hash;
-/* Macro hash table. */
-static htab_t ppc_macro_hash;
-
#ifdef OBJ_ELF
/* What type of shared library support to use. */
static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE;
@@ -1617,22 +1613,18 @@ insn_validate (const struct powerpc_opcode *op)
return false;
}
-/* Insert opcodes and macros into hash tables. Called at startup and
- for .machine pseudo. */
+/* Insert opcodes into hash tables. Called at startup and for
+ .machine pseudo. */
static void
ppc_setup_opcodes (void)
{
const struct powerpc_opcode *op;
const struct powerpc_opcode *op_end;
- const struct powerpc_macro *macro;
- const struct powerpc_macro *macro_end;
bool bad_insn = false;
if (ppc_hash != NULL)
htab_delete (ppc_hash);
- if (ppc_macro_hash != NULL)
- htab_delete (ppc_macro_hash);
/* Insert the opcodes into a hash table. */
ppc_hash = str_htab_create ();
@@ -1839,19 +1831,6 @@ ppc_setup_opcodes (void)
str_hash_insert (ppc_hash, op->name, op, 0);
}
- /* Insert the macros into a hash table. */
- ppc_macro_hash = str_htab_create ();
-
- macro_end = powerpc_macros + powerpc_num_macros;
- for (macro = powerpc_macros; macro < macro_end; macro++)
- if (((macro->flags & ppc_cpu) != 0
- || (ppc_cpu & PPC_OPCODE_ANY) != 0)
- && str_hash_insert (ppc_macro_hash, macro->name, macro, 0) != NULL)
- {
- as_bad (_("duplicate %s"), macro->name);
- bad_insn = true;
- }
-
if (bad_insn)
abort ();
}
@@ -3292,15 +3271,7 @@ md_assemble (char *str)
opcode = (const struct powerpc_opcode *) str_hash_find (ppc_hash, str);
if (opcode == (const struct powerpc_opcode *) NULL)
{
- const struct powerpc_macro *macro;
-
- macro = (const struct powerpc_macro *) str_hash_find (ppc_macro_hash,
- str);
- if (macro == (const struct powerpc_macro *) NULL)
- as_bad (_("unrecognized opcode: `%s'"), str);
- else
- ppc_macro (s, macro);
-
+ as_bad (_("unrecognized opcode: `%s'"), str);
ppc_clear_labels ();
return;
}
@@ -4133,85 +4104,6 @@ md_assemble (char *str)
fixP->fx_pcrel_adjust = fixups[i].opindex;
}
}
-
-/* Handle a macro. Gather all the operands, transform them as
- described by the macro, and call md_assemble recursively. All the
- operands are separated by commas; we don't accept parentheses
- around operands here. */
-
-static void
-ppc_macro (char *str, const struct powerpc_macro *macro)
-{
- char *operands[10];
- unsigned int count;
- char *s;
- unsigned int len;
- const char *format;
- unsigned int arg;
- char *send;
- char *complete;
-
- /* Gather the users operands into the operands array. */
- count = 0;
- s = str;
- while (1)
- {
- if (count >= sizeof operands / sizeof operands[0])
- break;
- operands[count++] = s;
- s = strchr (s, ',');
- if (s == (char *) NULL)
- break;
- *s++ = '\0';
- }
-
- if (count != macro->operands)
- {
- as_bad (_("wrong number of operands"));
- return;
- }
-
- /* Work out how large the string must be (the size is unbounded
- because it includes user input). */
- len = 0;
- format = macro->format;
- while (*format != '\0')
- {
- if (*format != '%')
- {
- ++len;
- ++format;
- }
- else
- {
- arg = strtol (format + 1, &send, 10);
- know (send != format && arg < count);
- len += strlen (operands[arg]);
- format = send;
- }
- }
-
- /* Put the string together. */
- complete = s = XNEWVEC (char, len + 1);
- format = macro->format;
- while (*format != '\0')
- {
- if (*format != '%')
- *s++ = *format++;
- else
- {
- arg = strtol (format + 1, &send, 10);
- strcpy (s, operands[arg]);
- s += strlen (s);
- format = send;
- }
- }
- *s = '\0';
-
- /* Assemble the constructed instruction. */
- md_assemble (complete);
- free (complete);
-}
\f
#ifdef OBJ_ELF
/* For ELF, add support for SHT_ORDERED. */
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 463965dab58..a9c25298311 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -453,32 +453,6 @@ extern const unsigned int num_powerpc_operands;
#define PPC_OPERAND_FSL (0x800000)
#define PPC_OPERAND_FCR (0x1000000)
#define PPC_OPERAND_UDI (0x2000000)
-\f
-/* The POWER and PowerPC assemblers use a few macros. We keep them
- with the operands table for simplicity. The macro table is an
- array of struct powerpc_macro. */
-
-struct powerpc_macro
-{
- /* The macro name. */
- const char *name;
-
- /* The number of operands the macro takes. */
- unsigned int operands;
-
- /* One bit flags for the opcode. These are used to indicate which
- specific processors support the instructions. The values are the
- same as those for the struct powerpc_opcode flags field. */
- ppc_cpu_t flags;
-
- /* A format string to turn the macro into a normal instruction.
- Each %N in the string is replaced with operand number N (zero
- based). */
- const char *format;
-};
-
-extern const struct powerpc_macro powerpc_macros[];
-extern const int powerpc_num_macros;
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index df0d5417d23..bd83d44a2ae 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -10504,24 +10504,6 @@ const struct powerpc_opcode vle_opcodes[] = {
const unsigned int vle_num_opcodes =
sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
-\f
-/* The macro table. This is only used by the assembler. */
-
-/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
- when x=0; 32-x when x is between 1 and 31; are negative if x is
- negative; and are 32 or more otherwise. This is what you want
- when, for instance, you are emulating a right shift by a
- rotate-left-and-mask, because the underlying instructions support
- shifts of size 0 but not shifts of size 32. By comparison, when
- extracting x bits from some word you want to use just 32-x, because
- the underlying instructions don't support extracting 0 bits but do
- support extracting the whole word (32 bits in this case). */
-
-const struct powerpc_macro powerpc_macros[] = {
-};
-
-const int powerpc_num_macros =
- sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
/* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */
const struct powerpc_opcode spe2_opcodes[] = {
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros
2022-03-15 23:40 [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros Alan Modra
` (3 preceding siblings ...)
2022-03-15 23:40 ` [PATCH 5/5] Delete PowerPC macro insn support Alan Modra
@ 2022-03-18 21:40 ` Peter Bergner
4 siblings, 0 replies; 6+ messages in thread
From: Peter Bergner @ 2022-03-18 21:40 UTC (permalink / raw)
To: Alan Modra, binutils
On 3/15/22 6:40 PM, Alan Modra via Binutils wrote:
> The extended instructions implemented in powerpc_macros aren't used by
> the disassembler. That means instructions like "sldi r3,r3,2" appear
> in disassembly as "rldicr r3,r3,2,61", which is annoying since many
> other extended instructions are shown.
>
> Note that some of the instructions moved out of the macro table to the
> opcode table won't appear in disassembly, because they are aliases
> rather than a subset of the underlying raw instruction. If enabled,
> rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all
> occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many
> occurrences in the case of clrlsldi if n <= b was added to the extract
> functions.)
Very nice! I hated the macros table, especially because we never did get
the rldicl extended mnemonics in our disassembly. Thanks!!!
Peter
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-03-18 21:40 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-15 23:40 [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros Alan Modra
2022-03-15 23:40 ` [PATCH 2/5] PowerPC32 " Alan Modra
2022-03-15 23:40 ` [PATCH 3/5] PowerPC VLE " Alan Modra
2022-03-15 23:40 ` [PATCH 4/5] PowerPC SPE/SPE2 aliases " Alan Modra
2022-03-15 23:40 ` [PATCH 5/5] Delete PowerPC macro insn support Alan Modra
2022-03-18 21:40 ` [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros Peter Bergner
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