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From: Andrew Burgess <>
Cc: Andrew Burgess <>
Subject: [PATCH] opcodes/riscv: style csr names as registers
Date: Mon,  3 Oct 2022 11:13:28 +0100	[thread overview]
Message-ID: <> (raw)

While reviewing another patch I noticed that RISC-V CSR names are
given the text style, not the register style.  This patch fixes this
 opcodes/riscv-dis.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 6ac69490b78..031c19334fa 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -547,7 +547,8 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    if (riscv_csr_hash[csr] != NULL)
-	      print (info->stream, dis_style_text, "%s", riscv_csr_hash[csr]);
+	      print (info->stream, dis_style_register, "%s",
+		     riscv_csr_hash[csr]);
 	      print (info->stream, dis_style_text, "0x%x", csr);

             reply	other threads:[~2022-10-03 10:13 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-03 10:13 Andrew Burgess [this message]
2022-10-03 10:52 ` Tsukasa OI
2022-10-04  1:10 ` Nelson Chu
2022-10-04  8:53   ` Andrew Burgess

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