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From: Nelson Chu <nelson@rivosinc.com>
To: Andrew Burgess <aburgess@redhat.com>
Cc: binutils@sourceware.org
Subject: Re: [PATCH] opcodes/riscv: style csr names as registers
Date: Tue, 4 Oct 2022 09:10:15 +0800	[thread overview]
Message-ID: <CAPpQWtDENj1hhVBkFnWW-_r8Ze4tOKEH0eA-gVJz2iapUgT_ZA@mail.gmail.com> (raw)
In-Reply-To: <20221003101328.1790113-1-aburgess@redhat.com>

Please commit, thanks.

Nelson

On Mon, Oct 3, 2022 at 6:14 PM Andrew Burgess via Binutils
<binutils@sourceware.org> wrote:
>
> While reviewing another patch I noticed that RISC-V CSR names are
> given the text style, not the register style.  This patch fixes this
> mistake.
> ---
>  opcodes/riscv-dis.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 6ac69490b78..031c19334fa 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -547,7 +547,8 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
>               }
>
>             if (riscv_csr_hash[csr] != NULL)
> -             print (info->stream, dis_style_text, "%s", riscv_csr_hash[csr]);
> +             print (info->stream, dis_style_register, "%s",
> +                    riscv_csr_hash[csr]);
>             else
>               print (info->stream, dis_style_text, "0x%x", csr);
>             break;
> --
> 2.25.4
>

  parent reply	other threads:[~2022-10-04  1:10 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-03 10:13 Andrew Burgess
2022-10-03 10:52 ` Tsukasa OI
2022-10-04  1:10 ` Nelson Chu [this message]
2022-10-04  8:53   ` Andrew Burgess

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