From: Andrew Burgess <aburgess@redhat.com>
To: binutils@sourceware.org
Cc: Andrew Burgess <aburgess@redhat.com>
Subject: [PATCHv2 1/2] opcodes/arm: use '@' consistently for the comment character
Date: Mon, 3 Oct 2022 17:37:36 +0100 [thread overview]
Message-ID: <e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com> (raw)
Message-ID: <20221003163736.4DDlMg_IToKsb30G9tZ6p9YEU8pyrpULnkciY3b1d4M@z> (raw)
In-Reply-To: <cover.1664707612.git.aburgess@redhat.com>
This is a resend of patch 1/2. My first attempt to send this message
got stuck in the moderation queue due to its size.
In order to get this to the list I've removed all of the changes to
the test results from this email, but obviously they are still
included in my local patch.
The important changes, in opcodes/arm-dis.c, are included below.
---
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then started a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is event harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated after this change.
---
gas/testsuite/gas/arm/adr.d | 2 +-
gas/testsuite/gas/arm/adrl.d | 20 +-
gas/testsuite/gas/arm/arch4t-eabi.d | 8 +-
gas/testsuite/gas/arm/arch4t.d | 8 +-
gas/testsuite/gas/arm/arch7.d | 4 +-
gas/testsuite/gas/arm/arch7a-mp.d | 6 +-
gas/testsuite/gas/arm/arch7r-mp.d | 6 +-
gas/testsuite/gas/arm/archv6t2.d | 10 +-
gas/testsuite/gas/arm/archv8m-base.d | 12 +-
gas/testsuite/gas/arm/archv8m-main-dsp-1.d | 12 +-
gas/testsuite/gas/arm/archv8m-main.d | 12 +-
gas/testsuite/gas/arm/arm3.d | 2 +-
gas/testsuite/gas/arm/arm6.d | 4 +-
gas/testsuite/gas/arm/arm7dm.d | 6 +-
gas/testsuite/gas/arm/arm7t.d | 26 +-
gas/testsuite/gas/arm/armv1.d | 8 +-
gas/testsuite/gas/arm/armv7-a+virt.d | 4 +-
.../gas/arm/armv8-2-fp16-scalar-ext.d | 8 +-
.../gas/arm/armv8-2-fp16-scalar-thumb-ext.d | 8 +-
.../gas/arm/armv8-2-fp16-scalar-thumb.d | 8 +-
gas/testsuite/gas/arm/armv8-2-fp16-scalar.d | 8 +-
gas/testsuite/gas/arm/armv8.1-m.main-fp.d | 70 +--
gas/testsuite/gas/arm/armv8.1-m.main-hp.d | 8 +-
gas/testsuite/gas/arm/bl-local-2.d | 10 +-
gas/testsuite/gas/arm/bl-local-v4t.d | 10 +-
gas/testsuite/gas/arm/blx-bad.d | 14 +-
gas/testsuite/gas/arm/blx-local-thumb.d | 10 +-
gas/testsuite/gas/arm/blx-local.d | 12 +-
gas/testsuite/gas/arm/branch-reloc.d | 10 +-
gas/testsuite/gas/arm/ccs.d | 2 +-
.../gas/arm/copro-arm_v2plus-arm_v2.d | 8 +-
.../gas/arm/copro-arm_v5plus-arm_v5.d | 4 +-
.../arm/copro-thumb_v6t2plus-thumb_v6t2-1.d | 4 +-
.../arm/copro-thumb_v6t2plus-thumb_v6t2-2.d | 4 +-
gas/testsuite/gas/arm/crc32-armv8-a-bad.d | 24 +-
gas/testsuite/gas/arm/crc32-armv8-r-bad.d | 24 +-
gas/testsuite/gas/arm/dis-data3.d | 2 +-
gas/testsuite/gas/arm/el_segundo.d | 2 +-
gas/testsuite/gas/arm/float.d | 2 +-
gas/testsuite/gas/arm/group-reloc-alu.d | 160 ++---
gas/testsuite/gas/arm/group-reloc-ldrs.d | 240 ++++----
gas/testsuite/gas/arm/immed.d | 10 +-
gas/testsuite/gas/arm/immed2.d | 2 +-
gas/testsuite/gas/arm/inst.d | 36 +-
gas/testsuite/gas/arm/iwmmxt.d | 2 +-
gas/testsuite/gas/arm/ldconst.d | 42 +-
gas/testsuite/gas/arm/ldr-global.d | 14 +-
gas/testsuite/gas/arm/ldr-t.d | 16 +-
gas/testsuite/gas/arm/ldr.d | 10 +-
gas/testsuite/gas/arm/ldst-offset0.d | 6 +-
gas/testsuite/gas/arm/ldst-pc.d | 8 +-
gas/testsuite/gas/arm/m0-load-pseudo.d | 4 +-
gas/testsuite/gas/arm/m23-load-pseudo.d | 4 +-
gas/testsuite/gas/arm/m33-load-pseudo.d | 4 +-
gas/testsuite/gas/arm/macro1.d | 6 +-
gas/testsuite/gas/arm/mapdir.d | 4 +-
gas/testsuite/gas/arm/mapmisc.d | 38 +-
gas/testsuite/gas/arm/mapsecs.d | 10 +-
gas/testsuite/gas/arm/mapshort-eabi.d | 10 +-
gas/testsuite/gas/arm/mapshort-elf.d | 10 +-
gas/testsuite/gas/arm/mask_1-armv8-a.d | 32 +-
gas/testsuite/gas/arm/mask_1-armv8-r.d | 32 +-
gas/testsuite/gas/arm/mrs-msr-arm-v6.d | 6 +-
gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d | 6 +-
gas/testsuite/gas/arm/msr-imm.d | 268 ++++-----
gas/testsuite/gas/arm/mve-vand.d | 94 +--
gas/testsuite/gas/arm/mve-vbic.d | 20 +-
gas/testsuite/gas/arm/mve-vcvt-3.d | 80 +--
gas/testsuite/gas/arm/mve-vmov-1.d | 20 +-
gas/testsuite/gas/arm/mve-vmov-2.d | 34 +-
.../gas/arm/mve-vmov-vmvn-vorr-vbic.d | 64 +-
gas/testsuite/gas/arm/mve-vmvn.d | 114 ++--
gas/testsuite/gas/arm/mve-vorn.d | 22 +-
gas/testsuite/gas/arm/mve-vorr.d | 20 +-
gas/testsuite/gas/arm/neon-cond-bad_t2.d | 4 +-
gas/testsuite/gas/arm/neon-const.d | 516 ++++++++--------
gas/testsuite/gas/arm/neon-cov.d | 564 +++++++++---------
gas/testsuite/gas/arm/neon-ldst-rm.d | 4 +-
gas/testsuite/gas/arm/neon-logic.d | 8 +-
gas/testsuite/gas/arm/nops.d | 2 +-
gas/testsuite/gas/arm/offset-1.d | 8 +-
gas/testsuite/gas/arm/offset.d | 8 +-
gas/testsuite/gas/arm/pr21458.d | 14 +-
gas/testsuite/gas/arm/pr24907.d | 6 +-
gas/testsuite/gas/arm/pr25235.d | 14 +-
gas/testsuite/gas/arm/push-pop.d | 8 +-
gas/testsuite/gas/arm/reg-alias.d | 6 +-
gas/testsuite/gas/arm/relax_branch_align.d | 8 +-
gas/testsuite/gas/arm/relax_load_align.d | 6 +-
gas/testsuite/gas/arm/sp-pc-usage-t.d | 8 +-
gas/testsuite/gas/arm/tcompat.d | 6 +-
gas/testsuite/gas/arm/tcompat2.d | 8 +-
gas/testsuite/gas/arm/thumb-eabi.d | 42 +-
gas/testsuite/gas/arm/thumb-nop.d | 4 +-
gas/testsuite/gas/arm/thumb.d | 42 +-
gas/testsuite/gas/arm/thumb1_unified.d | 4 +-
gas/testsuite/gas/arm/thumb2_add.d | 38 +-
gas/testsuite/gas/arm/thumb2_invert.d | 24 +-
gas/testsuite/gas/arm/thumb2_pool.d | 32 +-
gas/testsuite/gas/arm/thumb2_relax.d | 52 +-
gas/testsuite/gas/arm/thumb2_vpool.d | 158 ++---
gas/testsuite/gas/arm/thumb2_vpool_be.d | 158 ++---
gas/testsuite/gas/arm/thumb32.d | 186 +++---
gas/testsuite/gas/arm/thumbv6.d | 8 +-
gas/testsuite/gas/arm/thumbv6k.d | 8 +-
gas/testsuite/gas/arm/tls.d | 14 +-
gas/testsuite/gas/arm/tls_vxworks.d | 6 +-
gas/testsuite/gas/arm/udf.d | 24 +-
gas/testsuite/gas/arm/unpredictable.d | 2 +-
gas/testsuite/gas/arm/vfp-mov-enc.d | 18 +-
gas/testsuite/gas/arm/vfp-neon-overlap.d | 8 +-
gas/testsuite/gas/arm/vfp1.d | 6 +-
gas/testsuite/gas/arm/vfp1xD.d | 76 +--
gas/testsuite/gas/arm/vfp1xD_t2.d | 70 +--
gas/testsuite/gas/arm/vfpv3-32drs.d | 6 +-
gas/testsuite/gas/arm/vldconst.d | 246 ++++----
gas/testsuite/gas/arm/vldconst_be.d | 246 ++++----
gas/testsuite/gas/arm/vldr.d | 4 +-
gas/testsuite/gas/arm/wince.d | 12 +-
gas/testsuite/gas/arm/wince_inst.d | 36 +-
gas/testsuite/gas/arm/xscale.d | 4 +-
ld/testsuite/ld-arm/arm-app-abs32.d | 8 +-
ld/testsuite/ld-arm/arm-app.d | 6 +-
ld/testsuite/ld-arm/arm-be8.d | 2 +-
ld/testsuite/ld-arm/arm-call.d | 8 +-
ld/testsuite/ld-arm/arm-lib-plt32.d | 6 +-
ld/testsuite/ld-arm/arm-lib.d | 6 +-
ld/testsuite/ld-arm/arm-movwt.d | 40 +-
ld/testsuite/ld-arm/arm-pic-veneer.d | 4 +-
ld/testsuite/ld-arm/armthumb-lib.d | 16 +-
ld/testsuite/ld-arm/attr-merge-wchar-24.d | 2 +-
ld/testsuite/ld-arm/attr-merge-wchar-42.d | 2 +-
ld/testsuite/ld-arm/callweak.d | 2 +-
ld/testsuite/ld-arm/cortex-a8-far.d | 6 +-
ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d | 8 +-
ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d | 8 +-
ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d | 8 +-
.../ld-arm/cortex-a8-fix-bl-rel-plt.d | 8 +-
ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d | 8 +-
.../ld-arm/farcall-arm-arm-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-arm.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-nacl-pic.d | 4 +-
ld/testsuite/ld-arm/farcall-arm-nacl.d | 4 +-
.../ld-arm/farcall-arm-thumb-blx-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-thumb-blx.d | 2 +-
.../ld-arm/farcall-arm-thumb-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-thumb.d | 2 +-
ld/testsuite/ld-arm/farcall-data-nacl.d | 4 +-
ld/testsuite/ld-arm/farcall-data.d | 2 +-
ld/testsuite/ld-arm/farcall-group-limit.d | 2 +-
ld/testsuite/ld-arm/farcall-group-size2.d | 10 +-
ld/testsuite/ld-arm/farcall-group.d | 10 +-
ld/testsuite/ld-arm/farcall-mix.d | 10 +-
ld/testsuite/ld-arm/farcall-mix2.d | 10 +-
ld/testsuite/ld-arm/farcall-mixed-app-v5.d | 26 +-
ld/testsuite/ld-arm/farcall-mixed-app.d | 26 +-
ld/testsuite/ld-arm/farcall-mixed-app2.d | 28 +-
ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d | 36 +-
ld/testsuite/ld-arm/farcall-mixed-lib.d | 24 +-
.../ld-arm/farcall-thumb-arm-blx-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-arm-blx.d | 2 +-
.../ld-arm/farcall-thumb-arm-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-arm.d | 2 +-
.../farcall-thumb-thumb-blx-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d | 2 +-
.../ld-arm/farcall-thumb-thumb-m-no-profile.d | 2 +-
.../ld-arm/farcall-thumb-thumb-m-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-thumb-m.d | 2 +-
.../ld-arm/farcall-thumb-thumb-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-thumb.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb2-purecode.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb2-thumb2-m.d | 2 +-
ld/testsuite/ld-arm/fdpic-main-m.d | 16 +-
ld/testsuite/ld-arm/fdpic-main.d | 16 +-
ld/testsuite/ld-arm/fdpic-shared-m.d | 4 +-
ld/testsuite/ld-arm/fdpic-shared.d | 4 +-
ld/testsuite/ld-arm/fix-arm1176-off.d | 2 +-
ld/testsuite/ld-arm/fix-arm1176-on.d | 2 +-
ld/testsuite/ld-arm/gc-hidden-1.d | 2 +-
ld/testsuite/ld-arm/group-relocs.d | 58 +-
ld/testsuite/ld-arm/ifunc-1.dd | 50 +-
ld/testsuite/ld-arm/ifunc-10.dd | 236 ++++----
ld/testsuite/ld-arm/ifunc-11.dd | 28 +-
ld/testsuite/ld-arm/ifunc-12.dd | 28 +-
ld/testsuite/ld-arm/ifunc-13.dd | 28 +-
ld/testsuite/ld-arm/ifunc-14.dd | 42 +-
ld/testsuite/ld-arm/ifunc-15.dd | 42 +-
ld/testsuite/ld-arm/ifunc-16.dd | 36 +-
ld/testsuite/ld-arm/ifunc-17.dd | 2 +-
ld/testsuite/ld-arm/ifunc-2.dd | 146 ++---
ld/testsuite/ld-arm/ifunc-3.dd | 40 +-
ld/testsuite/ld-arm/ifunc-4.dd | 236 ++++----
ld/testsuite/ld-arm/ifunc-5.dd | 26 +-
ld/testsuite/ld-arm/ifunc-6.dd | 38 +-
ld/testsuite/ld-arm/ifunc-7.dd | 18 +-
ld/testsuite/ld-arm/ifunc-8.dd | 118 ++--
ld/testsuite/ld-arm/ifunc-9.dd | 56 +-
.../jump-reloc-veneers-cond-long-backward.d | 2 +-
.../ld-arm/jump-reloc-veneers-cond-long.d | 2 +-
ld/testsuite/ld-arm/jump-reloc-veneers-long.d | 2 +-
ld/testsuite/ld-arm/long-plt-format.d | 4 +-
ld/testsuite/ld-arm/mixed-app-v5.d | 26 +-
ld/testsuite/ld-arm/mixed-app.d | 26 +-
ld/testsuite/ld-arm/mixed-lib.d | 12 +-
ld/testsuite/ld-arm/movw-merge.d | 4 +-
ld/testsuite/ld-arm/non-contiguous-arm2.d | 10 +-
ld/testsuite/ld-arm/non-contiguous-arm3.d | 12 +-
ld/testsuite/ld-arm/non-contiguous-arm5.d | 10 +-
ld/testsuite/ld-arm/non-contiguous-arm6.d | 12 +-
.../ld-arm/stm32l4xx-cannot-fix-far-ldm.d | 2 +-
ld/testsuite/ld-arm/stm32l4xx-fix-ldm.d | 8 +-
ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d | 2 +-
ld/testsuite/ld-arm/stm32l4xx-fix-vldm.d | 2 +-
ld/testsuite/ld-arm/thumb-plt.d | 4 +-
ld/testsuite/ld-arm/thumb1-adds.d | 12 +-
ld/testsuite/ld-arm/thumb1-movs.d | 10 +-
ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d | 2 +-
ld/testsuite/ld-arm/thumb2-bl-bad.d | 2 +-
ld/testsuite/ld-arm/tls-app.d | 4 +-
ld/testsuite/ld-arm/tls-descrelax-be32.d | 112 ++--
ld/testsuite/ld-arm/tls-descrelax-be8.d | 78 +--
ld/testsuite/ld-arm/tls-descrelax-v7.d | 78 +--
ld/testsuite/ld-arm/tls-descrelax.d | 112 ++--
ld/testsuite/ld-arm/tls-descseq.d | 20 +-
ld/testsuite/ld-arm/tls-gdesc-neg.d | 14 +-
ld/testsuite/ld-arm/tls-gdesc.d | 22 +-
ld/testsuite/ld-arm/tls-gdierelax.d | 8 +-
ld/testsuite/ld-arm/tls-gdierelax2.d | 10 +-
ld/testsuite/ld-arm/tls-gdlerelax.d | 4 +-
ld/testsuite/ld-arm/tls-lib-loc.d | 14 +-
ld/testsuite/ld-arm/tls-lib.d | 4 +-
ld/testsuite/ld-arm/tls-longplt-lib.d | 28 +-
ld/testsuite/ld-arm/tls-longplt.d | 30 +-
ld/testsuite/ld-arm/tls-thumb1.d | 36 +-
ld/testsuite/ld-arm/vxworks1-lib.dd | 12 +-
ld/testsuite/ld-arm/vxworks1.dd | 10 +-
opcodes/arm-dis.c | 96 +--
237 files changed, 3548 insertions(+), 3548 deletions(-)
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index caf3531ae3d..c73a7447b28 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -458,10 +458,10 @@ enum opcode_sentinel_enum
SENTINEL_GENERIC_START
} opcode_sentinels;
-#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
-#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
-#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
-#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
+#define UNDEFINED_INSTRUCTION "\t\t@ <UNDEFINED> instruction: %0-31x"
+#define UNKNOWN_INSTRUCTION_32BIT "\t\t@ <UNDEFINED> instruction: %08x"
+#define UNKNOWN_INSTRUCTION_16BIT "\t\t@ <UNDEFINED> instruction: %04x"
+#define UNPREDICTABLE_INSTRUCTION "\t@ <UNPREDICTABLE>"
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
@@ -846,13 +846,13 @@ static const struct sopcode32 coprocessor_opcodes[] =
0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
+ 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
+ 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
+ 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
+ 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
/* Data transfer between ARM and NEON registers. */
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -3657,7 +3657,7 @@ static const struct opcode32 arm_opcodes[] =
{
/* ARM instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
+ 0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0xe7f000f0, 0xfff000f0, "udf\t#%e"},
@@ -4140,7 +4140,7 @@ static const struct opcode32 arm_opcodes[] =
/* ARM Instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
+ 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
@@ -4303,7 +4303,7 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
+ 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
@@ -4419,7 +4419,7 @@ static const struct opcode32 arm_opcodes[] =
%c print the condition code
%C print the condition code, or "s" if not conditional
%x print warning if conditional an not at end of IT block"
- %X print "\t; unpredictable <IT:code>" if conditional
+ %X print "\t@ unpredictable <IT:code>" if conditional
%I print IT instruction suffix and operands
%W print Thumb Writeback indicator for LDMIA
%<bitfield>r print bitfield as an ARM register
@@ -4481,7 +4481,7 @@ static const struct opcode16 thumb_opcodes[] =
0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
/* ARM V4T ISA (Thumb v1). */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
+ 0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
/* Format 4. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
@@ -4546,7 +4546,7 @@ static const struct opcode16 thumb_opcodes[] =
/* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x4800, 0xF800,
- "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
+ "ldr%c\t%8-10r, [pc, #%0-7W]\t@ (%0-7a)"},
/* format 9 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
@@ -4568,7 +4568,7 @@ static const struct opcode16 thumb_opcodes[] =
0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
/* format 12 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
+ 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t@ (adr %8-10r, %0-7a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
/* format 15 */
@@ -4628,7 +4628,7 @@ static const struct opcode16 thumb_opcodes[] =
%P print address for pli instruction.
%c print the condition code
%x print warning if conditional an not at end of IT block"
- %X print "\t; unpredictable <IT:code>" if conditional
+ %X print "\t@ unpredictable <IT:code>" if conditional
%<bitfield>d print bitfield in decimal
%<bitfield>D print bitfield plus one in decimal
@@ -5488,7 +5488,7 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream,
func (stream, ", #%d", amount);
}
else if ((given & 0x80) == 0x80)
- func (stream, "\t; <illegal shifter operand>");
+ func (stream, "\t@ <illegal shifter operand>");
else if (print_shift)
func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
arm_regnames[(given & 0xf00) >> 8]);
@@ -7067,14 +7067,14 @@ print_simd_imm8 (struct disassemble_info *info, unsigned long given,
switch (size)
{
case 8:
- func (stream, "#%ld\t; 0x%.2lx", value, value);
+ func (stream, "#%ld\t@ 0x%.2lx", value, value);
break;
case 16:
func (stream,
printU
- ? "#%lu\t; 0x%.4lx"
- : "#%ld\t; 0x%.4lx", value, value);
+ ? "#%lu\t@ 0x%.4lx"
+ : "#%ld\t@ 0x%.4lx", value, value);
break;
case 32:
@@ -7094,14 +7094,14 @@ print_simd_imm8 (struct disassemble_info *info, unsigned long given,
(& floatformat_ieee_single_little, valbytes,
& fvalue);
- func (stream, "#%.7g\t; 0x%.8lx", fvalue,
+ func (stream, "#%.7g\t@ 0x%.8lx", fvalue,
value);
}
else
func (stream,
printU
- ? "#%lu\t; 0x%.8lx"
- : "#%ld\t; 0x%.8lx",
+ ? "#%lu\t@ 0x%.8lx"
+ : "#%ld\t@ 0x%.8lx",
(long) (((value & 0x80000000L) != 0)
&& !printU
? value | ~0xffffffffL : value),
@@ -8242,7 +8242,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
}
if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
{
- func (stream, "\t; ");
+ func (stream, "\t@ ");
/* For unaligned PCs, apply off-by-alignment
correction. */
info->print_address_func (offset + pc
@@ -8485,17 +8485,17 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
(16 + (value & 0xF));
if (!(decVal % 1000000))
- func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
+ func (stream, "%ld\t@ 0x%08x %c%u.%01u", value,
floatVal, value & 0x80 ? '-' : ' ',
decVal / 10000000,
decVal % 10000000 / 1000000);
else if (!(decVal % 10000))
- func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
+ func (stream, "%ld\t@ 0x%08x %c%u.%03u", value,
floatVal, value & 0x80 ? '-' : ' ',
decVal / 10000000,
decVal % 10000000 / 10000);
else
- func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
+ func (stream, "%ld\t@ 0x%08x %c%u.%07u", value,
floatVal, value & 0x80 ? '-' : ' ',
decVal / 10000000, decVal % 10000000);
break;
@@ -8765,7 +8765,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
+ func (stream, "\t@ 0x%lx", (value_in_comment & 0xffffffffUL));
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
@@ -8840,7 +8840,7 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
offset = pc + 8;
}
- func (stream, "\t; ");
+ func (stream, "\t@ ");
info->print_address_func (offset, info);
offset = 0;
}
@@ -9381,11 +9381,11 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
switch (size)
{
case 8:
- func (stream, "#%ld\t; 0x%.2lx", value, value);
+ func (stream, "#%ld\t@ 0x%.2lx", value, value);
break;
case 16:
- func (stream, "#%ld\t; 0x%.4lx", value, value);
+ func (stream, "#%ld\t@ 0x%.4lx", value, value);
break;
case 32:
@@ -9405,11 +9405,11 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
(& floatformat_ieee_single_little, valbytes,
& fvalue);
- func (stream, "#%.7g\t; 0x%.8lx", fvalue,
+ func (stream, "#%.7g\t@ 0x%.8lx", fvalue,
value);
}
else
- func (stream, "#%ld\t; 0x%.8lx",
+ func (stream, "#%ld\t@ 0x%.8lx",
(long) (((value & 0x80000000L) != 0)
? value | ~0xffffffffL : value),
value);
@@ -9530,7 +9530,7 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, "\t@ 0x%lx", value_in_comment);
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
@@ -9894,7 +9894,7 @@ print_insn_mve (struct disassemble_info *info, long given)
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, "\t@ 0x%lx", value_in_comment);
if (is_unpredictable)
print_mve_unpredictable (info, unpredictable_cond);
@@ -10059,10 +10059,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
{
/* Elide positive zero offset. */
if (offset || NEGATIVE_BIT_SET)
- func (stream, "[pc, #%s%d]\t; ",
+ func (stream, "[pc, #%s%d]\t@ ",
NEGATIVE_BIT_SET ? "-" : "", (int) offset);
else
- func (stream, "[pc]\t; ");
+ func (stream, "[pc]\t@ ");
if (NEGATIVE_BIT_SET)
offset = -offset;
info->print_address_func (offset + pc + 8, info);
@@ -10421,9 +10421,9 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
/* Some SWI instructions have special
meanings. */
if ((given & 0x0fffffff) == 0x0FF00000)
- func (stream, "\t; IMB");
+ func (stream, "\t@ IMB");
else if ((given & 0x0fffffff) == 0x0FF00001)
- func (stream, "\t; IMBRange");
+ func (stream, "\t@ IMBRange");
break;
case 'X':
func (stream, "%01lx", value & 0xf);
@@ -10512,7 +10512,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
+ func (stream, "\t@ 0x%lx", (value_in_comment & 0xffffffffUL));
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
@@ -10581,12 +10581,12 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
case 'x':
if (ifthen_next_state)
- func (stream, "\t; unpredictable branch in IT block\n");
+ func (stream, "\t@ unpredictable branch in IT block\n");
break;
case 'X':
if (ifthen_state)
- func (stream, "\t; unpredictable <IT:%s>",
+ func (stream, "\t@ unpredictable <IT:%s>",
arm_conditional[IFTHEN_COND]);
break;
@@ -10798,7 +10798,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, "\t@ 0x%lx", value_in_comment);
return;
}
@@ -10897,12 +10897,12 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
case 'x':
if (ifthen_next_state)
- func (stream, "\t; unpredictable branch in IT block\n");
+ func (stream, "\t@ unpredictable branch in IT block\n");
break;
case 'X':
if (ifthen_state)
- func (stream, "\t; unpredictable <IT:%s>",
+ func (stream, "\t@ unpredictable <IT:%s>",
arm_conditional[IFTHEN_COND]);
break;
@@ -11103,7 +11103,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
if (Rn == 15)
{
- func (stream, "\t; ");
+ func (stream, "\t@ ");
info->print_address_func (((pc + 4) & ~3) + offset, info);
}
}
@@ -11539,7 +11539,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
if ((given & (1 << 23)) == 0)
offset = - offset;
- func (stream, "\t; ");
+ func (stream, "\t@ ");
info->print_address_func ((pc & ~3) + 4 + offset, info);
}
break;
@@ -11550,7 +11550,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, "\t@ 0x%lx", value_in_comment);
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
--
2.25.4
next prev parent reply other threads:[~2022-10-03 16:37 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-16 13:21 [PATCH 0/2] Disassembler styling for ARM Andrew Burgess
2022-09-16 13:21 ` [PATCH 1/2] opcodes/arm: add missing ';' characters Andrew Burgess
2022-09-20 15:13 ` Richard Earnshaw
2022-09-22 9:08 ` Andrew Burgess
2022-09-22 12:39 ` Richard Earnshaw
2022-09-22 18:20 ` Andrew Burgess
2022-09-16 13:21 ` [PATCH 2/2] opcodes/arm: add disassembler styling for arm Andrew Burgess
2022-10-02 10:47 ` [PATCHv2 0/2] Disassembler styling for ARM Andrew Burgess
2022-10-02 10:47 ` Andrew Burgess [this message]
2022-10-03 16:37 ` [PATCHv2 1/2] opcodes/arm: use '@' consistently for the comment character Andrew Burgess
2022-10-02 10:47 ` [PATCHv2 2/2] opcodes/arm: add disassembler styling for arm Andrew Burgess
2022-10-12 12:42 ` Andrew Burgess
2022-10-19 10:10 ` [PATCHv2 0/2] Disassembler styling for ARM Andrew Burgess
2022-10-31 14:59 ` Nick Clifton
2022-11-01 9:37 ` Andrew Burgess
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