From: Haochen Jiang <haochen.jiang@intel.com>
To: binutils@sourceware.org
Cc: jbeulich@suse.com, hjl.tools@gmail.com,
wwwhhhyyy <hongyu.wang@intel.com>
Subject: [PATCH 01/10] Support Intel AVX-IFMA
Date: Wed, 19 Oct 2022 23:15:25 +0800 [thread overview]
Message-ID: <20221019151534.45521-2-haochen.jiang@intel.com> (raw)
In-Reply-To: <20221019151534.45521-1-haochen.jiang@intel.com>
From: wwwhhhyyy <hongyu.wang@intel.com>
x86: Support Intel AVX-IFMA
Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is
cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions
are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX
encoding for Intel IFMA instructions.
gas/
* NEWS: Support Intel AVX-IFMA.
* config/tc-i386.c (cpu_arch): Add avx_ifma.
* doc/c-i386.texi: Document .avx_ifma and how to
encode Intel IFMA instructions with VEX prefix.
* testsuite/gas/i386/avx-ifma.d: New file.
* testsuite/gas/i386/avx-ifma-intel.d: Likewise.
* testsuite/gas/i386/avx-ifma.s: Likewise.
* testsuite/gas/i386/x86-64-avx-ifma.d: Likewise.
* testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx-ifma.s: Likewise.
* testsuite/gas/i386/i386.exp: Run AVX IFMA tests.
opcodes/
* i386-dis.c (PREFIX_VEX_0F38B4): New.
(PREFIX_VEX_0F38B5): Likewise.
(VEX_W_0F38B4_P_2): Likewise.
(VEX_W_0F38B5_P_2): Likewise.
(prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5.
(vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2.
* i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in
CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and
CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS.
(cpu_flags): Add CpuAVX_IFMA.
* i386-opc.h (CpuAVX_IFMA): New.
(i386_cpu_flags): Add cpuavx_ifma.
* i386-opc.tbl: Add Intel AVX IFMA instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 6 +-
gas/testsuite/gas/i386/avx-ifma-intel.d | 30 +
gas/testsuite/gas/i386/avx-ifma-inval.l | 2 +
gas/testsuite/gas/i386/avx-ifma-inval.s | 6 +
gas/testsuite/gas/i386/avx-ifma.d | 30 +
gas/testsuite/gas/i386/avx-ifma.s | 21 +
gas/testsuite/gas/i386/i386.exp | 6 +
gas/testsuite/gas/i386/noavx512-1.l | 24 +-
.../gas/i386/x86-64-avx-ifma-intel.d | 34 +
.../gas/i386/x86-64-avx-ifma-inval.l | 3 +
.../gas/i386/x86-64-avx-ifma-inval.s | 7 +
gas/testsuite/gas/i386/x86-64-avx-ifma.d | 34 +
gas/testsuite/gas/i386/x86-64-avx-ifma.s | 23 +
opcodes/i386-dis.c | 16 +-
opcodes/i386-gen.c | 7 +-
opcodes/i386-init.h | 522 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 7 +
opcodes/i386-tbl.h | 7808 +++++++++--------
21 files changed, 4436 insertions(+), 4156 deletions(-)
create mode 100644 gas/testsuite/gas/i386/avx-ifma-intel.d
create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.l
create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.s
create mode 100644 gas/testsuite/gas/i386/avx-ifma.d
create mode 100644 gas/testsuite/gas/i386/avx-ifma.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.s
diff --git a/gas/NEWS b/gas/NEWS
index 16cb347e77..7cf65728ba 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel AVX-IFMA instructions.
+
* gas now supports --compress-debug-sections=zstd to compress
debug sections with zstd.
* Add --enable-default-compressed-debug-sections-algorithm={zlib,zstd}
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 01f84cb9a3..2fe7674884 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1094,6 +1094,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (uintr, UINTR, ANY_UINTR, false),
SUBARCH (hreset, HRESET, ANY_HRESET, false),
SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false),
+ SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index d4f5018b6c..2d0735c169 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -194,6 +194,7 @@ accept various extension mnemonics. For example,
@code{avx512_bf16},
@code{avx_vnni},
@code{avx512_fp16},
+@code{avx_ifma},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -826,9 +827,9 @@ prefix which generates REX prefix unconditionally.
@samp{@{nooptimize@}} -- disable instruction size optimization.
@end itemize
-Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix
+Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix
by default. The pseudo @samp{@{vex@}} prefix can be used to encode
-mnemonics of Intel VNNI instructions with the VEX prefix.
+mnemonics of Intel VNNI/IFMA instructions with the VEX prefix.
@cindex conversion instructions, i386
@cindex i386 conversion instructions
@@ -1486,6 +1487,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
+@item @samp{.avx_ifma}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/avx-ifma-intel.d b/gas/testsuite/gas/i386/avx-ifma-intel.d
new file mode 100644
index 0000000000..3b6bcce2a1
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma-intel.d
@@ -0,0 +1,30 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX IFMA insns (Intel disassembly)
+#source: avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.l b/gas/testsuite/gas/i386/avx-ifma-inval.l
new file mode 100644
index 0000000000..f706972175
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma-inval.l
@@ -0,0 +1,2 @@
+.* Assembler messages:
+.*:6: Error: unsupported instruction `vpmadd52huq'
diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.s b/gas/testsuite/gas/i386/avx-ifma-inval.s
new file mode 100644
index 0000000000..0697ab2215
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma-inval.s
@@ -0,0 +1,6 @@
+# Check illegal in AVXIFMA instructions
+
+ .text
+ .arch .noavx512ifma
+_start:
+ vpmadd52huq %xmm2,%xmm4,%xmm2
diff --git a/gas/testsuite/gas/i386/avx-ifma.d b/gas/testsuite/gas/i386/avx-ifma.d
new file mode 100644
index 0000000000..50c24947db
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma.d
@@ -0,0 +1,30 @@
+#as:
+#objdump: -dw
+#name: i386 AVX IFMA insns
+#source: avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx-ifma.s b/gas/testsuite/gas/i386/avx-ifma.s
new file mode 100644
index 0000000000..983b48ebcb
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma.s
@@ -0,0 +1,21 @@
+ .allow_index_reg
+
+.macro test_insn mnemonic
+ \mnemonic %xmm2, %xmm4, %xmm2
+ {evex} \mnemonic %xmm2, %xmm4, %xmm2
+ {vex} \mnemonic %xmm2, %xmm4, %xmm2
+ {vex} \mnemonic (%ecx), %xmm4, %xmm2
+ \mnemonic %ymm2, %ymm4, %ymm2
+ {evex} \mnemonic %ymm2, %ymm4, %ymm2
+ {vex} \mnemonic %ymm2, %ymm4, %ymm2
+ {vex} \mnemonic (%ecx), %ymm4, %ymm2
+.endm
+
+ .text
+_start:
+ test_insn vpmadd52huq
+ test_insn vpmadd52luq
+
+ .arch .avx_ifma
+ vpmadd52huq %xmm2, %xmm4, %xmm2
+ vpmadd52huq %ymm2, %ymm4, %ymm2
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 0ad2b6a818..3a46807e4f 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -478,6 +478,9 @@ if [gas_32_check] then {
run_list_test "avx512_bf16_vl-inval"
run_dump_test "avx-vnni"
run_list_test "avx-vnni-inval"
+ run_dump_test "avx-ifma"
+ run_dump_test "avx-ifma-intel"
+ run_list_test "avx-ifma-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1145,6 +1148,9 @@ if [gas_64_check] then {
run_list_test "x86-64-avx512_bf16_vl-inval"
run_dump_test "x86-64-avx-vnni"
run_list_test "x86-64-avx-vnni-inval"
+ run_dump_test "x86-64-avx-ifma"
+ run_dump_test "x86-64-avx-ifma-intel"
+ run_list_test "x86-64-avx-ifma-inval"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/noavx512-1.l b/gas/testsuite/gas/i386/noavx512-1.l
index 15a6fc689b..75c28afafb 100644
--- a/gas/testsuite/gas/i386/noavx512-1.l
+++ b/gas/testsuite/gas/i386/noavx512-1.l
@@ -37,9 +37,9 @@
.*:120: Error: .*not supported.*
.*:121: Error: .*not supported.*
.*:122: Error: .*not supported.*
-.*:126: Error: .*not supported.*
-.*:127: Error: .*not supported.*
-.*:128: Error: .*not supported.*
+.*:126: Error: .*unsupported instruction.*
+.*:127: Error: .*unsupported instruction.*
+.*:128: Error: .*unsupported instruction.*
.*:135: Error: .*operand size mismatch.*
.*:136: Error: .*unsupported masking.*
.*:137: Error: .*unsupported masking.*
@@ -50,9 +50,9 @@
.*:142: Error: .*not supported.*
.*:143: Error: .*not supported.*
.*:144: Error: .*not supported.*
-.*:148: Error: .*not supported.*
-.*:149: Error: .*not supported.*
-.*:150: Error: .*not supported.*
+.*:148: Error: .*unsupported instruction.*
+.*:149: Error: .*unsupported instruction.*
+.*:150: Error: .*unsupported instruction.*
.*:151: Error: .*not supported.*
.*:157: Error: .*operand size mismatch.*
.*:158: Error: .*unsupported masking.*
@@ -64,9 +64,9 @@
.*:164: Error: .*not supported.*
.*:165: Error: .*not supported.*
.*:166: Error: .*not supported.*
-.*:170: Error: .*not supported.*
-.*:171: Error: .*not supported.*
-.*:172: Error: .*not supported.*
+.*:170: Error: .*unsupported instruction.*
+.*:171: Error: .*unsupported instruction.*
+.*:172: Error: .*unsupported instruction.*
.*:173: Error: .*not supported.*
.*:174: Error: .*not supported.*
.*:175: Error: .*not supported.*
@@ -84,9 +84,9 @@
.*:189: Error: .*bad register name.*
.*:190: Error: .*unknown vector operation.*
.*:191: Error: .*unknown vector operation.*
-.*:192: Error: .*not supported.*
-.*:193: Error: .*not supported.*
-.*:194: Error: .*not supported.*
+.*:192: Error: .*bad register name.*
+.*:193: Error: .*unknown vector operation.*
+.*:194: Error: .*unknown vector operation.*
.*:195: Error: .*not supported.*
.*:196: Error: .*not supported.*
.*:197: Error: .*not supported.*
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d
new file mode 100644
index 0000000000..0b3b053e5d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d
@@ -0,0 +1,34 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86-64 AVX IFMA insns (Intel disassembly)
+#source: x86-64-avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq xmm2,xmm4,xmm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq ymm2,ymm4,ymm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq xmm2,xmm4,xmm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq ymm2,ymm4,ymm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l
new file mode 100644
index 0000000000..57a7f16807
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l
@@ -0,0 +1,3 @@
+.* Assembler messages:
+.*:6: Error: unsupported instruction `vpmadd52huq'
+.*:7: Error: unsupported instruction `vpmadd52huq'
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s
new file mode 100644
index 0000000000..0e37bf2361
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s
@@ -0,0 +1,7 @@
+# Check illegal in AVXIFMA instructions
+
+ .text
+ .arch .noavx512ifma
+_start:
+ vpmadd52huq %xmm2, %xmm4, %xmm2
+ vpmadd52huq %xmm22, %xmm4, %xmm2
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.d b/gas/testsuite/gas/i386/x86-64-avx-ifma.d
new file mode 100644
index 0000000000..b1670b68b6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.d
@@ -0,0 +1,34 @@
+#as:
+#objdump: -dw
+#name: x86-64 AVX IFMA insns
+#source: x86-64-avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq %xmm22,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq %ymm22,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq %xmm22,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq %ymm22,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.s b/gas/testsuite/gas/i386/x86-64-avx-ifma.s
new file mode 100644
index 0000000000..bfc524a103
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.s
@@ -0,0 +1,23 @@
+ .allow_index_reg
+
+.macro test_insn mnemonic
+ \mnemonic %xmm12, %xmm4, %xmm2
+ {evex} \mnemonic %xmm12, %xmm4, %xmm2
+ {vex} \mnemonic %xmm12, %xmm4, %xmm2
+ {vex} \mnemonic (%rcx), %xmm4, %xmm2
+ \mnemonic %xmm22, %xmm4, %xmm2
+ \mnemonic %ymm12, %ymm4, %ymm2
+ {evex} \mnemonic %ymm12, %ymm4, %ymm2
+ {vex} \mnemonic %ymm12, %ymm4, %ymm2
+ {vex} \mnemonic (%rcx), %ymm4, %ymm2
+ \mnemonic %ymm22, %ymm4, %ymm2
+.endm
+
+ .text
+_start:
+ test_insn vpmadd52huq
+ test_insn vpmadd52luq
+
+ .arch .avx_ifma
+ vpmadd52huq %xmm12, %xmm4, %xmm2
+ vpmadd52huq %ymm12, %ymm4, %ymm2
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 83290700c6..e736acce80 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1526,6 +1526,8 @@ enum
VEX_W_0F385E_X86_64_P_3,
VEX_W_0F3878,
VEX_W_0F3879,
+ VEX_W_0F38B4,
+ VEX_W_0F38B5,
VEX_W_0F38CF,
VEX_W_0F3A00_L_1,
VEX_W_0F3A01_L_1,
@@ -6293,8 +6295,8 @@ static const struct dis386 vex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F38B4) },
+ { VEX_W_TABLE (VEX_W_0F38B5) },
{ "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
{ "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
/* b8 */
@@ -7599,6 +7601,16 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3879 */
{ "vpbroadcastw", { XM, EXw }, PREFIX_DATA },
},
+ {
+ /* VEX_W_0F38B4 */
+ { Bad_Opcode },
+ { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
+ },
+ {
+ /* VEX_W_0F38B5 */
+ { Bad_Opcode },
+ { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
+ },
{
/* VEX_W_0F38CF */
{ "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index eb3bd85079..060bb304cd 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -245,6 +245,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX512F_FLAGS|CpuAVX512_BF16" },
{ "CPU_AVX512_FP16_FLAGS",
"CPU_AVX512BW_FLAGS|CpuAVX512_FP16" },
+ { "CPU_AVX_IFMA_FLAGS",
+ "CPU_AVX2_FLAGS|CpuAVX_IFMA" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -370,7 +372,7 @@ static initializer cpu_flag_init[] =
{ "CPU_ANY_AVX_FLAGS",
"CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" },
{ "CPU_ANY_AVX2_FLAGS",
- "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI" },
+ "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA" },
{ "CPU_ANY_AVX512F_FLAGS",
"CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" },
{ "CPU_ANY_AVX512CD_FLAGS",
@@ -439,6 +441,8 @@ static initializer cpu_flag_init[] =
"CpuHRESET" },
{ "CPU_ANY_AVX512_FP16_FLAGS",
"CpuAVX512_FP16" },
+ { "CPU_ANY_AVX_IFMA_FLAGS",
+ "CpuAVX_IFMA" },
};
static initializer operand_type_init[] =
@@ -640,6 +644,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuTDX),
BITFIELD (CpuAVX_VNNI),
BITFIELD (CpuAVX512_FP16),
+ BITFIELD (CpuAVX_IFMA),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index c033aeb8e0..8ff66d42cc 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -209,6 +209,8 @@ enum
CpuAVX_VNNI,
/* Intel AVX-512 FP16 Instructions support required. */
CpuAVX512_FP16,
+ /* Intel AVX IFMA Instructions support required. */
+ CpuAVX_IFMA,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -388,6 +390,7 @@ typedef union i386_cpu_flags
unsigned int cputdx:1;
unsigned int cpuavx_vnni:1;
unsigned int cpuavx512_fp16:1;
+ unsigned int cpuavx_ifma:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index fbd48c203a..8ce92ae390 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3263,3 +3263,10 @@ vrsqrtph, 0x664e, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast
vrsqrtsh, 0x664f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
// FP16 (HFNI) instructions end.
+
+// AVX_IFMA instructions.
+
+vpmadd52huq, 0x66B5, None, CpuAVX_IFMA, Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+
+// AVX_IFMA instructions end.
--
2.18.1
next prev parent reply other threads:[~2022-10-19 15:17 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` Haochen Jiang [this message]
2022-10-19 15:15 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-25 6:34 ` Jan Beulich
2022-10-19 15:15 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-19 15:15 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-19 15:15 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-19 15:15 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-19 15:15 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-19 15:15 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-19 15:15 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-19 15:15 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-25 7:11 ` Jan Beulich
2022-10-25 7:49 ` Cui, Lili
2022-10-25 8:31 ` Jan Beulich
-- strict thread matches above, loose matches on Subject: below --
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:55 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14 9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14 9:12 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14 9:52 ` Jan Beulich
2022-10-14 18:10 ` H.J. Lu
2022-10-16 6:39 ` Jan Beulich
2022-10-17 22:23 ` H.J. Lu
2022-10-18 5:33 ` Jan Beulich
2022-10-18 21:28 ` H.J. Lu
2022-10-19 6:01 ` Jan Beulich
2022-10-19 21:27 ` H.J. Lu
2022-10-20 6:15 ` Jan Beulich
2022-10-24 2:07 ` Jiang, Haochen
2022-10-24 5:53 ` Jiang, Haochen
2022-10-24 19:09 ` H.J. Lu
2022-10-25 6:29 ` Jan Beulich
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