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From: "Cui, Lili" <lili.cui@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>,
	"Jiang, Haochen" <haochen.jiang@intel.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
	"binutils@sourceware.org" <binutils@sourceware.org>
Subject: RE: [PATCH 10/10] Support Intel PREFETCHI
Date: Tue, 25 Oct 2022 07:49:01 +0000	[thread overview]
Message-ID: <SJ0PR11MB56002DCDFC1CF29945EEAFE89E319@SJ0PR11MB5600.namprd11.prod.outlook.com> (raw)
In-Reply-To: <0559bce1-34ea-bdbf-9711-f94ae5f6490d@suse.com>

> On 19.10.2022 17:15, Haochen Jiang wrote:
> > --- a/gas/config/tc-i386.c
> > +++ b/gas/config/tc-i386.c
> > @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
> >    SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
> >    SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
> >    SUBARCH (msrlist, MSRLIST, MSRLIST, false),
> > +  SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
> >  };
> >
> >  #undef SUBARCH
> > @@ -4522,7 +4523,8 @@ load_insn_p (void)
> >      {
> >        /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
> >  	 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
> > -	 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote.  */
> > +	 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
> > +	 prefetchit1.  */
> >        if (i.tm.opcode_modifier.anysize)
> >  	return 0;
> >
> 
> There's still no change in this file making sure that the new insns are _only_
> accepted with RIP-relative addressing. See my earlier comments.
> 
Hi Jan,
I'll modify the patch based on your previous comments, do you agree with adding a warning instead of an error for illegal input for assembler. Because it doesn't cause hardware errors.

Lili.
> Jan


  reply	other threads:[~2022-10-25  7:49 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-19 15:15 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-25  6:34   ` Jan Beulich
2022-10-19 15:15 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-19 15:15 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-19 15:15 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-19 15:15 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-19 15:15 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-19 15:15 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-19 15:15 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-19 15:15 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-25  7:11   ` Jan Beulich
2022-10-25  7:49     ` Cui, Lili [this message]
2022-10-25  8:31       ` Jan Beulich
  -- strict thread matches above, loose matches on Subject: below --
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:56 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-14  9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14  9:12 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-17  8:15   ` Jan Beulich
2022-10-25 13:03     ` Cui, Lili
2022-10-25 15:41       ` Jan Beulich
2022-10-25 15:52       ` Jan Beulich
2022-10-25 17:01         ` H.J. Lu
2022-10-26 13:42           ` Cui, Lili
2022-10-26 13:53             ` Jan Beulich
2022-10-27  6:04               ` Cui, Lili
2022-10-27  6:45                 ` Jan Beulich
2022-10-27  7:01                   ` Cui, Lili
2022-10-27  7:15                     ` Jan Beulich
2022-10-27  7:43                       ` Cui, Lili
2022-10-28  9:03                       ` Cui, Lili
2022-10-28 15:54                     ` H.J. Lu
2022-10-31 13:23                       ` Cui, Lili
2022-10-31 14:45                     ` Mike Frysinger
2022-10-31 16:25                       ` H.J. Lu

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