From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
"Wang, Hongyu" <hongyu.wang@intel.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: RE: [PATCH 01/10] Support Intel AVX-IFMA
Date: Mon, 24 Oct 2022 05:53:36 +0000 [thread overview]
Message-ID: <SA1PR11MB5946DDA650C165540BACD061EC2E9@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <863655db-f202-477f-c638-00773c25886c@suse.com>
[-- Attachment #1: Type: text/plain, Size: 5582 bytes --]
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, October 14, 2022 5:53 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; Wang, Hongyu <hongyu.wang@intel.com>;
> binutils@sourceware.org
> Subject: Re: [PATCH 01/10] Support Intel AVX-IFMA
>
> On 14.10.2022 11:12, Haochen Jiang wrote:
> > From: wwwhhhyyy <hongyu.wang@intel.com>
> >
> > x86: Support Intel AVX-IFMA
> >
> > Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is
> > cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions
> > are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX
> > encoding for Intel IFMA instructions.
>
> I firmly object to the proliferation of this mis-feature. As expressed
> before for AVX-VNNI, as long as the user has disabled AVX512 (or
> respective sub-features thereof), there should be no need to use {vex} in
> the source code. There's also no reason at all to make the disassembler
> print {vex} prefixes - we don't do so for any other insns (apart from
> AVX-VNNI) where an ambiguity exists between their VEX and EVEX encodings
> (when none of the EVEX-specific features is used).
>
> I actually have a patch queued to undo the odd behavior for AVX-VNNI, at
> least on the assembler side (which also drops the PseudoVexPrefix
> attribute).
Has rebased the patch to latest trunk and removed PseudoVexPrefix in table.
Also added some testcases just like how your patch did.
>
> > --- a/opcodes/i386-dis.c
> > +++ b/opcodes/i386-dis.c
> > @@ -1526,6 +1526,8 @@ enum
> > VEX_W_0F385E_X86_64_P_3,
> > VEX_W_0F3878,
> > VEX_W_0F3879,
> > + VEX_W_0F38B4,
> > + VEX_W_0F38B5,
> > VEX_W_0F38CF,
> > VEX_W_0F3A00_L_1,
> > VEX_W_0F3A01_L_1,
> > @@ -6293,8 +6295,8 @@ static const struct dis386 vex_table[][256] = {
> > { Bad_Opcode },
> > { Bad_Opcode },
> > { Bad_Opcode },
> > - { Bad_Opcode },
> > - { Bad_Opcode },
> > + { VEX_W_TABLE (VEX_W_0F38B4) },
> > + { VEX_W_TABLE (VEX_W_0F38B5) },
> > { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
> > { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
> > /* b8 */
> > @@ -7599,6 +7601,16 @@ static const struct dis386 vex_w_table[][2] = {
> > /* VEX_W_0F3879 */
> > { "vpbroadcastw", { XM, EXw }, PREFIX_DATA },
> > },
> > + {
> > + /* VEX_W_0F38B4 */
> > + { Bad_Opcode },
> > + { "%XV vpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
> > + },
> > + {
> > + /* VEX_W_0F38B5 */
> > + { Bad_Opcode },
> > + { "%XV vpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
> > + },
>
> Irrespective of the aspect mentioned at the top I think this is yet
> another case where VEX and EVEX table entries can be shared. This would
> (if the {vex} printing really needs retaining for whatever obscure
> reason) merely require the processing of %XV to do nothing for EVEX-
> encoded insns, plus of course the separating blank would then also need
> to be included in the processing of %XV.
>
> I guess I'll make a patch to fold the AVX-VNNI and AVX512-VNNI entries,
> which you could then re-base on top of.
Folded the table of AVX512IFMA and AVX-IFMA.
>
> > --- a/opcodes/i386-gen.c
> > +++ b/opcodes/i386-gen.c
> > @@ -245,6 +245,8 @@ static initializer cpu_flag_init[] =
> > "CPU_AVX512F_FLAGS|CpuAVX512_BF16" },
> > { "CPU_AVX512_FP16_FLAGS",
> > "CPU_AVX512BW_FLAGS|CpuAVX512_FP16" },
> > + { "CPU_AVX_IFMA_FLAGS",
> > + "CPU_AVX2_FLAGS|CpuAVX_IFMA" },
> > { "CPU_IAMCU_FLAGS",
> > "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
> > { "CPU_ADX_FLAGS",
> > @@ -439,6 +441,8 @@ static initializer cpu_flag_init[] =
> > "CpuHRESET" },
> > { "CPU_ANY_AVX512_FP16_FLAGS",
> > "CpuAVX512_FP16" },
> > + { "CPU_ANY_AVX_IFMA_FLAGS",
> > + "CpuAVX_IFMA" },
>
> If AVX2 is taken as a prereq feature, then CPU_ANY_AVX2_FLAGS also needs
> adjustment, such that disabling of AVX2 also results in disabling of
> AVX-IFMA. (The same issue actually exists for AVX-VNNI afaics.)
>
Added AVX-IFMA to CPU_ANY_AVX2_FLAGS.
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3263,3 +3263,10 @@ vrsqrtph, 0x664e, None, CpuAVX512_FP16,
> Modrm|Masking=3|EVexMap6|VexW0|Broadcast
> > vrsqrtsh, 0x664f, None, CpuAVX512_FP16,
> Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|N
> o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,
> { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> >
> > // FP16 (HFNI) instructions end.
> > +
> > +// AVX_IFMA instructions.
>
> Nit: Perhaps better use AVX-IFMA here, but I see we're having many examples
> of the (needless) use of underscores like this.
>
> > +vpmadd52huq, 0x66B5, None, CpuAVX_IFMA,
> Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV=1|VexW1|CheckRegSize|N
> o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,
> { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM,
> RegXMM|RegYMM }
> > +vpmadd52luq, 0x66B4, None, CpuAVX_IFMA,
> Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV=1|VexW1|CheckRegSize|N
> o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,
> { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM,
> RegXMM|RegYMM }
>
> Please use plain VexVVVV (without =1) - we want to have as little clutter as
> possible on these usually already overlong lines.
Changed to VexVVVV.
Thx for your review and see if there is still something need to be changed.
Haochen
>
> Jan
[-- Attachment #2: 0001-Support-Intel-AVX-IFMA.patch --]
[-- Type: application/octet-stream, Size: 26325 bytes --]
From a064594d9882c9d2c8b5fbd86ecf93a5b6602484 Mon Sep 17 00:00:00 2001
From: Hongyu Wang <hongyu.wang@intel.com>
Date: Mon, 12 Oct 2020 12:38:34 +0800
Subject: [PATCH 1/8] Support Intel AVX-IFMA
x86: Support Intel AVX-IFMA
Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is
cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions
are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX
encoding for Intel IFMA instructions.
gas/
* NEWS: Support Intel AVX-IFMA.
* config/tc-i386.c (cpu_arch): Add avx_ifma.
* doc/c-i386.texi: Document .avx_ifma.
* testsuite/gas/i386/avx-ifma.d: New file.
* testsuite/gas/i386/avx-ifma-intel.d: Likewise.
* testsuite/gas/i386/avx-ifma.s: Likewise.
* testsuite/gas/i386/x86-64-avx-ifma.d: Likewise.
* testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx-ifma.s: Likewise.
* testsuite/gas/i386/i386.exp: Run AVX IFMA tests.
opcodes/
* i386-dis.c (PREFIX_VEX_0F38B4): New.
(PREFIX_VEX_0F38B5): Likewise.
(VEX_W_0F38B4_P_2): Likewise.
(VEX_W_0F38B5_P_2): Likewise.
(prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5.
(vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2.
* i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA.
* i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in
CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and
CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS.
(cpu_flags): Add CpuAVX_IFMA.
* i386-opc.h (CpuAVX_IFMA): New.
(i386_cpu_flags): Add cpuavx_ifma.
* i386-opc.tbl: Add Intel AVX IFMA instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 6 +-
gas/testsuite/gas/i386/avx-ifma-intel.d | 37 +
gas/testsuite/gas/i386/avx-ifma-inval.l | 3 +
gas/testsuite/gas/i386/avx-ifma-inval.s | 7 +
gas/testsuite/gas/i386/avx-ifma.d | 37 +
gas/testsuite/gas/i386/avx-ifma.s | 40 +
gas/testsuite/gas/i386/i386.exp | 6 +
gas/testsuite/gas/i386/noavx512-1.l | 24 +-
.../gas/i386/x86-64-avx-ifma-intel.d | 34 +
.../gas/i386/x86-64-avx-ifma-inval.l | 4 +
.../gas/i386/x86-64-avx-ifma-inval.s | 8 +
gas/testsuite/gas/i386/x86-64-avx-ifma.d | 34 +
gas/testsuite/gas/i386/x86-64-avx-ifma.s | 23 +
opcodes/i386-dis-evex.h | 4 +-
opcodes/i386-dis.c | 16 +-
opcodes/i386-gen.c | 7 +-
opcodes/i386-init.h | 522 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 7 +
opcodes/i386-tbl.h | 7808 +++++++++--------
22 files changed, 4475 insertions(+), 4158 deletions(-)
create mode 100644 gas/testsuite/gas/i386/avx-ifma-intel.d
create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.l
create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.s
create mode 100644 gas/testsuite/gas/i386/avx-ifma.d
create mode 100644 gas/testsuite/gas/i386/avx-ifma.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.s
diff --git a/gas/NEWS b/gas/NEWS
index 16cb347e77..7cf65728ba 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel AVX-IFMA instructions.
+
* gas now supports --compress-debug-sections=zstd to compress
debug sections with zstd.
* Add --enable-default-compressed-debug-sections-algorithm={zlib,zstd}
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 02905c1702..b9d67a3b90 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1094,6 +1094,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (uintr, UINTR, ANY_UINTR, false),
SUBARCH (hreset, HRESET, ANY_HRESET, false),
SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false),
+ SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index d4f5018b6c..2d0735c169 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -194,6 +194,7 @@ accept various extension mnemonics. For example,
@code{avx512_bf16},
@code{avx_vnni},
@code{avx512_fp16},
+@code{avx_ifma},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -826,9 +827,9 @@ prefix which generates REX prefix unconditionally.
@samp{@{nooptimize@}} -- disable instruction size optimization.
@end itemize
-Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix
+Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix
by default. The pseudo @samp{@{vex@}} prefix can be used to encode
-mnemonics of Intel VNNI instructions with the VEX prefix.
+mnemonics of Intel VNNI/IFMA instructions with the VEX prefix.
@cindex conversion instructions, i386
@cindex i386 conversion instructions
@@ -1486,6 +1487,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
+@item @samp{.avx_ifma}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/avx-ifma-intel.d b/gas/testsuite/gas/i386/avx-ifma-intel.d
new file mode 100644
index 0000000000..b56ba847bf
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma-intel.d
@@ -0,0 +1,37 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX IFMA insns (Intel disassembly)
+#source: avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 b5 c0[ ]*vpmadd52huq zmm0,zmm0,zmm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.l b/gas/testsuite/gas/i386/avx-ifma-inval.l
new file mode 100644
index 0000000000..5294c2ca73
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma-inval.l
@@ -0,0 +1,3 @@
+.* Assembler messages:
+.*:6: Error: unsupported .* `vpmadd52huq'
+.*:7: Error: operand .* `vpmadd52huq'
diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.s b/gas/testsuite/gas/i386/avx-ifma-inval.s
new file mode 100644
index 0000000000..4b763b6e45
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma-inval.s
@@ -0,0 +1,7 @@
+# Check illegal in AVXIFMA instructions
+
+ .text
+ .arch .noavx512ifma
+_start:
+ vpmadd52huq %xmm2, %xmm4, %xmm2{%k6}
+ vpmadd52huq %zmm2, %zmm4, %zmm2
diff --git a/gas/testsuite/gas/i386/avx-ifma.d b/gas/testsuite/gas/i386/avx-ifma.d
new file mode 100644
index 0000000000..c84b4caad8
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma.d
@@ -0,0 +1,37 @@
+#as:
+#objdump: -dw
+#name: i386 AVX IFMA insns
+#source: avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 b5 c0[ ]*vpmadd52huq %zmm0,%zmm0,%zmm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx-ifma.s b/gas/testsuite/gas/i386/avx-ifma.s
new file mode 100644
index 0000000000..81046966d7
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma.s
@@ -0,0 +1,40 @@
+ .allow_index_reg
+
+.macro test_insn mnemonic
+ \mnemonic %xmm2, %xmm4, %xmm2
+ {evex} \mnemonic %xmm2, %xmm4, %xmm2
+ {vex} \mnemonic %xmm2, %xmm4, %xmm2
+ {vex} \mnemonic (%ecx), %xmm4, %xmm2
+ \mnemonic %ymm2, %ymm4, %ymm2
+ {evex} \mnemonic %ymm2, %ymm4, %ymm2
+ {vex} \mnemonic %ymm2, %ymm4, %ymm2
+ {vex} \mnemonic (%ecx), %ymm4, %ymm2
+.endm
+
+ .text
+_start:
+ test_insn vpmadd52huq
+ test_insn vpmadd52luq
+
+ .arch .noavx512vl
+
+ vpmadd52huq %zmm0, %zmm0, %zmm0
+ vpmadd52huq %ymm0, %ymm0, %ymm0
+ vpmadd52huq %xmm0, %xmm0, %xmm0
+
+ .arch default
+ .arch .noavx512ifma
+
+ vpmadd52huq %ymm0, %ymm0, %ymm0
+ vpmadd52huq %xmm0, %xmm0, %xmm0
+
+ .arch default
+ .arch .noavx512f
+
+ vpmadd52huq %ymm0, %ymm0, %ymm0
+ vpmadd52huq %xmm0, %xmm0, %xmm0
+
+ .arch default
+ .arch .avx_ifma
+ vpmadd52huq %xmm2, %xmm4, %xmm2
+ vpmadd52huq %ymm2, %ymm4, %ymm2
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 0ad2b6a818..3a46807e4f 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -478,6 +478,9 @@ if [gas_32_check] then {
run_list_test "avx512_bf16_vl-inval"
run_dump_test "avx-vnni"
run_list_test "avx-vnni-inval"
+ run_dump_test "avx-ifma"
+ run_dump_test "avx-ifma-intel"
+ run_list_test "avx-ifma-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1145,6 +1148,9 @@ if [gas_64_check] then {
run_list_test "x86-64-avx512_bf16_vl-inval"
run_dump_test "x86-64-avx-vnni"
run_list_test "x86-64-avx-vnni-inval"
+ run_dump_test "x86-64-avx-ifma"
+ run_dump_test "x86-64-avx-ifma-intel"
+ run_list_test "x86-64-avx-ifma-inval"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/noavx512-1.l b/gas/testsuite/gas/i386/noavx512-1.l
index 15a6fc689b..a289b23619 100644
--- a/gas/testsuite/gas/i386/noavx512-1.l
+++ b/gas/testsuite/gas/i386/noavx512-1.l
@@ -37,9 +37,9 @@
.*:120: Error: .*not supported.*
.*:121: Error: .*not supported.*
.*:122: Error: .*not supported.*
-.*:126: Error: .*not supported.*
-.*:127: Error: .*not supported.*
-.*:128: Error: .*not supported.*
+.*:126: Error: .*operand .*
+.*:127: Error: .*unsupported .*
+.*:128: Error: .*unsupported .*
.*:135: Error: .*operand size mismatch.*
.*:136: Error: .*unsupported masking.*
.*:137: Error: .*unsupported masking.*
@@ -50,9 +50,9 @@
.*:142: Error: .*not supported.*
.*:143: Error: .*not supported.*
.*:144: Error: .*not supported.*
-.*:148: Error: .*not supported.*
-.*:149: Error: .*not supported.*
-.*:150: Error: .*not supported.*
+.*:148: Error: .*operand .*
+.*:149: Error: .*unsupported .*
+.*:150: Error: .*unsupported .*
.*:151: Error: .*not supported.*
.*:157: Error: .*operand size mismatch.*
.*:158: Error: .*unsupported masking.*
@@ -64,9 +64,9 @@
.*:164: Error: .*not supported.*
.*:165: Error: .*not supported.*
.*:166: Error: .*not supported.*
-.*:170: Error: .*not supported.*
-.*:171: Error: .*not supported.*
-.*:172: Error: .*not supported.*
+.*:170: Error: .*operand .*
+.*:171: Error: .*unsupported .*
+.*:172: Error: .*unsupported .*
.*:173: Error: .*not supported.*
.*:174: Error: .*not supported.*
.*:175: Error: .*not supported.*
@@ -84,9 +84,9 @@
.*:189: Error: .*bad register name.*
.*:190: Error: .*unknown vector operation.*
.*:191: Error: .*unknown vector operation.*
-.*:192: Error: .*not supported.*
-.*:193: Error: .*not supported.*
-.*:194: Error: .*not supported.*
+.*:192: Error: .*bad register name.*
+.*:193: Error: .*unknown vector operation.*
+.*:194: Error: .*unknown vector operation.*
.*:195: Error: .*not supported.*
.*:196: Error: .*not supported.*
.*:197: Error: .*not supported.*
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d
new file mode 100644
index 0000000000..0b3b053e5d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d
@@ -0,0 +1,34 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86-64 AVX IFMA insns (Intel disassembly)
+#source: x86-64-avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq xmm2,xmm4,xmm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq ymm2,ymm4,ymm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq xmm2,xmm4,xmm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq ymm2,ymm4,ymm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l
new file mode 100644
index 0000000000..fad43f6768
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l
@@ -0,0 +1,4 @@
+.* Assembler messages:
+.*:6: Error: unsupported .* `vpmadd52huq'
+.*:7: Error: unsupported .* `vpmadd52huq'
+.*:8: Error: operand .* `vpmadd52huq'
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s
new file mode 100644
index 0000000000..76da0f1a37
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s
@@ -0,0 +1,8 @@
+# Check illegal in AVXIFMA instructions
+
+ .text
+ .arch .noavx512ifma
+_start:
+ vpmadd52huq %xmm2, %xmm4, %xmm2{%k6}
+ vpmadd52huq %xmm22, %xmm4, %xmm2{%k1}
+ vpmadd52huq %zmm2, %zmm4, %zmm2
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.d b/gas/testsuite/gas/i386/x86-64-avx-ifma.d
new file mode 100644
index 0000000000..b1670b68b6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.d
@@ -0,0 +1,34 @@
+#as:
+#objdump: -dw
+#name: x86-64 AVX IFMA insns
+#source: x86-64-avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq %xmm22,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq %ymm22,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq %xmm22,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq %ymm22,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.s b/gas/testsuite/gas/i386/x86-64-avx-ifma.s
new file mode 100644
index 0000000000..bfc524a103
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.s
@@ -0,0 +1,23 @@
+ .allow_index_reg
+
+.macro test_insn mnemonic
+ \mnemonic %xmm12, %xmm4, %xmm2
+ {evex} \mnemonic %xmm12, %xmm4, %xmm2
+ {vex} \mnemonic %xmm12, %xmm4, %xmm2
+ {vex} \mnemonic (%rcx), %xmm4, %xmm2
+ \mnemonic %xmm22, %xmm4, %xmm2
+ \mnemonic %ymm12, %ymm4, %ymm2
+ {evex} \mnemonic %ymm12, %ymm4, %ymm2
+ {vex} \mnemonic %ymm12, %ymm4, %ymm2
+ {vex} \mnemonic (%rcx), %ymm4, %ymm2
+ \mnemonic %ymm22, %ymm4, %ymm2
+.endm
+
+ .text
+_start:
+ test_insn vpmadd52huq
+ test_insn vpmadd52luq
+
+ .arch .avx_ifma
+ vpmadd52huq %xmm12, %xmm4, %xmm2
+ vpmadd52huq %ymm12, %ymm4, %ymm2
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 9353c9c312..92074052a3 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -495,8 +495,8 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
- { "vpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
+ { VEX_W_TABLE (VEX_W_0F38B4) },
+ { VEX_W_TABLE (VEX_W_0F38B5) },
{ "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
/* B8 */
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 83290700c6..e736acce80 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1526,6 +1526,8 @@ enum
VEX_W_0F385E_X86_64_P_3,
VEX_W_0F3878,
VEX_W_0F3879,
+ VEX_W_0F38B4,
+ VEX_W_0F38B5,
VEX_W_0F38CF,
VEX_W_0F3A00_L_1,
VEX_W_0F3A01_L_1,
@@ -6293,8 +6295,8 @@ static const struct dis386 vex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F38B4) },
+ { VEX_W_TABLE (VEX_W_0F38B5) },
{ "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
{ "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
/* b8 */
@@ -7599,6 +7601,16 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3879 */
{ "vpbroadcastw", { XM, EXw }, PREFIX_DATA },
},
+ {
+ /* VEX_W_0F38B4 */
+ { Bad_Opcode },
+ { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
+ },
+ {
+ /* VEX_W_0F38B5 */
+ { Bad_Opcode },
+ { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
+ },
{
/* VEX_W_0F38CF */
{ "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 129a06d6c0..980fdab306 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -245,6 +245,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX512F_FLAGS|CpuAVX512_BF16" },
{ "CPU_AVX512_FP16_FLAGS",
"CPU_AVX512BW_FLAGS|CpuAVX512_FP16" },
+ { "CPU_AVX_IFMA_FLAGS",
+ "CPU_AVX2_FLAGS|CpuAVX_IFMA" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -370,7 +372,7 @@ static initializer cpu_flag_init[] =
{ "CPU_ANY_AVX_FLAGS",
"CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" },
{ "CPU_ANY_AVX2_FLAGS",
- "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI" },
+ "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA" },
{ "CPU_ANY_AVX512F_FLAGS",
"CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" },
{ "CPU_ANY_AVX512CD_FLAGS",
@@ -439,6 +441,8 @@ static initializer cpu_flag_init[] =
"CpuHRESET" },
{ "CPU_ANY_AVX512_FP16_FLAGS",
"CpuAVX512_FP16" },
+ { "CPU_ANY_AVX_IFMA_FLAGS",
+ "CpuAVX_IFMA" },
};
static initializer operand_type_init[] =
@@ -640,6 +644,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuTDX),
BITFIELD (CpuAVX_VNNI),
BITFIELD (CpuAVX512_FP16),
+ BITFIELD (CpuAVX_IFMA),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 11c8a0219f..3aab54a0ec 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -209,6 +209,8 @@ enum
CpuAVX_VNNI,
/* Intel AVX-512 FP16 Instructions support required. */
CpuAVX512_FP16,
+ /* Intel AVX IFMA Instructions support required. */
+ CpuAVX_IFMA,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -388,6 +390,7 @@ typedef union i386_cpu_flags
unsigned int cputdx:1;
unsigned int cpuavx_vnni:1;
unsigned int cpuavx512_fp16:1;
+ unsigned int cpuavx_ifma:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index e07b36d4ec..827de35e1a 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3263,3 +3263,10 @@ vrsqrtph, 0x664e, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast
vrsqrtsh, 0x664f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
// FP16 (HFNI) instructions end.
+
+// AVX-IFMA instructions.
+
+vpmadd52huq, 0x66B5, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+
+// AVX-IFMA instructions end.
--
2.18.1
next prev parent reply other threads:[~2022-10-24 5:53 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14 9:12 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14 9:52 ` Jan Beulich
2022-10-14 18:10 ` H.J. Lu
2022-10-16 6:39 ` Jan Beulich
2022-10-17 22:23 ` H.J. Lu
2022-10-18 5:33 ` Jan Beulich
2022-10-18 21:28 ` H.J. Lu
2022-10-19 6:01 ` Jan Beulich
2022-10-19 21:27 ` H.J. Lu
2022-10-20 6:15 ` Jan Beulich
2022-10-24 2:07 ` Jiang, Haochen
2022-10-24 5:53 ` Jiang, Haochen [this message]
2022-10-24 19:09 ` H.J. Lu
2022-10-25 6:29 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-14 10:57 ` Jan Beulich
2022-10-21 3:22 ` Jiang, Haochen
2022-10-25 1:52 ` H.J. Lu
2022-10-14 9:12 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-14 12:58 ` Jan Beulich
2022-10-24 5:37 ` Kong, Lingling
2022-10-24 5:59 ` Kong, Lingling
2022-10-24 19:25 ` H.J. Lu
2022-10-25 6:44 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-14 13:46 ` Jan Beulich
2022-10-14 18:27 ` H.J. Lu
2022-10-14 21:51 ` H.J. Lu
2022-10-16 6:34 ` Jan Beulich
2022-10-17 23:31 ` H.J. Lu
2022-10-16 6:25 ` Jan Beulich
2022-10-17 23:44 ` H.J. Lu
2022-10-16 6:19 ` Jan Beulich
2022-10-24 2:30 ` Jiang, Haochen
2022-10-24 19:12 ` H.J. Lu
2022-10-24 5:55 ` Jiang, Haochen
2022-10-25 6:53 ` Jan Beulich
2022-10-26 3:03 ` Jiang, Haochen
2022-10-26 8:49 ` Jan Beulich
2022-10-27 3:09 ` Jiang, Haochen
2022-10-27 6:37 ` Jan Beulich
2022-10-28 0:59 ` Jiang, Haochen
2022-10-14 9:12 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-14 13:53 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-14 14:38 ` Jan Beulich
2022-10-16 6:15 ` Jan Beulich
2022-10-24 3:12 ` Jiang, Haochen
2022-10-24 19:17 ` H.J. Lu
2022-10-24 5:56 ` Jiang, Haochen
2022-10-25 7:01 ` Jan Beulich
2022-10-26 5:16 ` Jiang, Haochen
2022-10-26 8:56 ` Jan Beulich
2022-10-27 3:50 ` Jiang, Haochen
2022-10-27 6:39 ` Jan Beulich
2022-10-27 18:46 ` H.J. Lu
2022-10-28 6:52 ` Jan Beulich
2022-10-28 8:10 ` Jiang, Haochen
2022-10-28 8:22 ` Jan Beulich
2022-10-28 8:31 ` Jiang, Haochen
2022-10-28 8:40 ` Jan Beulich
2022-10-28 16:08 ` H.J. Lu
2022-10-31 9:41 ` Jan Beulich
2022-10-31 16:49 ` H.J. Lu
2022-11-06 12:50 ` Kong, Lingling
2022-11-07 9:24 ` Jan Beulich
2022-11-07 13:37 ` Kong, Lingling
2022-11-07 20:03 ` H.J. Lu
2022-10-17 23:23 ` H.J. Lu
2022-10-18 5:38 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-17 7:17 ` Jan Beulich
2022-10-24 2:52 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:14 ` H.J. Lu
2022-10-25 7:04 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-17 7:20 ` Jan Beulich
2022-10-24 3:03 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:15 ` H.J. Lu
2022-10-25 7:07 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-17 7:35 ` Jan Beulich
2022-10-18 9:01 ` Cui, Lili
2022-10-18 9:23 ` Jan Beulich
2022-10-18 9:33 ` Jiang, Haochen
2022-10-19 10:33 ` Cui, Lili
2022-10-19 13:35 ` Jan Beulich
2022-10-19 14:05 ` Cui, Lili
2022-10-19 14:09 ` Jan Beulich
2022-10-19 14:41 ` Cui, Lili
2022-10-19 15:04 ` Jan Beulich
2022-10-19 15:21 ` Cui, Lili
2022-10-19 14:01 ` Jiang, Haochen
2022-10-19 14:13 ` Jan Beulich
2022-10-19 14:58 ` Jiang, Haochen
2022-10-25 6:02 ` Jan Beulich
2022-10-25 13:05 ` Cui, Lili
2022-10-14 9:12 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-17 8:15 ` Jan Beulich
2022-10-25 13:03 ` Cui, Lili
2022-10-25 15:41 ` Jan Beulich
2022-10-25 15:52 ` Jan Beulich
2022-10-25 17:01 ` H.J. Lu
2022-10-26 13:42 ` Cui, Lili
2022-10-26 13:53 ` Jan Beulich
2022-10-27 6:04 ` Cui, Lili
2022-10-27 6:45 ` Jan Beulich
2022-10-27 7:01 ` Cui, Lili
2022-10-27 7:15 ` Jan Beulich
2022-10-27 7:43 ` Cui, Lili
2022-10-28 9:03 ` Cui, Lili
2022-10-28 15:54 ` H.J. Lu
2022-10-31 13:23 ` Cui, Lili
2022-10-31 14:45 ` Mike Frysinger
2022-10-31 16:25 ` H.J. Lu
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:55 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=SA1PR11MB5946DDA650C165540BACD061EC2E9@SA1PR11MB5946.namprd11.prod.outlook.com \
--to=haochen.jiang@intel.com \
--cc=JBeulich@suse.com \
--cc=binutils@sourceware.org \
--cc=hjl.tools@gmail.com \
--cc=hongyu.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).