From: Haochen Jiang <haochen.jiang@intel.com>
To: binutils@sourceware.org
Cc: jbeulich@suse.com, hjl.tools@gmail.com, "Hu, Lin1" <lin1.hu@intel.com>
Subject: [PATCH 07/10] Support Intel WRMSRNS
Date: Wed, 19 Oct 2022 23:15:31 +0800 [thread overview]
Message-ID: <20221019151534.45521-8-haochen.jiang@intel.com> (raw)
In-Reply-To: <20221019151534.45521-1-haochen.jiang@intel.com>
From: "Hu, Lin1" <lin1.hu@intel.com>
gas/ChangeLog:
* NEWS: Support Intel WRMSRNS.
* config/tc-i386.c: Add wrmsrns.
* doc/c-i386.texi: Document .wrmsrns.
* testsuite/gas/i386/i386.exp: Add WRMSRNS tests.
* testsuite/gas/i386/wrmsrns-intel.d: New test.
* testsuite/gas/i386/wrmsrns.d: Ditto.
* testsuite/gas/i386/wrmsrns.s: Ditto.
* testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto.
* testsuite/gas/i386/x86-64-wrmsrns.d: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New.
(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6.
(rm_table): New entry for wrmsrns.
* i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS
and CPU_ANY_WRMSRNS_FLAGS.
(cpu_flags): Add CpuWRMSRNS.
* i386-init.h: Regenerated.
* i386-opc.h (CpuWRMSRNS): New.
(i386_cpu_flags): Add cpuwrmsrns.
* i386-opc.tbl: Add WRMSRNS instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/i386.exp | 4 +
gas/testsuite/gas/i386/wrmsrns-intel.d | 12 +
gas/testsuite/gas/i386/wrmsrns.d | 12 +
gas/testsuite/gas/i386/wrmsrns.s | 8 +
gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d | 12 +
gas/testsuite/gas/i386/x86-64-wrmsrns.d | 12 +
opcodes/i386-dis.c | 7 +
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 514 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 6 +
opcodes/i386-tbl.h | 7859 +++++++++--------
15 files changed, 4288 insertions(+), 4172 deletions(-)
create mode 100644 gas/testsuite/gas/i386/wrmsrns-intel.d
create mode 100644 gas/testsuite/gas/i386/wrmsrns.d
create mode 100644 gas/testsuite/gas/i386/wrmsrns.s
create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns.d
diff --git a/gas/NEWS b/gas/NEWS
index f352c5ab89..2d745dfc31 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel WRMSRNS instructions.
+
* Add support for Intel RAO-INT instructions.
* Add support for Intel CMPccXADD instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 0ca9b43610..a332889f71 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1099,6 +1099,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
+ SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index e15cf7a7aa..d8376566be 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -199,6 +199,7 @@ accept various extension mnemonics. For example,
@code{avx_ne_convert},
@code{cmpccxadd},
@code{raoint},
+@code{wrmsrns},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -1492,7 +1493,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
-@item @samp{.cmpccxadd} @tab @samp{.raoint}
+@item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 1eb0eabb6b..c924075180 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -488,6 +488,8 @@ if [gas_32_check] then {
run_list_test "cmpccxadd-inval"
run_dump_test "raoint"
run_dump_test "raoint-intel"
+ run_dump_test "wrmsrns"
+ run_dump_test "wrmsrns-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1166,6 +1168,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-cmpccxadd-intel"
run_dump_test "x86-64-raoint"
run_dump_test "x86-64-raoint-intel"
+ run_dump_test "x86-64-wrmsrns"
+ run_dump_test "x86-64-wrmsrns-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/wrmsrns-intel.d b/gas/testsuite/gas/i386/wrmsrns-intel.d
new file mode 100644
index 0000000000..83194511a5
--- /dev/null
+++ b/gas/testsuite/gas/i386/wrmsrns-intel.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 WRMSRNS insns (Intel disassembly)
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/gas/testsuite/gas/i386/wrmsrns.d b/gas/testsuite/gas/i386/wrmsrns.d
new file mode 100644
index 0000000000..e804adc501
--- /dev/null
+++ b/gas/testsuite/gas/i386/wrmsrns.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw
+#name: i386 WRMSRNS insns
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/gas/testsuite/gas/i386/wrmsrns.s b/gas/testsuite/gas/i386/wrmsrns.s
new file mode 100644
index 0000000000..a450b0536d
--- /dev/null
+++ b/gas/testsuite/gas/i386/wrmsrns.s
@@ -0,0 +1,8 @@
+# Check WRMSRNS instructions
+
+ .text
+_start:
+ wrmsrns #WRMSRNS
+
+.intel_syntax noprefix
+ wrmsrns #WRMSRNS
diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
new file mode 100644
index 0000000000..2f789ed5df
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 WRMSRNS insns (Intel disassembly)
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns.d b/gas/testsuite/gas/i386/x86-64-wrmsrns.d
new file mode 100644
index 0000000000..b8535c266a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-wrmsrns.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw
+#name: x86_64 WRMSRNS insns
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 3a990e4e63..064a1bc0ce 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1000,6 +1000,7 @@ enum
enum
{
PREFIX_90 = 0,
+ PREFIX_0F01_REG_0_MOD_3_RM_6,
PREFIX_0F01_REG_1_RM_4,
PREFIX_0F01_REG_1_RM_5,
PREFIX_0F01_REG_1_RM_6,
@@ -2970,6 +2971,11 @@ static const struct dis386 prefix_table[][4] = {
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
+ /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
+ {
+ { "wrmsrns", { Skip_MODRM }, 0 },
+ },
+
/* PREFIX_0F01_REG_1_RM_4 */
{
{ Bad_Opcode },
@@ -8733,6 +8739,7 @@ static const struct dis386 rm_table[][8] = {
{ "vmresume", { Skip_MODRM }, 0 },
{ "vmxoff", { Skip_MODRM }, 0 },
{ "pconfig", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
},
{
/* RM_0F01_REG_1 */
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 5d75646c7e..0bfccdc7af 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -255,6 +255,8 @@ static initializer cpu_flag_init[] =
"CpuCMPCCXADD" },
{ "CPU_RAOINT_FLAGS",
"CpuRAOINT" },
+ { "CPU_WRMSRNS_FLAGS",
+ "CpuWRMSRNS" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -459,6 +461,8 @@ static initializer cpu_flag_init[] =
"CpuCMPCCXADD" },
{ "CPU_ANY_RAOINT_FLAGS",
"CpuRAOINT" },
+ { "CPU_ANY_WRMSRNS_FLAGS",
+ "CpuWRMSRNS" },
};
static initializer operand_type_init[] =
@@ -665,6 +669,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX_NE_CONVERT),
BITFIELD (CpuCMPCCXADD),
BITFIELD (CpuRAOINT),
+ BITFIELD (CpuWRMSRNS),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index cb6c372203..90e0591ae2 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -219,6 +219,8 @@ enum
CpuCMPCCXADD,
/* Intel RAO INT Instructions support required. */
CpuRAOINT,
+ /* Intel WRMSRNS Instructions support required */
+ CpuWRMSRNS,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -403,6 +405,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx_ne_convert:1;
unsigned int cpucmpccxadd:1;
unsigned int cpuraoint:1;
+ unsigned int cpuwrmsrns:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index dacafe1e14..bff32e69c2 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3311,3 +3311,9 @@ aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ld
axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
// RAOINT instructions end.
+
+// WRMSRNS instruction.
+
+wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+
+// WRMSRNS instruction end.
--
2.18.1
next prev parent reply other threads:[~2022-10-19 15:17 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-19 15:15 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-25 6:34 ` Jan Beulich
2022-10-19 15:15 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-19 15:15 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-19 15:15 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-19 15:15 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-19 15:15 ` Haochen Jiang [this message]
2022-10-19 15:15 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-19 15:15 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-19 15:15 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-25 7:11 ` Jan Beulich
2022-10-25 7:49 ` Cui, Lili
2022-10-25 8:31 ` Jan Beulich
-- strict thread matches above, loose matches on Subject: below --
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:56 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-14 9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14 9:12 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-17 7:17 ` Jan Beulich
2022-10-24 2:52 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:14 ` H.J. Lu
2022-10-25 7:04 ` Jan Beulich
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