From: Nathan Huckleberry <nhuck@google.com>
To: binutils@sourceware.org
Cc: nhuck@pmull.org,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
"Nathan Huckleberry" <nhuck@google.com>
Subject: [PATCH 03/14] Add support for the Zvkg ISA extension.
Date: Thu, 29 Jun 2023 10:18:28 -0700 [thread overview]
Message-ID: <20230629171839.573187-4-nhuck@google.com> (raw)
In-Reply-To: <20230629171839.573187-1-nhuck@google.com>
From: Christoph Müllner <christoph.muellner@vrull.eu>
Zvkg is part of the vector crypto extensions.
This extension adds the following instructions:
- vghsh.vv
- vgmul.vv
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvkg.d | 10 ++++++++++
gas/testsuite/gas/riscv/zvkg.s | 2 ++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
6 files changed, 30 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkg.d
create mode 100644 gas/testsuite/gas/riscv/zvkg.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a56b2b840b6..b51d4f4438f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1261,6 +1261,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2417,6 +2418,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvbb");
case INSN_CLASS_ZVBC:
return riscv_subset_supports (rps, "zvbc");
+ case INSN_CLASS_ZVKG:
+ return riscv_subset_supports (rps, "zvkg");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2581,6 +2584,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvbb");
case INSN_CLASS_ZVBC:
return _("zvbc");
+ case INSN_CLASS_ZVKG:
+ return _("zvkg");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkg.d b/gas/testsuite/gas/riscv/zvkg.d
new file mode 100644
index 00000000000..7f898d377b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.d
@@ -0,0 +1,10 @@
+#as: -march=rv64gc_zvkg
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghsh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+a2c8a277[ ]+vgmul.vv[ ]+v4,v12
diff --git a/gas/testsuite/gas/riscv/zvkg.s b/gas/testsuite/gas/riscv/zvkg.s
new file mode 100644
index 00000000000..b802d6add39
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.s
@@ -0,0 +1,2 @@
+ vghsh.vv v4, v8, v12
+ vgmul.vv v4, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index e1f2966499a..9bc75fd0e59 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2097,6 +2097,11 @@
#define MASK_VCLMULH_VV 0xfc00707f
#define MATCH_VCLMULH_VX 0x34006057
#define MASK_VCLMULH_VX 0xfc00707f
+/* Zvkg instructions. */
+#define MATCH_VGHSH_VV 0xb2002077
+#define MASK_VGHSH_VV 0xfe00707f
+#define MATCH_VGMUL_VV 0xa208a077
+#define MASK_VGMUL_VV 0xfe0ff07f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3187,6 +3192,9 @@ DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
+/* Zvkg instructions. */
+DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
+DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 0f00bc2e6fb..ae13dc17022 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -411,6 +411,7 @@ enum riscv_insn_class
INSN_CLASS_ZVEF,
INSN_CLASS_ZVBB,
INSN_CLASS_ZVBC,
+ INSN_CLASS_ZVKG,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 79a5e2c694a..09c8444ee74 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1839,6 +1839,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
+/* Zvkg instructions. */
+{"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
+{"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.41.0.255.g8b1d071c50-goog
next prev parent reply other threads:[~2023-06-29 17:18 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-29 17:18 [PATCH 00/14] Support RISC-V Vector Cryptography Extensions Nathan Huckleberry
2023-06-29 17:18 ` [PATCH 01/14] Add support for the Zvbb ISA extension Nathan Huckleberry
2023-06-30 17:51 ` Jeff Law
2023-06-30 20:29 ` Christoph Müllner
2023-06-30 20:57 ` Jeff Law
2023-06-30 22:01 ` Christoph Müllner
2023-06-30 22:16 ` Palmer Dabbelt
2023-06-29 17:18 ` [PATCH 02/14] Add support for the Zvbc " Nathan Huckleberry
2023-06-30 17:56 ` Jeff Law
2023-06-29 17:18 ` Nathan Huckleberry [this message]
2023-06-29 17:18 ` [PATCH 04/14] Add support for the Zvkned " Nathan Huckleberry
2023-06-30 19:30 ` Jeff Law
2023-06-29 17:18 ` [PATCH 05/14] Add support for the Zvknh[a,b] ISA extensions Nathan Huckleberry
2023-06-30 19:33 ` Jeff Law
2023-06-29 17:18 ` [PATCH 06/14] Add support for the Zvksed ISA extension Nathan Huckleberry
2023-06-30 20:06 ` Jeff Law
2023-06-29 17:18 ` [PATCH 07/14] Adds support for the Zvksh " Nathan Huckleberry
2023-06-30 20:08 ` Jeff Law
2023-06-29 17:18 ` [PATCH 08/14] Add support for the Zvkn " Nathan Huckleberry
2023-06-30 20:12 ` Jeff Law
2023-06-29 17:18 ` [PATCH 09/14] Allow nested implications for extensions Nathan Huckleberry
2023-06-30 20:44 ` Jeff Law
2023-06-30 21:53 ` Christoph Müllner
2023-06-30 22:24 ` Jeff Law
2023-06-30 23:48 ` Nathan Huckleberry
2023-07-01 5:22 ` Christoph Müllner
2023-07-01 13:08 ` Jeff Law
2023-07-01 13:33 ` Jeff Law
2023-07-02 20:01 ` Christoph Müllner
2023-07-05 21:29 ` Jeff Law
2023-06-29 17:18 ` [PATCH 10/14] Add support for the Zvkng ISA extension Nathan Huckleberry
2023-06-30 20:14 ` Jeff Law
2023-06-29 17:18 ` [PATCH 11/14] Add support for the Zvks " Nathan Huckleberry
2023-06-29 17:18 ` [PATCH 12/14] Add support for the Zvksg " Nathan Huckleberry
2023-06-29 17:18 ` [PATCH 13/14] Add support for the Zvknc " Nathan Huckleberry
2023-06-29 17:18 ` [PATCH 14/14] Add support for the Zvksc " Nathan Huckleberry
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