[PATCH 0/3] RISC-V: Support CORE-V XCVELW, XCVBI, and XCVMEM extensions

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* [PATCH 0/3] RISC-V: Support CORE-V XCVELW, XCVBI, and XCVMEM extensions
@ 2023-11-13 12:14 Mary Bennett
  2023-11-13 12:14 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Mary Bennett @ 2023-11-13 12:14 UTC (permalink / raw)
  To: binutils; +Cc: mary.bennett

This patch series presents the comprehensive implementation of the ELW, BI, and MEM
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V instructions are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

[2] github.com/openhwgroup/corev-binutils-gdb

Contributors:
      Mary Bennett <mary.bennett@embecosm.com>
      Nandni Jamnadas <nandni.jamnadas@embecosm.com>
      Pietra Ferreira <pietra.ferreira@embecosm.com>
      Charlie Keaney
      Jessica Mills
      Craig Blackmore <craig.blackmore@embecosm.com>
      Simon Cook <simon.cook@embecosm.com>
      Jeremy Bennett <jeremy.bennett@embecosm.com>
      Helene Chelin <helene.chelin@embecosm.com>
      Nazareno Bruschi <nazareno.bruschi@embecosm.com>
      Lin Sinan

RISC-V: Add support for XCVmem extension in CV32E40P
RISC-V: Add support for XCVelw extension in CV32E40P
RISC-V: Add support for XCVbi extension in CV32E40P

 bfd/elfxx-riscv.c                             | 15 ++++++
 gas/config/tc-riscv.c                         | 12 ++++-
 gas/doc/c-riscv.texi                          | 15 ++++++
 gas/testsuite/gas/riscv/cv-bi-beqimm.d        | 12 +++++
 gas/testsuite/gas/riscv/cv-bi-beqimm.s        |  4 ++
 gas/testsuite/gas/riscv/cv-bi-bneimm.d        | 12 +++++
 gas/testsuite/gas/riscv/cv-bi-bneimm.s        |  4 ++
 gas/testsuite/gas/riscv/cv-bi-fail-march.d    |  3 ++
 gas/testsuite/gas/riscv/cv-bi-fail-march.l    |  3 ++
 gas/testsuite/gas/riscv/cv-bi-fail-march.s    |  5 ++
 .../gas/riscv/cv-bi-fail-operand-01.d         |  3 ++
 .../gas/riscv/cv-bi-fail-operand-01.l         |  3 ++
 .../gas/riscv/cv-bi-fail-operand-01.s         |  4 ++
 .../gas/riscv/cv-bi-fail-operand-02.d         |  3 ++
 .../gas/riscv/cv-bi-fail-operand-02.l         |  3 ++
 .../gas/riscv/cv-bi-fail-operand-02.s         |  4 ++
 .../gas/riscv/cv-bi-fail-operand-03.d         |  3 ++
 .../gas/riscv/cv-bi-fail-operand-03.l         |  9 ++++
 .../gas/riscv/cv-bi-fail-operand-03.s         | 10 ++++
 gas/testsuite/gas/riscv/cv-elw-fail-march.d   |  3 ++
 gas/testsuite/gas/riscv/cv-elw-fail-march.l   | 38 +++++++++++++++
 gas/testsuite/gas/riscv/cv-elw-fail-march.s   | 42 +++++++++++++++++
 gas/testsuite/gas/riscv/cv-elw-fail.d         |  3 ++
 gas/testsuite/gas/riscv/cv-elw-fail.l         |  5 ++
 gas/testsuite/gas/riscv/cv-elw-fail.s         |  8 ++++
 gas/testsuite/gas/riscv/cv-elw-pass.d         | 46 +++++++++++++++++++
 gas/testsuite/gas/riscv/cv-elw-pass.s         | 42 +++++++++++++++++
 gas/testsuite/gas/riscv/cv-mem-fail-march.d   |  3 ++
 gas/testsuite/gas/riscv/cv-mem-fail-march.l   | 25 ++++++++++
 gas/testsuite/gas/riscv/cv-mem-fail-march.s   | 26 +++++++++++
 .../gas/riscv/cv-mem-fail-operand-01.d        |  3 ++
 .../gas/riscv/cv-mem-fail-operand-01.l        | 21 +++++++++
 .../gas/riscv/cv-mem-fail-operand-01.s        | 22 +++++++++
 .../gas/riscv/cv-mem-fail-operand-02.d        |  3 ++
 .../gas/riscv/cv-mem-fail-operand-02.l        | 13 ++++++
 .../gas/riscv/cv-mem-fail-operand-02.s        | 14 ++++++
 .../gas/riscv/cv-mem-fail-operand-03.d        |  3 ++
 .../gas/riscv/cv-mem-fail-operand-03.l        | 33 +++++++++++++
 .../gas/riscv/cv-mem-fail-operand-03.s        | 34 ++++++++++++++
 .../gas/riscv/cv-mem-fail-operand-04.d        |  3 ++
 .../gas/riscv/cv-mem-fail-operand-04.l        | 41 +++++++++++++++++
 .../gas/riscv/cv-mem-fail-operand-04.s        | 42 +++++++++++++++++
 .../gas/riscv/cv-mem-fail-operand-05.d        |  3 ++
 .../gas/riscv/cv-mem-fail-operand-05.l        | 25 ++++++++++
 .../gas/riscv/cv-mem-fail-operand-05.s        | 26 +++++++++++
 gas/testsuite/gas/riscv/cv-mem-lbpost.d       | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lbpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lbrr.d         | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lbrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lbrrpost.d     | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lbrrpost.s     |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lbupost.d      | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lbupost.s      |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lburr.d        | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lburr.s        |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lburrpost.d    | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lburrpost.s    |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhpost.d       | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lhpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhrr.d         | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lhrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhrrpost.d     | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lhrrpost.s     |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhupost.d      | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lhupost.s      |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhurr.d        | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lhurr.s        |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhurrpost.d    | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lhurrpost.s    |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lwpost.d       | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lwpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lwrr.d         | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lwrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lwrrpost.d     | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-lwrrpost.s     |  4 ++
 gas/testsuite/gas/riscv/cv-mem-sbpost.d       | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-sbpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-sbrr.d         | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-sbrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-sbrrpost.d     | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-sbrrpost.s     |  4 ++
 gas/testsuite/gas/riscv/cv-mem-shpost.d       | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-shpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-shrr.d         | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-shrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-shrrpost.d     | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-shrrpost.s     |  4 ++
 gas/testsuite/gas/riscv/cv-mem-swpost.d       | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-swpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-swrr.d         | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-swrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-swrrpost.d     | 12 +++++
 gas/testsuite/gas/riscv/cv-mem-swrrpost.s     |  4 ++
 include/opcode/riscv-opc.h                    | 39 ++++++++++++++++
 include/opcode/riscv.h                        |  6 +++
 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d      | 21 +++++++++
 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s      | 11 +++++
 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d      | 21 +++++++++
 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s      | 11 +++++
 ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp    |  2 +
 opcodes/riscv-dis.c                           |  4 ++
 opcodes/riscv-opc.c                           | 33 +++++++++++++
 102 files changed, 1185 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.s
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.s
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbupost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbupost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhupost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhupost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrrpost.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s

-- 
2.34.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P
  2023-11-13 12:14 [PATCH 0/3] RISC-V: Support CORE-V XCVELW, XCVBI, and XCVMEM extensions Mary Bennett
@ 2023-11-13 12:14 ` Mary Bennett
  2023-11-21  4:20   ` Nelson Chu
  2023-11-13 12:14 ` [PATCH 2/3] RISC-V: Add support for XCVbi " Mary Bennett
  2023-11-13 12:14 ` [PATCH 3/3] RISC-V: Add support for XCVmem " Mary Bennett
  2 siblings, 1 reply; 5+ messages in thread
From: Mary Bennett @ 2023-11-13 12:14 UTC (permalink / raw)
  To: binutils; +Cc: mary.bennett

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

        * doc/c-riscv.texi: Note XCVelw as an additional ISA extension
          for CORE-V.
        * testsuite/gas/riscv/cv-elw-fail.d: New test.
        * testsuite/gas/riscv/cv-elw-fail.l: New test.
        * testsuite/gas/riscv/cv-elw-fail.s: New test.
        * testsuite/gas/riscv/cv-elw-fail-march.d: New test.
	* testsuite/gas/riscv/cv-elw-fail-march.l: New test.
        * testsuite/gas/riscv/cv-elw-fail-march.s: New test.
        * testsuite/gas/riscv/cv-elw-pass.d: New test.
        * testsuite/gas/riscv/cv-elw-pass.s: New test.

opcodes/ChangeLog:

        * riscv-opc.c: (riscv_opcode) Add event load instructions.

include/ChangeLog:

        * opcode/riscv-opc.h: Add corresponding MATCH and MASK
          instruction opcode macros.
        * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
---
 bfd/elfxx-riscv.c                           |  5 +++
 gas/doc/c-riscv.texi                        |  5 +++
 gas/testsuite/gas/riscv/cv-elw-fail-march.d |  3 ++
 gas/testsuite/gas/riscv/cv-elw-fail-march.l | 38 +++++++++++++++++
 gas/testsuite/gas/riscv/cv-elw-fail-march.s | 42 +++++++++++++++++++
 gas/testsuite/gas/riscv/cv-elw-fail.d       |  3 ++
 gas/testsuite/gas/riscv/cv-elw-fail.l       |  5 +++
 gas/testsuite/gas/riscv/cv-elw-fail.s       |  8 ++++
 gas/testsuite/gas/riscv/cv-elw-pass.d       | 46 +++++++++++++++++++++
 gas/testsuite/gas/riscv/cv-elw-pass.s       | 42 +++++++++++++++++++
 include/opcode/riscv-opc.h                  |  3 ++
 include/opcode/riscv.h                      |  1 +
 opcodes/riscv-opc.c                         |  3 ++
 13 files changed, 204 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c9acf124626..545588b5afd 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1361,6 +1361,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
 {
   {"xcvmac",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvalu",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xcvelw",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2556,6 +2557,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvmac");
     case INSN_CLASS_XCVALU:
       return riscv_subset_supports (rps, "xcvalu");
+    case INSN_CLASS_XCVELW:
+      return riscv_subset_supports (rps, "xcvelw");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2800,6 +2803,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xcvmac";
     case INSN_CLASS_XCVALU:
       return "xcvalu";
+    case INSN_CLASS_XCVELW:
+      return "xcvelw";
     case INSN_CLASS_XTHEADBA:
       return "xtheadba";
     case INSN_CLASS_XTHEADBB:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index b23504648bd..8d2b8b2d4bb 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -754,6 +754,11 @@ The Xcvalu extension provides instructions for general ALU operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
+@item Xcvelw
+The Xcvelw extension provides instructions for event load word operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
 @item XTheadBa
 The XTheadBa extension provides instructions for address calculations.
 
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.d b/gas/testsuite/gas/riscv/cv-elw-fail-march.d
new file mode 100644
index 00000000000..5a3a6dba66b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-elw-fail-march.s
+#error_output: cv-elw-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.l b/gas/testsuite/gas/riscv/cv-elw-fail-march.l
new file mode 100644
index 00000000000..760a71b3827
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.l
@@ -0,0 +1,38 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.elw x5,-2048\(x6\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x5,0\(x6\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x5,20\(x6\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x5,2047\(x6\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x31,2047\(x31\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x0,0\(x0\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x1,1024\(x1\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x2,1024\(x2\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x3,1024\(x3\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x4,1024\(x4\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x5,1024\(x5\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x6,1024\(x6\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x7,1024\(x7\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x8,1024\(x8\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x9,1024\(x9\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x10,1024\(x10\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x11,1024\(x11\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x12,1024\(x12\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x13,1024\(x13\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x14,1024\(x14\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x15,1024\(x15\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x16,1024\(x16\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x17,1024\(x17\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x18,1024\(x18\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x19,1024\(x19\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x20,1024\(x20\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x21,1024\(x21\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x22,1024\(x22\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x23,1024\(x23\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x24,1024\(x24\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x25,1024\(x25\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x26,1024\(x26\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x27,1024\(x27\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x28,1024\(x28\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x29,1024\(x29\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x30,1024\(x30\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x31,1024\(x31\)', extension `xcvelw' required
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.s b/gas/testsuite/gas/riscv/cv-elw-fail-march.s
new file mode 100644
index 00000000000..8728f1cbdee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.s
@@ -0,0 +1,42 @@
+target:
+    # Immediate Boundary Tests
+    cv.elw x5,-2048(x6)
+    cv.elw x5,0(x6)
+    cv.elw x5,20(x6)
+    cv.elw x5,2047(x6)
+    cv.elw x31,2047(x31)
+    
+    # Register Boundary Tests
+    cv.elw x0,0(x0)
+    cv.elw x1,1024(x1)
+    cv.elw x2,1024(x2)
+    cv.elw x3,1024(x3)
+    cv.elw x4,1024(x4)
+    cv.elw x5,1024(x5)
+    cv.elw x6,1024(x6)
+    cv.elw x7,1024(x7)
+    cv.elw x8,1024(x8)
+    cv.elw x9,1024(x9)
+    cv.elw x10,1024(x10)
+    cv.elw x11,1024(x11)
+    cv.elw x12,1024(x12)
+    cv.elw x13,1024(x13)
+    cv.elw x14,1024(x14)
+    cv.elw x15,1024(x15)
+    cv.elw x16,1024(x16)
+    cv.elw x17,1024(x17)
+    cv.elw x18,1024(x18)
+    cv.elw x19,1024(x19)
+    cv.elw x20,1024(x20)
+    cv.elw x21,1024(x21)
+    cv.elw x22,1024(x22)
+    cv.elw x23,1024(x23)
+    cv.elw x24,1024(x24)
+    cv.elw x25,1024(x25)
+    cv.elw x26,1024(x26)
+    cv.elw x27,1024(x27)
+    cv.elw x28,1024(x28)
+    cv.elw x29,1024(x29)
+    cv.elw x30,1024(x30)
+    cv.elw x31,1024(x31)
+    
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.d b/gas/testsuite/gas/riscv/cv-elw-fail.d
new file mode 100644
index 00000000000..d7fd1d1a6cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvelw
+#source: cv-elw-fail.s
+#error_output: cv-elw-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.l b/gas/testsuite/gas/riscv/cv-elw-fail.l
new file mode 100644
index 00000000000..4d3f15ba138
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.elw x5,-2049\(x6\)'
+.*: Error: illegal operands `cv.elw x5,2048\(x6\)'
+.*: Error: illegal operands `cv.elw x-1,1024\(x-1\)'
+.*: Error: illegal operands `cv.elw x32,1024\(x32\)'
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.s b/gas/testsuite/gas/riscv/cv-elw-fail.s
new file mode 100644
index 00000000000..4ce122297f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail.s
@@ -0,0 +1,8 @@
+target:
+    # Immediate Boundary Tests
+    cv.elw x5,-2049(x6)
+    cv.elw x5,2048(x6)
+
+    # Register Boundary Tests
+    cv.elw x-1,1024(x-1)
+    cv.elw x32,1024(x32)
diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.d b/gas/testsuite/gas/riscv/cv-elw-pass.d
new file mode 100644
index 00000000000..fed2c870e7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-pass.d
@@ -0,0 +1,46 @@
+#as: -march=rv32i_xcvelw
+#source: cv-elw-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[  ]+0:[	]+80036283[ 	]+cv.elw[	]+t0,-2048\(t1\)
+[  ]+4:[	]+00036283[ 	]+cv.elw[	]+t0,0\(t1\)
+[  ]+8:[	]+01436283[ 	]+cv.elw[	]+t0,20\(t1\)
+[  ]+c:[	]+7ff36283[ 	]+cv.elw[	]+t0,2047\(t1\)
+[  ]+10:[	]+7fffef83[ 	]+cv.elw[	]+t6,2047\(t6\)
+[  ]+14:[	]+00006003[ 	]+cv.elw[	]+zero,0\(zero\) # 0 <target>
+[  ]+18:[	]+4000e083[ 	]+cv.elw[	]+ra,1024\(ra\)
+[  ]+1c:[	]+40016103[ 	]+cv.elw[	]+sp,1024\(sp\)
+[  ]+20:[	]+4001e183[ 	]+cv.elw[	]+gp,1024\(gp\)
+[  ]+24:[	]+40026203[ 	]+cv.elw[	]+tp,1024\(tp\) # 400 <target\+0x400>
+[  ]+28:[	]+4002e283[ 	]+cv.elw[	]+t0,1024\(t0\)
+[  ]+2c:[	]+40036303[ 	]+cv.elw[	]+t1,1024\(t1\)
+[  ]+30:[	]+4003e383[ 	]+cv.elw[	]+t2,1024\(t2\)
+[  ]+34:[	]+40046403[ 	]+cv.elw[	]+s0,1024\(s0\)
+[  ]+38:[	]+4004e483[ 	]+cv.elw[	]+s1,1024\(s1\)
+[  ]+3c:[	]+40056503[ 	]+cv.elw[	]+a0,1024\(a0\)
+[  ]+40:[	]+4005e583[ 	]+cv.elw[	]+a1,1024\(a1\)
+[  ]+44:[	]+40066603[ 	]+cv.elw[	]+a2,1024\(a2\)
+[  ]+48:[	]+4006e683[ 	]+cv.elw[	]+a3,1024\(a3\)
+[  ]+4c:[	]+40076703[ 	]+cv.elw[	]+a4,1024\(a4\)
+[  ]+50:[	]+4007e783[ 	]+cv.elw[	]+a5,1024\(a5\)
+[  ]+54:[	]+40086803[ 	]+cv.elw[	]+a6,1024\(a6\)
+[  ]+58:[	]+4008e883[ 	]+cv.elw[	]+a7,1024\(a7\)
+[  ]+5c:[	]+40096903[ 	]+cv.elw[	]+s2,1024\(s2\)
+[  ]+60:[	]+4009e983[ 	]+cv.elw[	]+s3,1024\(s3\)
+[  ]+64:[	]+400a6a03[ 	]+cv.elw[	]+s4,1024\(s4\)
+[  ]+68:[	]+400aea83[ 	]+cv.elw[	]+s5,1024\(s5\)
+[  ]+6c:[	]+400b6b03[ 	]+cv.elw[	]+s6,1024\(s6\)
+[  ]+70:[	]+400beb83[ 	]+cv.elw[	]+s7,1024\(s7\)
+[  ]+74:[	]+400c6c03[ 	]+cv.elw[	]+s8,1024\(s8\)
+[  ]+78:[	]+400cec83[ 	]+cv.elw[	]+s9,1024\(s9\)
+[  ]+7c:[	]+400d6d03[ 	]+cv.elw[	]+s10,1024\(s10\)
+[  ]+80:[	]+400ded83[ 	]+cv.elw[	]+s11,1024\(s11\)
+[  ]+84:[	]+400e6e03[ 	]+cv.elw[	]+t3,1024\(t3\)
+[  ]+88:[	]+400eee83[ 	]+cv.elw[	]+t4,1024\(t4\)
+[  ]+8c:[	]+400f6f03[ 	]+cv.elw[	]+t5,1024\(t5\)
+[  ]+90:[	]+400fef83[ 	]+cv.elw[	]+t6,1024\(t6\)
diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.s b/gas/testsuite/gas/riscv/cv-elw-pass.s
new file mode 100644
index 00000000000..ed6d1882f06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-pass.s
@@ -0,0 +1,42 @@
+target:
+    # Immediate Boundary Tests
+    cv.elw x5,-2048(x6)
+    cv.elw x5,0(x6)
+    cv.elw x5,20(x6)
+    cv.elw x5,2047(x6)
+    cv.elw x31,2047(x31)
+
+    # Register Boundary Tests
+    cv.elw x0,0(x0)
+    cv.elw x1,1024(x1)
+    cv.elw x2,1024(x2)
+    cv.elw x3,1024(x3)
+    cv.elw x4,1024(x4)
+    cv.elw x5,1024(x5)
+    cv.elw x6,1024(x6)
+    cv.elw x7,1024(x7)
+    cv.elw x8,1024(x8)
+    cv.elw x9,1024(x9)
+    cv.elw x10,1024(x10)
+    cv.elw x11,1024(x11)
+    cv.elw x12,1024(x12)
+    cv.elw x13,1024(x13)
+    cv.elw x14,1024(x14)
+    cv.elw x15,1024(x15)
+    cv.elw x16,1024(x16)
+    cv.elw x17,1024(x17)
+    cv.elw x18,1024(x18)
+    cv.elw x19,1024(x19)
+    cv.elw x20,1024(x20)
+    cv.elw x21,1024(x21)
+    cv.elw x22,1024(x22)
+    cv.elw x23,1024(x23)
+    cv.elw x24,1024(x24)
+    cv.elw x25,1024(x25)
+    cv.elw x26,1024(x26)
+    cv.elw x27,1024(x27)
+    cv.elw x28,1024(x28)
+    cv.elw x29,1024(x29)
+    cv.elw x30,1024(x30)
+    cv.elw x31,1024(x31)
+    
\ No newline at end of file
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 24217062edc..3d521703b98 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2424,6 +2424,9 @@
 #define MASK_CV_SUBRN 0xc000707f
 #define MATCH_CV_SUBURN 0xc000305b
 #define MASK_CV_SUBURN 0xc000707f
+/* Vendor-specific (CORE-V) Xcvelw instructions. */
+#define MATCH_CV_ELW 0x6003
+#define MASK_CV_ELW 0x707f
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 #define MATCH_TH_ADDSL 0x0000100b
 #define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 710a9b73189..df131aa3680 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -455,6 +455,7 @@ enum riscv_insn_class
   INSN_CLASS_H,
   INSN_CLASS_XCVMAC,
   INSN_CLASS_XCVALU,
+  INSN_CLASS_XCVELW,
   INSN_CLASS_XTHEADBA,
   INSN_CLASS_XTHEADBB,
   INSN_CLASS_XTHEADBS,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 72d727cd77e..c3fb20ec345 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2100,6 +2100,9 @@ const struct riscv_opcode riscv_opcodes[] =
 {"cv.subrnr",  0, INSN_CLASS_XCVALU, "d,s,t",     MATCH_CV_SUBRNR,  MASK_CV_SUBRNR, match_opcode, 0},
 {"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t",     MATCH_CV_SUBURNR, MASK_CV_SUBURNR, match_opcode, 0},
 
+/* Vendor-specific (CORE-V) Xcvelw instructions.  */
+{"cv.elw", 0, INSN_CLASS_XCVELW, "d,o(s)",  MATCH_CV_ELW, MASK_CV_ELW, match_opcode, 0},
+
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 {"th.addsl",    0, INSN_CLASS_XTHEADBA,    "d,s,t,Xtu2@25",   MATCH_TH_ADDSL,    MASK_TH_ADDSL,    match_opcode, 0},
 
-- 
2.34.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/3] RISC-V: Add support for XCVbi extension in CV32E40P
  2023-11-13 12:14 [PATCH 0/3] RISC-V: Support CORE-V XCVELW, XCVBI, and XCVMEM extensions Mary Bennett
  2023-11-13 12:14 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
@ 2023-11-13 12:14 ` Mary Bennett
  2023-11-13 12:14 ` [PATCH 3/3] RISC-V: Add support for XCVmem " Mary Bennett
  2 siblings, 0 replies; 5+ messages in thread
From: Mary Bennett @ 2023-11-13 12:14 UTC (permalink / raw)
  To: binutils; +Cc: mary.bennett

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>
  Nazareno Bruschi <nazareno.bruschi@embecosm.com>
  Lin Sinan

include/ChangeLog:
	* opcode/riscv-opc.h: Add corresponding MATCH and MASK
	  macros for XCVbi.
	* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
          for XCVbi.
	(enum riscv_insn_class): Add the XCVbi instruction class.

gas/ChangeLog:
	* config/tc-riscv.c (validate_riscv_insn): Add the necessary
	  operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Note XCVbi as an additional ISA extension
	  for CORE-V.
	* testsuite/gas/riscv/cv-bi-beqimm.d: New test.
	* testsuite/gas/riscv/cv-bi-beqimm.s: New test.
	* testsuite/gas/riscv/cv-bi-bneimm.d: New test.
	* testsuite/gas/riscv/cv-bi-bneimm.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test.

include/ChangeLog:
        * opcode/riscv-opc.h: Add corresponding MATCH and MASK
          macros for XCVbi.
        * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
          for XCVbi.
        (enum riscv_insn_class): Add the XCVbi instruction class.

ld/ChangeLog:
	* testsuite/ld-riscv-elf/cv-bi-beqimm.d: New test.
	* testsuite/ld-riscv-elf/cv-bi-beqimm.s: New test.
	* testsuite/ld-riscv-elf/cv-bi-bneimm.d: New test.
	* testsuite/ld-riscv-elf/cv-bi-bneimm.s: New test.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add new tests.

opcodes/ChangeLog:
	* riscv-dis.c (print_insn_args): Add disassembly for new operand.
	* riscv-opc.c: Add XCVbi instructions.
---
 bfd/elfxx-riscv.c                             |  5 +++++
 gas/config/tc-riscv.c                         | 12 ++++++++++-
 gas/doc/c-riscv.texi                          |  5 +++++
 gas/testsuite/gas/riscv/cv-bi-beqimm.d        | 12 +++++++++++
 gas/testsuite/gas/riscv/cv-bi-beqimm.s        |  4 ++++
 gas/testsuite/gas/riscv/cv-bi-bneimm.d        | 12 +++++++++++
 gas/testsuite/gas/riscv/cv-bi-bneimm.s        |  4 ++++
 gas/testsuite/gas/riscv/cv-bi-fail-march.d    |  3 +++
 gas/testsuite/gas/riscv/cv-bi-fail-march.l    |  3 +++
 gas/testsuite/gas/riscv/cv-bi-fail-march.s    |  5 +++++
 .../gas/riscv/cv-bi-fail-operand-01.d         |  3 +++
 .../gas/riscv/cv-bi-fail-operand-01.l         |  3 +++
 .../gas/riscv/cv-bi-fail-operand-01.s         |  4 ++++
 .../gas/riscv/cv-bi-fail-operand-02.d         |  3 +++
 .../gas/riscv/cv-bi-fail-operand-02.l         |  3 +++
 .../gas/riscv/cv-bi-fail-operand-02.s         |  4 ++++
 .../gas/riscv/cv-bi-fail-operand-03.d         |  3 +++
 .../gas/riscv/cv-bi-fail-operand-03.l         |  9 ++++++++
 .../gas/riscv/cv-bi-fail-operand-03.s         | 10 +++++++++
 include/opcode/riscv-opc.h                    |  5 +++++
 include/opcode/riscv.h                        |  4 ++++
 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d      | 21 +++++++++++++++++++
 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s      | 11 ++++++++++
 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d      | 21 +++++++++++++++++++
 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s      | 11 ++++++++++
 ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp    |  2 ++
 opcodes/riscv-dis.c                           |  4 ++++
 opcodes/riscv-opc.c                           |  4 ++++
 28 files changed, 189 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.s
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.s
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l
 create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 545588b5afd..8239f243b47 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1362,6 +1362,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xcvmac",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvalu",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvelw",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xcvbi",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2559,6 +2560,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvalu");
     case INSN_CLASS_XCVELW:
       return riscv_subset_supports (rps, "xcvelw");
+    case INSN_CLASS_XCVBI:
+      return riscv_subset_supports (rps, "xcvbi");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2805,6 +2808,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xcvalu";
     case INSN_CLASS_XCVELW:
       return "xcvelw";
+    case INSN_CLASS_XCVBI:
+      return "xcvbi";
     case INSN_CLASS_XTHEADBA:
       return "xtheadba";
     case INSN_CLASS_XTHEADBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 402c46ad753..8ebd2609969 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1485,7 +1485,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	      switch (*++oparg)
 		{
 		  case '2':
-		    /* ls2[4:0] */
+		  case '4':
 		    used_bits |= ENCODE_CV_IS2_UIMM5 (-1U);
 		    break;
 		  case '3':
@@ -3618,6 +3618,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 			ip->insn_opcode
 			    |= ENCODE_CV_IS3_UIMM5 (imm_expr->X_add_number);
 			continue;
+		      case '4':
+			my_getExpression (imm_expr, asarg);
+			check_absolute_expr (ip, imm_expr, FALSE);
+			asarg = expr_parse_end;
+			if (imm_expr->X_add_number < -16
+			    || imm_expr->X_add_number > 15)
+			  break;
+			ip->insn_opcode
+			    |= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);
+			continue;
 		      default:
 			goto unknown_riscv_ip_operand;
 		    }
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 8d2b8b2d4bb..8a0a2c67e42 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -759,6 +759,11 @@ The Xcvelw extension provides instructions for event load word operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
+@item Xcvbi
+The Xcvbi extension provides instructions for branch immediate operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
 @item XTheadBa
 The XTheadBa extension provides instructions for address calculations.
 
diff --git a/gas/testsuite/gas/riscv/cv-bi-beqimm.d b/gas/testsuite/gas/riscv/cv-bi-beqimm.d
new file mode 100644
index 00000000000..97ef57d91cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-beqimm.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvbi
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]+0:[ 	]+0102e00b[ 	]+cv.beqimm[ 	]+t0,-16,0 +<foo>
+[ 	]+4:[ 	]+fe5eee8b[ 	]+cv.beqimm[ 	]+t4,5,0 +<foo>
+[ 	]+8:[ 	]+fef3ec8b[ 	]+cv.beqimm[ 	]+t2,15,0 +<foo>
diff --git a/gas/testsuite/gas/riscv/cv-bi-beqimm.s b/gas/testsuite/gas/riscv/cv-bi-beqimm.s
new file mode 100644
index 00000000000..7fbb8f27515
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-beqimm.s
@@ -0,0 +1,4 @@
+foo:
+	cv.beqimm t0, -16, foo
+	cv.beqimm t4, 5, foo
+	cv.beqimm t2, 15, foo
diff --git a/gas/testsuite/gas/riscv/cv-bi-bneimm.d b/gas/testsuite/gas/riscv/cv-bi-bneimm.d
new file mode 100644
index 00000000000..7dddf408107
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-bneimm.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvbi
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]+0:[ 	]+0102f00b[ 	]+cv.bneimm[ 	]+t0,-16,0 +<foo>
+[ 	]+4:[ 	]+fe5efe8b[ 	]+cv.bneimm[ 	]+t4,5,0 +<foo>
+[ 	]+8:[ 	]+fef3fc8b[ 	]+cv.bneimm[ 	]+t2,15,0 +<foo>
diff --git a/gas/testsuite/gas/riscv/cv-bi-bneimm.s b/gas/testsuite/gas/riscv/cv-bi-bneimm.s
new file mode 100644
index 00000000000..8014e6a8a4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-bneimm.s
@@ -0,0 +1,4 @@
+foo:
+	cv.bneimm t0, -16, foo
+	cv.bneimm t4, 5, foo
+	cv.bneimm t2, 15, foo
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.d b/gas/testsuite/gas/riscv/cv-bi-fail-march.d
new file mode 100644
index 00000000000..7a24146afe2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-bi-fail-march.s
+#error_output: cv-bi-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.l b/gas/testsuite/gas/riscv/cv-bi-fail-march.l
new file mode 100644
index 00000000000..c351c64d414
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-march.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.beqimm t2,1,foo', extension `xcvbi' required
+.*: Error: unrecognized opcode `cv.bneimm t2,1,foo', extension `xcvbi' required
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.s b/gas/testsuite/gas/riscv/cv-bi-fail-march.s
new file mode 100644
index 00000000000..b7fa16de240
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-march.s
@@ -0,0 +1,5 @@
+# Absence of xcorev or xcorevbi march option disables all CORE-V
+# immediate branching extensions.
+foo:
+	cv.beqimm t2, 1, foo
+	cv.bneimm t2, 1, foo
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d
new file mode 100644
index 00000000000..cc73fdd6492
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbi
+#source: cv-bi-fail-operand-01.s
+#error_output: cv-bi-fail-operand-01.l
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l
new file mode 100644
index 00000000000..c76c5139429
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.beqimm 20,10,foo'
+.*: Error: illegal operands `cv.bneimm 8,-4,foo'
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s
new file mode 100644
index 00000000000..7c529d4d045
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s
@@ -0,0 +1,4 @@
+# Comparison target must be a register
+foo:
+	cv.beqimm 20, 10, foo
+	cv.bneimm 8, -4, foo
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d
new file mode 100644
index 00000000000..39741b9ed2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbi
+#source: cv-bi-fail-operand-02.s
+#error_output: cv-bi-fail-operand-02.l
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l
new file mode 100644
index 00000000000..7c766fb072a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: instruction cv.beqimm requires absolute expression
+.*: Error: instruction cv.bneimm requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s
new file mode 100644
index 00000000000..5c8874cb9ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s
@@ -0,0 +1,4 @@
+# Comparison value must be an immediate
+foo:
+	cv.beqimm t0, t1, foo
+	cv.bneimm t3, t4, foo
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d
new file mode 100644
index 00000000000..141efdeacc6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbi
+#source: cv-bi-fail-operand-03.s
+#error_output: cv-bi-fail-operand-03.l
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l
new file mode 100644
index 00000000000..af8ebce1284
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.beqimm t0,-17,foo'
+.*: Error: illegal operands `cv.beqimm t2,-32,foo'
+.*: Error: illegal operands `cv.beqimm t4,16,foo'
+.*: Error: illegal operands `cv.beqimm t3,44,foo'
+.*: Error: illegal operands `cv.bneimm t0,-17,foo'
+.*: Error: illegal operands `cv.bneimm t2,-32,foo'
+.*: Error: illegal operands `cv.bneimm t4,16,foo'
+.*: Error: illegal operands `cv.bneimm t3,44,foo'
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s
new file mode 100644
index 00000000000..9c7f67b4aed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s
@@ -0,0 +1,10 @@
+# Comparison value must be an immediate in range [-16, +15]
+foo:
+	cv.beqimm t0, -17, foo
+	cv.beqimm t2, -32, foo
+	cv.beqimm t4, 16, foo
+	cv.beqimm t3, 44, foo
+	cv.bneimm t0, -17, foo
+	cv.bneimm t2, -32, foo
+	cv.bneimm t4, 16, foo
+	cv.bneimm t3, 44, foo
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 3d521703b98..aa02dcf2f76 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2427,6 +2427,11 @@
 /* Vendor-specific (CORE-V) Xcvelw instructions. */
 #define MATCH_CV_ELW 0x6003
 #define MASK_CV_ELW 0x707f
+/* Vendor-specific (CORE-V) Xcvbi instructions. */
+#define MATCH_CV_BNEIMM 0x700b
+#define MASK_CV_BNEIMM 0x707f
+#define MATCH_CV_BEQIMM 0x600b
+#define MASK_CV_BEQIMM 0x707f
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 #define MATCH_TH_ADDSL 0x0000100b
 #define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index df131aa3680..c579ba85121 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -55,6 +55,7 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
 #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))
+#define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1))
 
 #define EXTRACT_ITYPE_IMM(x) \
   (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
@@ -117,6 +118,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 20, 5))
 #define EXTRACT_CV_IS3_UIMM5(x) \
   (RV_X(x, 25, 5))
+#define EXTRACT_CV_BI_IMM5(x) \
+  (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
 
 #define ENCODE_ITYPE_IMM(x) \
   (RV_X(x, 0, 12) << 20)
@@ -456,6 +459,7 @@ enum riscv_insn_class
   INSN_CLASS_XCVMAC,
   INSN_CLASS_XCVALU,
   INSN_CLASS_XCVELW,
+  INSN_CLASS_XCVBI,
   INSN_CLASS_XTHEADBA,
   INSN_CLASS_XTHEADBB,
   INSN_CLASS_XTHEADBS,
diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d
new file mode 100644
index 00000000000..b50d3846c1c
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d
@@ -0,0 +1,21 @@
+#name: beqimm relocation
+#source: cv-bi-beqimm.s
+#as: -march=rv32i_xcvbi
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+.* <func>:
+.*:[[:space:]]+00008067[[:space:]]+ret
+
+.* <_start>:
+.*:[[:space:]]+0102e40b[[:space:]]+cv.beqimm[[:space:]]+t0,-16,.*[[:space:]]+<L2>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
+
+.* <L2>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s
new file mode 100644
index 00000000000..88a6b293e69
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s
@@ -0,0 +1,11 @@
+        .option nopic
+        .text
+        .align 1
+        .globl _start
+        .type _start, @function
+
+func:   ret
+_start:
+        cv.beqimm       t0, -16, L2
+        call func
+L2:     nop
diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d
new file mode 100644
index 00000000000..52231a14b71
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d
@@ -0,0 +1,21 @@
+#name: bneimm relocation
+#source: cv-bi-bneimm.s
+#as: -march=rv32i_xcvbi
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+.* <func>:
+.*:[[:space:]]+00008067[[:space:]]+ret
+
+.* <_start>:
+.*:[[:space:]]+0102f40b[[:space:]]+cv.bneimm[[:space:]]+t0,-16,.*[[:space:]]+<L2>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
+
+.* <L2>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s
new file mode 100644
index 00000000000..0f514f02e1b
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s
@@ -0,0 +1,11 @@
+        .option nopic
+        .text
+        .align 1
+        .globl _start
+        .type _start, @function
+
+func:   ret
+_start:
+        cv.bneimm       t0, -16, L2
+        call func
+L2:     nop
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 947a266ba72..adcf8155345 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -173,6 +173,8 @@ if [istarget "riscv*-*-*"] {
     run_dump_test "attr-phdr"
     run_dump_test "relax-max-align-gp"
     run_dump_test "uleb128"
+    run_dump_test "cv-bi-bneimm"
+    run_dump_test "cv-bi-beqimm"
     run_ld_link_tests [list \
 	[list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
 	    "-march=rv32i -mabi=ilp32" {weakref32.s} \
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index ca328b4c997..b74bcbaf954 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -688,6 +688,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		    print (info->stream, dis_style_immediate, "%d",
 			((int) EXTRACT_CV_IS3_UIMM5 (l)));
 		    break;
+		  case '4':
+		    print (info->stream, dis_style_immediate, "%d",
+			((int) EXTRACT_CV_BI_IMM5 (l)));
+		    break;
 		  default:
 		    goto undefined_modifier;
 		}
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c3fb20ec345..c3c809f4545 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2103,6 +2103,10 @@ const struct riscv_opcode riscv_opcodes[] =
 /* Vendor-specific (CORE-V) Xcvelw instructions.  */
 {"cv.elw", 0, INSN_CLASS_XCVELW, "d,o(s)",  MATCH_CV_ELW, MASK_CV_ELW, match_opcode, 0},
 
+/* Vendor-specific (CORE-V) Xcvbi instructions.  */
+{"cv.beqimm", 0, INSN_CLASS_XCVBI, "s,Xc4,p", MATCH_CV_BEQIMM, MASK_CV_BEQIMM, match_opcode, 0},
+{"cv.bneimm", 0, INSN_CLASS_XCVBI, "s,Xc4,p", MATCH_CV_BNEIMM, MASK_CV_BNEIMM, match_opcode, 0},
+
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 {"th.addsl",    0, INSN_CLASS_XTHEADBA,    "d,s,t,Xtu2@25",   MATCH_TH_ADDSL,    MASK_TH_ADDSL,    match_opcode, 0},
 
-- 
2.34.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 3/3] RISC-V: Add support for XCVmem extension in CV32E40P
  2023-11-13 12:14 [PATCH 0/3] RISC-V: Support CORE-V XCVELW, XCVBI, and XCVMEM extensions Mary Bennett
  2023-11-13 12:14 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
  2023-11-13 12:14 ` [PATCH 2/3] RISC-V: Add support for XCVbi " Mary Bennett
@ 2023-11-13 12:14 ` Mary Bennett
  2 siblings, 0 replies; 5+ messages in thread
From: Mary Bennett @ 2023-11-13 12:14 UTC (permalink / raw)
  To: binutils; +Cc: mary.bennett

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:
	* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvmem`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:
	* doc/c-riscv.texi: Note XCVmem as an additional ISA extension
          for CORE-V.
	* testsuite/gas/riscv/cv-mem-fail-march.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-march.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-march.s: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-01.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-01.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-01.s: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-02.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-02.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-02.s: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-03.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-03.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-03.s: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-04.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-04.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-04.s: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-05.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-05.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-05.s: New test.
	* testsuite/gas/riscv/cv-mem-lbpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lbpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lbrr.d: New test.
	* testsuite/gas/riscv/cv-mem-lbrr.s: New test.
	* testsuite/gas/riscv/cv-mem-lbrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lbrrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lbupost.d: New test.
	* testsuite/gas/riscv/cv-mem-lbupost.s: New test.
	* testsuite/gas/riscv/cv-mem-lburr.d: New test.
	* testsuite/gas/riscv/cv-mem-lburr.s: New test.
	* testsuite/gas/riscv/cv-mem-lburrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lburrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lhpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lhpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lhrr.d: New test.
	* testsuite/gas/riscv/cv-mem-lhrr.s: New test.
	* testsuite/gas/riscv/cv-mem-lhrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lhrrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lhupost.d: New test.
	* testsuite/gas/riscv/cv-mem-lhupost.s: New test.
	* testsuite/gas/riscv/cv-mem-lhurr.d: New test.
	* testsuite/gas/riscv/cv-mem-lhurr.s: New test.
	* testsuite/gas/riscv/cv-mem-lhurrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lhurrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lwpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lwpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lwrr.d: New test.
	* testsuite/gas/riscv/cv-mem-lwrr.s: New test.
	* testsuite/gas/riscv/cv-mem-lwrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lwrrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-sbpost.d: New test.
	* testsuite/gas/riscv/cv-mem-sbpost.s: New test.
	* testsuite/gas/riscv/cv-mem-sbrr.d: New test.
	* testsuite/gas/riscv/cv-mem-sbrr.s: New test.
	* testsuite/gas/riscv/cv-mem-sbrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-sbrrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-shpost.d: New test.
	* testsuite/gas/riscv/cv-mem-shpost.s: New test.
	* testsuite/gas/riscv/cv-mem-shrr.d: New test.
	* testsuite/gas/riscv/cv-mem-shrr.s: New test.
	* testsuite/gas/riscv/cv-mem-shrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-shrrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-swpost.d: New test.
	* testsuite/gas/riscv/cv-mem-swpost.s: New test.
	* testsuite/gas/riscv/cv-mem-swrr.d: New test.
	* testsuite/gas/riscv/cv-mem-swrr.s: New test.
	* testsuite/gas/riscv/cv-mem-swrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-swrrpost.s: New test.

include/ChangeLog:
	* opcode/riscv-opc.h: Add corresponding MATCH and MASK macros
          for XCVmem.
	* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
          for XCVmem.
	(enum riscv_insn_class): Add the XCVmem instruction class.

opcodes/ChangeLog:
	* riscv-opc.c: Add XCVmem instructions.
---
 bfd/elfxx-riscv.c                             |  5 +++
 gas/doc/c-riscv.texi                          |  5 +++
 gas/testsuite/gas/riscv/cv-mem-fail-march.d   |  3 ++
 gas/testsuite/gas/riscv/cv-mem-fail-march.l   | 25 +++++++++++
 gas/testsuite/gas/riscv/cv-mem-fail-march.s   | 26 ++++++++++++
 .../gas/riscv/cv-mem-fail-operand-01.d        |  3 ++
 .../gas/riscv/cv-mem-fail-operand-01.l        | 21 ++++++++++
 .../gas/riscv/cv-mem-fail-operand-01.s        | 22 ++++++++++
 .../gas/riscv/cv-mem-fail-operand-02.d        |  3 ++
 .../gas/riscv/cv-mem-fail-operand-02.l        | 13 ++++++
 .../gas/riscv/cv-mem-fail-operand-02.s        | 14 +++++++
 .../gas/riscv/cv-mem-fail-operand-03.d        |  3 ++
 .../gas/riscv/cv-mem-fail-operand-03.l        | 33 +++++++++++++++
 .../gas/riscv/cv-mem-fail-operand-03.s        | 34 +++++++++++++++
 .../gas/riscv/cv-mem-fail-operand-04.d        |  3 ++
 .../gas/riscv/cv-mem-fail-operand-04.l        | 41 ++++++++++++++++++
 .../gas/riscv/cv-mem-fail-operand-04.s        | 42 +++++++++++++++++++
 .../gas/riscv/cv-mem-fail-operand-05.d        |  3 ++
 .../gas/riscv/cv-mem-fail-operand-05.l        | 25 +++++++++++
 .../gas/riscv/cv-mem-fail-operand-05.s        | 26 ++++++++++++
 gas/testsuite/gas/riscv/cv-mem-lbpost.d       | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lbpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lbrr.d         | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lbrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lbrrpost.d     | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lbrrpost.s     |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lbupost.d      | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lbupost.s      |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lburr.d        | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lburr.s        |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lburrpost.d    | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lburrpost.s    |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhpost.d       | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lhpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhrr.d         | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lhrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhrrpost.d     | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lhrrpost.s     |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhupost.d      | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lhupost.s      |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhurr.d        | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lhurr.s        |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lhurrpost.d    | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lhurrpost.s    |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lwpost.d       | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lwpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lwrr.d         | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lwrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-lwrrpost.d     | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-lwrrpost.s     |  4 ++
 gas/testsuite/gas/riscv/cv-mem-sbpost.d       | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-sbpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-sbrr.d         | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-sbrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-sbrrpost.d     | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-sbrrpost.s     |  4 ++
 gas/testsuite/gas/riscv/cv-mem-shpost.d       | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-shpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-shrr.d         | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-shrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-shrrpost.d     | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-shrrpost.s     |  4 ++
 gas/testsuite/gas/riscv/cv-mem-swpost.d       | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-swpost.s       |  4 ++
 gas/testsuite/gas/riscv/cv-mem-swrr.d         | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-swrr.s         |  4 ++
 gas/testsuite/gas/riscv/cv-mem-swrrpost.d     | 12 ++++++
 gas/testsuite/gas/riscv/cv-mem-swrrpost.s     |  4 ++
 include/opcode/riscv-opc.h                    | 31 ++++++++++++++
 include/opcode/riscv.h                        |  1 +
 opcodes/riscv-opc.c                           | 26 ++++++++++++
 71 files changed, 792 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbupost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbupost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhupost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhupost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrrpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swpost.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrr.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrr.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrrpost.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrrpost.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 8239f243b47..b2b8ea25a5a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1363,6 +1363,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xcvalu",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvelw",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvbi",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xcvmem",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2562,6 +2563,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvelw");
     case INSN_CLASS_XCVBI:
       return riscv_subset_supports (rps, "xcvbi");
+    case INSN_CLASS_XCVMEM:
+      return riscv_subset_supports (rps, "xcvmem");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2810,6 +2813,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xcvelw";
     case INSN_CLASS_XCVBI:
       return "xcvbi";
+    case INSN_CLASS_XCVMEM:
+      return "xcvmem";
     case INSN_CLASS_XTHEADBA:
       return "xtheadba";
     case INSN_CLASS_XTHEADBB:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 8a0a2c67e42..56e621ef0b1 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -764,6 +764,11 @@ The Xcvbi extension provides instructions for branch immediate operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
+@item Xcvmem
+The Xcvmem extension provides instructions for post inc load/store operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
 @item XTheadBa
 The XTheadBa extension provides instructions for address calculations.
 
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-march.d b/gas/testsuite/gas/riscv/cv-mem-fail-march.d
new file mode 100644
index 00000000000..a2dff75937b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-mem-fail-march.s
+#error_output: cv-mem-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-march.l b/gas/testsuite/gas/riscv/cv-mem-fail-march.l
new file mode 100644
index 00000000000..4c331344d26
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-march.l
@@ -0,0 +1,25 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.lb t4,t2\(t0\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t6,t1\(t4\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t2,t0\(t3\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t0,t5\(t1\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t1,t3\(t6\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lb t4,\(t0\),t2', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t6,\(t4\),t1', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t2,\(t3\),t0', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t0,\(t1\),t5', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t1,\(t6\),t3', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lb t4,\(t0\),23', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t6,\(t4\),0', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t2,\(t3\),77', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t0,\(t1\),101', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t1,\(t6\),6', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t0,t1\(t2\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t1,t3\(t4\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t1,t2\(t4\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t0,\(t2\),t1', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t1,\(t2\),t6', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t5,\(t2\),t6', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t6,\(t1\),10', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t3,\(t5\),80', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t1,\(t4\),20', extension `xcvmem' required
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-march.s b/gas/testsuite/gas/riscv/cv-mem-fail-march.s
new file mode 100644
index 00000000000..cd82d26a7c5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-march.s
@@ -0,0 +1,26 @@
+# Absence of xcvmem march option disables all CORE-V mem extensions
+target:
+	cv.lb t4, t2(t0)
+	cv.lbu t6, t1(t4)
+	cv.lh t2, t0(t3)
+	cv.lhu t0, t5(t1)
+	cv.lw t1, t3(t6)
+	cv.lb t4, (t0), t2
+	cv.lbu t6, (t4), t1
+	cv.lh t2, (t3), t0
+	cv.lhu t0, (t1), t5
+	cv.lw t1, (t6), t3
+	cv.lb t4, (t0), 23
+	cv.lbu t6, (t4), 0
+	cv.lh t2, (t3), 77
+	cv.lhu t0, (t1), 101
+	cv.lw t1, (t6), 6
+	cv.sb t0, t1(t2)
+	cv.sh t1, t3(t4)
+	cv.sw t1, t2(t4)
+	cv.sb t0, (t2), t1
+	cv.sh t1, (t2), t6
+	cv.sw t5, (t2), t6
+	cv.sb t6, (t1), 10
+	cv.sh t3, (t5), 80
+	cv.sw t1, (t4), 20
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d
new file mode 100644
index 00000000000..f1bb6120ab6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvmem
+#source: cv-mem-fail-operand-01.s
+#error_output: cv-mem-fail-operand-01.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l
new file mode 100644
index 00000000000..839929118a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l
@@ -0,0 +1,21 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.lb 20,10\(t1\)'
+.*: Error: illegal operands `cv.lb 32,\(t2\),15'
+.*: Error: illegal operands `cv.lb 40,t2\(t3\)'
+.*: Error: illegal operands `cv.lb 28,\(t4\),t3'
+.*: Error: illegal operands `cv.lbu 16,20\(t5\)'
+.*: Error: illegal operands `cv.lbu 20,\(t6\),30'
+.*: Error: illegal operands `cv.lbu 44,t4\(t1\)'
+.*: Error: illegal operands `cv.lbu 48,\(t2\),t5'
+.*: Error: illegal operands `cv.lh 52,25\(t3\)'
+.*: Error: illegal operands `cv.lh 12,\(t4\),10'
+.*: Error: illegal operands `cv.lh 16,t6\(t5\)'
+.*: Error: illegal operands `cv.lh 36,\(t6\),t1'
+.*: Error: illegal operands `cv.lhu 24,35\(t1\)'
+.*: Error: illegal operands `cv.lhu 12,\(t2\),13'
+.*: Error: illegal operands `cv.lhu 32,t2\(t3\)'
+.*: Error: illegal operands `cv.lhu 40,\(t4\),t3'
+.*: Error: illegal operands `cv.lw 44,18\(t5\)'
+.*: Error: illegal operands `cv.lw 48,\(t6\),8'
+.*: Error: illegal operands `cv.lw 24,t4\(t1\)'
+.*: Error: illegal operands `cv.lw 12,\(t2\),t5'
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s
new file mode 100644
index 00000000000..385b3f79704
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s
@@ -0,0 +1,22 @@
+# Destination operand must be a register
+target:
+	cv.lb 20, 10(t1)
+	cv.lb 32, (t2), 15
+	cv.lb 40, t2(t3)
+	cv.lb 28, (t4), t3
+	cv.lbu 16, 20(t5)
+	cv.lbu 20, (t6), 30
+	cv.lbu 44, t4(t1)
+	cv.lbu 48, (t2), t5
+	cv.lh 52, 25(t3)
+	cv.lh 12, (t4), 10
+	cv.lh 16, t6(t5)
+	cv.lh 36, (t6), t1
+	cv.lhu 24, 35(t1)
+	cv.lhu 12, (t2), 13
+	cv.lhu 32, t2(t3)
+	cv.lhu 40, (t4), t3
+	cv.lw 44, 18(t5)
+	cv.lw 48, (t6), 8
+	cv.lw 24, t4(t1)
+	cv.lw 12, (t2), t5
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d
new file mode 100644
index 00000000000..bbf723736f8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvmem
+#source: cv-mem-fail-operand-02.s
+#error_output: cv-mem-fail-operand-02.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l
new file mode 100644
index 00000000000..871a221ea6d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l
@@ -0,0 +1,13 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sb 12,10\(t1\)'
+.*: Error: illegal operands `cv.sb 14,\(t2\),20'
+.*: Error: illegal operands `cv.sb 16,t1\(t3\)'
+.*: Error: illegal operands `cv.sb 20,\(t4\),t2'
+.*: Error: illegal operands `cv.sh 30,30\(t5\)'
+.*: Error: illegal operands `cv.sh 15,\(t6\),40'
+.*: Error: illegal operands `cv.sh 45,t3\(t1\)'
+.*: Error: illegal operands `cv.sh 52,\(t2\),t4'
+.*: Error: illegal operands `cv.sw 12,12\(t3\)'
+.*: Error: illegal operands `cv.sw 10,\(t4\),16'
+.*: Error: illegal operands `cv.sw 82,t5\(t5\)'
+.*: Error: illegal operands `cv.sw 14,\(t1\),t6'
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s
new file mode 100644
index 00000000000..8d7a41f6323
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s
@@ -0,0 +1,14 @@
+# Source operand must be a register
+target:
+	cv.sb 12, 10(t1)
+	cv.sb 14, (t2), 20
+	cv.sb 16, t1(t3)
+	cv.sb 20, (t4), t2
+	cv.sh 30, 30(t5)
+	cv.sh 15, (t6), 40
+	cv.sh 45, t3(t1)
+	cv.sh 52, (t2), t4
+	cv.sw 12, 12(t3)
+	cv.sw 10, (t4), 16
+	cv.sw 82, t5(t5)
+	cv.sw 14, (t1), t6
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d
new file mode 100644
index 00000000000..653c30a3321
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvmem
+#source: cv-mem-fail-operand-03.s
+#error_output: cv-mem-fail-operand-03.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l
new file mode 100644
index 00000000000..4ffdbb318cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l
@@ -0,0 +1,33 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sb t0,10\(12\)'
+.*: Error: illegal operands `cv.sb t1,\(24\),20'
+.*: Error: illegal operands `cv.sb t2,t1\(25\)'
+.*: Error: illegal operands `cv.sb t3,\(75\),t2'
+.*: Error: illegal operands `cv.sh t4,30\(13\)'
+.*: Error: illegal operands `cv.sh t5,\(16\),40'
+.*: Error: illegal operands `cv.sh t6,t3\(31\)'
+.*: Error: illegal operands `cv.sh t0,\(37\),t4'
+.*: Error: illegal operands `cv.sw t1,12\(51\)'
+.*: Error: illegal operands `cv.sw t2,\(43\),16'
+.*: Error: illegal operands `cv.sw t3,t5\(61\)'
+.*: Error: illegal operands `cv.sw t4,\(67\),t6'
+.*: Error: illegal operands `cv.lb t0,12\(12\)'
+.*: Error: illegal operands `cv.lb t1,\(24\),13'
+.*: Error: illegal operands `cv.lb t2,t3\(25\)'
+.*: Error: illegal operands `cv.lb t3,\(75\),t4'
+.*: Error: illegal operands `cv.lbu t4,22\(51\)'
+.*: Error: illegal operands `cv.lbu t5,\(43\),10'
+.*: Error: illegal operands `cv.lbu t6,t5\(61\)'
+.*: Error: illegal operands `cv.lbu t0,\(67\),t6'
+.*: Error: illegal operands `cv.lh t1,19\(13\)'
+.*: Error: illegal operands `cv.lh t2,\(16\),41'
+.*: Error: illegal operands `cv.lh t3,t0\(31\)'
+.*: Error: illegal operands `cv.lh t4,\(37\),t1'
+.*: Error: illegal operands `cv.lhu t5,15\(14\)'
+.*: Error: illegal operands `cv.lhu t6,\(17\),12'
+.*: Error: illegal operands `cv.lhu t0,t2\(14\)'
+.*: Error: illegal operands `cv.lhu t1,\(39\),t3'
+.*: Error: illegal operands `cv.lw t2,4\(24\)'
+.*: Error: illegal operands `cv.lw t3,\(21\),6'
+.*: Error: illegal operands `cv.lw t5,t4\(16\)'
+.*: Error: illegal operands `cv.lw t4,\(47\),t5'
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s
new file mode 100644
index 00000000000..e2e40921f98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s
@@ -0,0 +1,34 @@
+# Base operand must be a register
+target:
+	cv.sb t0, 10(12)
+	cv.sb t1, (24), 20
+	cv.sb t2, t1(25)
+	cv.sb t3, (75), t2
+	cv.sh t4, 30(13)
+	cv.sh t5, (16), 40
+	cv.sh t6, t3(31)
+	cv.sh t0, (37), t4
+	cv.sw t1, 12(51)
+	cv.sw t2, (43), 16
+	cv.sw t3, t5(61)
+	cv.sw t4, (67), t6
+	cv.lb t0, 12(12)
+	cv.lb t1, (24), 13
+	cv.lb t2, t3(25)
+	cv.lb t3, (75), t4
+	cv.lbu t4, 22(51)
+	cv.lbu t5, (43), 10
+	cv.lbu t6, t5(61)
+	cv.lbu t0, (67), t6
+	cv.lh t1, 19(13)
+	cv.lh t2, (16), 41
+	cv.lh t3, t0(31)
+	cv.lh t4, (37), t1
+	cv.lhu t5, 15(14)
+	cv.lhu t6, (17), 12
+	cv.lhu t0, t2(14)
+	cv.lhu t1, (39), t3
+	cv.lw t2, 4(24)
+	cv.lw t3, (21), 6
+	cv.lw t5, t4(16)
+	cv.lw t4, (47), t5
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d b/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d
new file mode 100644
index 00000000000..e6fe3987b99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvmem
+#source: cv-mem-fail-operand-04.s
+#error_output: cv-mem-fail-operand-04.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l b/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l
new file mode 100644
index 00000000000..a6d072291fc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l
@@ -0,0 +1,41 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.lb t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.lb t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.lbu t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.lbu t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.lh t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.lh t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.lhu t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.lhu t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.lw t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.lw t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.lb t2,-3678\(t1\)'
+.*: Error: illegal operands `cv.lb t2,\(t1\),-3678'
+.*: Error: illegal operands `cv.lbu t2,-3678\(t1\)'
+.*: Error: illegal operands `cv.lbu t2,\(t1\),-3678'
+.*: Error: illegal operands `cv.lh t2,-3678\(t1\)'
+.*: Error: illegal operands `cv.lh t2,\(t1\),-3678'
+.*: Error: illegal operands `cv.lhu t2,-3678\(t1\)'
+.*: Error: illegal operands `cv.lhu t2,\(t1\),-3678'
+.*: Error: illegal operands `cv.lw t2,-3678\(t1\)'
+.*: Error: illegal operands `cv.lw t2,\(t1\),-3678'
+.*: Error: illegal operands `cv.lb t2,2048\(t1\)'
+.*: Error: illegal operands `cv.lb t2,\(t1\),2048'
+.*: Error: illegal operands `cv.lbu t2,2048\(t1\)'
+.*: Error: illegal operands `cv.lbu t2,\(t1\),2048'
+.*: Error: illegal operands `cv.lh t2,2048\(t1\)'
+.*: Error: illegal operands `cv.lh t2,\(t1\),2048'
+.*: Error: illegal operands `cv.lhu t2,2048\(t1\)'
+.*: Error: illegal operands `cv.lhu t2,\(t1\),2048'
+.*: Error: illegal operands `cv.lw t2,2048\(t1\)'
+.*: Error: illegal operands `cv.lw t2,\(t1\),2048'
+.*: Error: illegal operands `cv.lb t2,4595\(t1\)'
+.*: Error: illegal operands `cv.lb t2,\(t1\),4595'
+.*: Error: illegal operands `cv.lbu t2,4595\(t1\)'
+.*: Error: illegal operands `cv.lbu t2,\(t1\),4595'
+.*: Error: illegal operands `cv.lh t2,4595\(t1\)'
+.*: Error: illegal operands `cv.lh t2,\(t1\),4595'
+.*: Error: illegal operands `cv.lhu t2,4595\(t1\)'
+.*: Error: illegal operands `cv.lhu t2,\(t1\),4595'
+.*: Error: illegal operands `cv.lw t2,4595\(t1\)'
+.*: Error: illegal operands `cv.lw t2,\(t1\),4595'
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s b/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s
new file mode 100644
index 00000000000..a6307cee49d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s
@@ -0,0 +1,42 @@
+# Offset operand must be in range [-2048, 2047]
+target:
+	cv.lb t2, -2049(t1)
+	cv.lb t2, (t1), -2049
+	cv.lbu t2, -2049(t1)
+	cv.lbu t2, (t1), -2049
+	cv.lh t2, -2049(t1)
+	cv.lh t2, (t1), -2049
+	cv.lhu t2, -2049(t1)
+	cv.lhu t2, (t1), -2049
+	cv.lw t2, -2049(t1)
+	cv.lw t2, (t1), -2049
+	cv.lb t2, -3678(t1)
+	cv.lb t2, (t1), -3678
+	cv.lbu t2, -3678(t1)
+	cv.lbu t2, (t1), -3678
+	cv.lh t2, -3678(t1)
+	cv.lh t2, (t1), -3678
+	cv.lhu t2, -3678(t1)
+	cv.lhu t2, (t1), -3678
+	cv.lw t2, -3678(t1)
+	cv.lw t2, (t1), -3678
+	cv.lb t2, 2048(t1)
+	cv.lb t2, (t1), 2048
+	cv.lbu t2, 2048(t1)
+	cv.lbu t2, (t1), 2048
+	cv.lh t2, 2048(t1)
+	cv.lh t2, (t1), 2048
+	cv.lhu t2, 2048(t1)
+	cv.lhu t2, (t1), 2048
+	cv.lw t2, 2048(t1)
+	cv.lw t2, (t1), 2048
+	cv.lb t2, 4595(t1)
+	cv.lb t2, (t1), 4595
+	cv.lbu t2, 4595(t1)
+	cv.lbu t2, (t1), 4595
+	cv.lh t2, 4595(t1)
+	cv.lh t2, (t1), 4595
+	cv.lhu t2, 4595(t1)
+	cv.lhu t2, (t1), 4595
+	cv.lw t2, 4595(t1)
+	cv.lw t2, (t1), 4595
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d b/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d
new file mode 100644
index 00000000000..c00880fa119
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvmem
+#source: cv-mem-fail-operand-05.s
+#error_output: cv-mem-fail-operand-05.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l b/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l
new file mode 100644
index 00000000000..3069f54cc3a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l
@@ -0,0 +1,25 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sb t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.sb t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.sh t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.sh t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.sw t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.sw t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.sb t2,-3669\(t1\)'
+.*: Error: illegal operands `cv.sb t2,\(t1\),-3669'
+.*: Error: illegal operands `cv.sh t2,-3669\(t1\)'
+.*: Error: illegal operands `cv.sh t2,\(t1\),-3669'
+.*: Error: illegal operands `cv.sw t2,-3669\(t1\)'
+.*: Error: illegal operands `cv.sw t2,\(t1\),-3669'
+.*: Error: illegal operands `cv.sb t2,2048\(t1\)'
+.*: Error: illegal operands `cv.sb t2,\(t1\),2048'
+.*: Error: illegal operands `cv.sh t2,2048\(t1\)'
+.*: Error: illegal operands `cv.sh t2,\(t1\),2048'
+.*: Error: illegal operands `cv.sw t2,2048\(t1\)'
+.*: Error: illegal operands `cv.sw t2,\(t1\),2048'
+.*: Error: illegal operands `cv.sb t2,5341\(t1\)'
+.*: Error: illegal operands `cv.sb t2,\(t1\),5341'
+.*: Error: illegal operands `cv.sh t2,5341\(t1\)'
+.*: Error: illegal operands `cv.sh t2,\(t1\),5341'
+.*: Error: illegal operands `cv.sw t2,5341\(t1\)'
+.*: Error: illegal operands `cv.sw t2,\(t1\),5341'
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s b/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s
new file mode 100644
index 00000000000..33b5883bc64
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s
@@ -0,0 +1,26 @@
+# Offset operand must be in range [-2048, 2047]
+target:
+	cv.sb t2, -2049(t1)
+	cv.sb t2, (t1), -2049
+	cv.sh t2, -2049(t1)
+	cv.sh t2, (t1), -2049
+	cv.sw t2, -2049(t1)
+	cv.sw t2, (t1), -2049
+	cv.sb t2, -3669(t1)
+	cv.sb t2, (t1), -3669
+	cv.sh t2, -3669(t1)
+	cv.sh t2, (t1), -3669
+	cv.sw t2, -3669(t1)
+	cv.sw t2, (t1), -3669
+	cv.sb t2, 2048(t1)
+	cv.sb t2, (t1), 2048
+	cv.sh t2, 2048(t1)
+	cv.sh t2, (t1), 2048
+	cv.sw t2, 2048(t1)
+	cv.sw t2, (t1), 2048
+	cv.sb t2, 5341(t1)
+	cv.sb t2, (t1), 5341
+	cv.sh t2, 5341(t1)
+	cv.sh t2, (t1), 5341
+	cv.sw t2, 5341(t1)
+	cv.sw t2, (t1), 5341
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbpost.d b/gas/testsuite/gas/riscv/cv-mem-lbpost.d
new file mode 100644
index 00000000000..9e3dbd6d345
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lbpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+8003828b[ 	]+cv.lb[ 	]+t0,\(t2\),-2048
+[ 	]+4:[ 	]+00f30e8b[ 	]+cv.lb[ 	]+t4,\(t1\),15
+[ 	]+8:[ 	]+7fff0e0b[ 	]+cv.lb[ 	]+t3,\(t5\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbpost.s b/gas/testsuite/gas/riscv/cv-mem-lbpost.s
new file mode 100644
index 00000000000..a55a414bb31
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lbpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.lb t0, (t2), -2048
+	cv.lb t4, (t1), 15
+	cv.lb t3, (t5), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbrr.d b/gas/testsuite/gas/riscv/cv-mem-lbrr.d
new file mode 100644
index 00000000000..6183ac47a86
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lbrr.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0863b2ab[ 	]+cv.lb[ 	]+t0,t1\(t2\)
+[ 	]+4:[ 	]+09c33eab[ 	]+cv.lb[ 	]+t4,t3\(t1\)
+[ 	]+8:[ 	]+085f3e2b[ 	]+cv.lb[ 	]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbrr.s b/gas/testsuite/gas/riscv/cv-mem-lbrr.s
new file mode 100644
index 00000000000..1cfaf241db3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lbrr.s
@@ -0,0 +1,4 @@
+target:
+	cv.lb t0, t1(t2)
+	cv.lb t4, t3(t1)
+	cv.lb t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbrrpost.d b/gas/testsuite/gas/riscv/cv-mem-lbrrpost.d
new file mode 100644
index 00000000000..839915ea45b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lbrrpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0063b2ab[ 	]+cv.lb[ 	]+t0,\(t2\),t1
+[ 	]+4:[ 	]+01c33eab[ 	]+cv.lb[ 	]+t4,\(t1\),t3
+[ 	]+8:[ 	]+005f3e2b[ 	]+cv.lb[ 	]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbrrpost.s b/gas/testsuite/gas/riscv/cv-mem-lbrrpost.s
new file mode 100644
index 00000000000..48f71ce31f1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lbrrpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.lb t0, (t2), t1
+	cv.lb t4, (t1), t3
+	cv.lb t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbupost.d b/gas/testsuite/gas/riscv/cv-mem-lbupost.d
new file mode 100644
index 00000000000..0db23ad5ecd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lbupost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+8003c28b[ 	]+cv.lbu[ 	]+t0,\(t2\),-2048
+[ 	]+4:[ 	]+00f34e8b[ 	]+cv.lbu[ 	]+t4,\(t1\),15
+[ 	]+8:[ 	]+7fff4e0b[ 	]+cv.lbu[ 	]+t3,\(t5\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbupost.s b/gas/testsuite/gas/riscv/cv-mem-lbupost.s
new file mode 100644
index 00000000000..e4d2ba8f805
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lbupost.s
@@ -0,0 +1,4 @@
+target:
+	cv.lbu t0, (t2), -2048
+	cv.lbu t4, (t1), 15
+	cv.lbu t3, (t5), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lburr.d b/gas/testsuite/gas/riscv/cv-mem-lburr.d
new file mode 100644
index 00000000000..12fe6b07f40
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lburr.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+1863b2ab[ 	]+cv.lbu[ 	]+t0,t1\(t2\)
+[ 	]+4:[ 	]+19c33eab[ 	]+cv.lbu[ 	]+t4,t3\(t1\)
+[ 	]+8:[ 	]+185f3e2b[ 	]+cv.lbu[ 	]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lburr.s b/gas/testsuite/gas/riscv/cv-mem-lburr.s
new file mode 100644
index 00000000000..20982b1b3bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lburr.s
@@ -0,0 +1,4 @@
+target:
+	cv.lbu t0, t1(t2)
+	cv.lbu t4, t3(t1)
+	cv.lbu t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lburrpost.d b/gas/testsuite/gas/riscv/cv-mem-lburrpost.d
new file mode 100644
index 00000000000..468a1df475b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lburrpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+1063b2ab[ 	]+cv.lbu[ 	]+t0,\(t2\),t1
+[ 	]+4:[ 	]+11c33eab[ 	]+cv.lbu[ 	]+t4,\(t1\),t3
+[ 	]+8:[ 	]+105f3e2b[ 	]+cv.lbu[ 	]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lburrpost.s b/gas/testsuite/gas/riscv/cv-mem-lburrpost.s
new file mode 100644
index 00000000000..ea23a2faf88
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lburrpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.lbu t0, (t2), t1
+	cv.lbu t4, (t1), t3
+	cv.lbu t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhpost.d b/gas/testsuite/gas/riscv/cv-mem-lhpost.d
new file mode 100644
index 00000000000..d7ba406fee6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+8003928b[ 	]+cv.lh[ 	]+t0,\(t2\),-2048
+[ 	]+4:[ 	]+00f31e8b[ 	]+cv.lh[ 	]+t4,\(t1\),15
+[ 	]+8:[ 	]+7fff1e0b[ 	]+cv.lh[ 	]+t3,\(t5\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhpost.s b/gas/testsuite/gas/riscv/cv-mem-lhpost.s
new file mode 100644
index 00000000000..39a3b6f75aa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.lh t0, (t2), -2048
+	cv.lh t4, (t1), 15
+	cv.lh t3, (t5), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhrr.d b/gas/testsuite/gas/riscv/cv-mem-lhrr.d
new file mode 100644
index 00000000000..606af406c01
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhrr.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0a63b2ab[ 	]+cv.lh[ 	]+t0,t1\(t2\)
+[ 	]+4:[ 	]+0bc33eab[ 	]+cv.lh[ 	]+t4,t3\(t1\)
+[ 	]+8:[ 	]+0a5f3e2b[ 	]+cv.lh[ 	]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhrr.s b/gas/testsuite/gas/riscv/cv-mem-lhrr.s
new file mode 100644
index 00000000000..fe8f761cfce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhrr.s
@@ -0,0 +1,4 @@
+target:
+	cv.lh t0, t1(t2)
+	cv.lh t4, t3(t1)
+	cv.lh t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhrrpost.d b/gas/testsuite/gas/riscv/cv-mem-lhrrpost.d
new file mode 100644
index 00000000000..d0c9ac0af7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhrrpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0263b2ab[ 	]+cv.lh[ 	]+t0,\(t2\),t1
+[ 	]+4:[ 	]+03c33eab[ 	]+cv.lh[ 	]+t4,\(t1\),t3
+[ 	]+8:[ 	]+025f3e2b[ 	]+cv.lh[ 	]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhrrpost.s b/gas/testsuite/gas/riscv/cv-mem-lhrrpost.s
new file mode 100644
index 00000000000..acfc110b8cf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhrrpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.lh t0, (t2), t1
+	cv.lh t4, (t1), t3
+	cv.lh t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhupost.d b/gas/testsuite/gas/riscv/cv-mem-lhupost.d
new file mode 100644
index 00000000000..56c15ae9fb9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhupost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+8003d28b[ 	]+cv.lhu[ 	]+t0,\(t2\),-2048
+[ 	]+4:[ 	]+00f35e8b[ 	]+cv.lhu[ 	]+t4,\(t1\),15
+[ 	]+8:[ 	]+7fff5e0b[ 	]+cv.lhu[ 	]+t3,\(t5\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhupost.s b/gas/testsuite/gas/riscv/cv-mem-lhupost.s
new file mode 100644
index 00000000000..7efa1ac9aca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhupost.s
@@ -0,0 +1,4 @@
+target:
+	cv.lhu t0, (t2), -2048
+	cv.lhu t4, (t1), 15
+	cv.lhu t3, (t5), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhurr.d b/gas/testsuite/gas/riscv/cv-mem-lhurr.d
new file mode 100644
index 00000000000..9dd81fecc33
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhurr.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+1a63b2ab[ 	]+cv.lhu[ 	]+t0,t1\(t2\)
+[ 	]+4:[ 	]+1bc33eab[ 	]+cv.lhu[ 	]+t4,t3\(t1\)
+[ 	]+8:[ 	]+1a5f3e2b[ 	]+cv.lhu[ 	]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhurr.s b/gas/testsuite/gas/riscv/cv-mem-lhurr.s
new file mode 100644
index 00000000000..91511fd8dfd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhurr.s
@@ -0,0 +1,4 @@
+target:
+	cv.lhu t0, t1(t2)
+	cv.lhu t4, t3(t1)
+	cv.lhu t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhurrpost.d b/gas/testsuite/gas/riscv/cv-mem-lhurrpost.d
new file mode 100644
index 00000000000..66e1a9019af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhurrpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+1263b2ab[ 	]+cv.lhu[ 	]+t0,\(t2\),t1
+[ 	]+4:[ 	]+13c33eab[ 	]+cv.lhu[ 	]+t4,\(t1\),t3
+[ 	]+8:[ 	]+125f3e2b[ 	]+cv.lhu[ 	]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhurrpost.s b/gas/testsuite/gas/riscv/cv-mem-lhurrpost.s
new file mode 100644
index 00000000000..ff5d24ddc69
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lhurrpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.lhu t0, (t2), t1
+	cv.lhu t4, (t1), t3
+	cv.lhu t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwpost.d b/gas/testsuite/gas/riscv/cv-mem-lwpost.d
new file mode 100644
index 00000000000..e0f1c58b102
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lwpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+8003a28b[ 	]+cv.lw[ 	]+t0,\(t2\),-2048
+[ 	]+4:[ 	]+00f32e8b[ 	]+cv.lw[ 	]+t4,\(t1\),15
+[ 	]+8:[ 	]+7fff2e0b[ 	]+cv.lw[ 	]+t3,\(t5\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwpost.s b/gas/testsuite/gas/riscv/cv-mem-lwpost.s
new file mode 100644
index 00000000000..3942d64a465
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lwpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.lw t0, (t2), -2048
+	cv.lw t4, (t1), 15
+	cv.lw t3, (t5), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwrr.d b/gas/testsuite/gas/riscv/cv-mem-lwrr.d
new file mode 100644
index 00000000000..8a72c021902
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lwrr.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0c63b2ab[ 	]+cv.lw[ 	]+t0,t1\(t2\)
+[ 	]+4:[ 	]+0dc33eab[ 	]+cv.lw[ 	]+t4,t3\(t1\)
+[ 	]+8:[ 	]+0c5f3e2b[ 	]+cv.lw[ 	]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwrr.s b/gas/testsuite/gas/riscv/cv-mem-lwrr.s
new file mode 100644
index 00000000000..41be011bc36
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lwrr.s
@@ -0,0 +1,4 @@
+target:
+	cv.lw t0, t1(t2)
+	cv.lw t4, t3(t1)
+	cv.lw t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwrrpost.d b/gas/testsuite/gas/riscv/cv-mem-lwrrpost.d
new file mode 100644
index 00000000000..502bd583d4e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lwrrpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0463b2ab[ 	]+cv.lw[ 	]+t0,\(t2\),t1
+[ 	]+4:[ 	]+05c33eab[ 	]+cv.lw[ 	]+t4,\(t1\),t3
+[ 	]+8:[ 	]+045f3e2b[ 	]+cv.lw[ 	]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwrrpost.s b/gas/testsuite/gas/riscv/cv-mem-lwrrpost.s
new file mode 100644
index 00000000000..5dc9c230ff8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-lwrrpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.lw t0, (t2), t1
+	cv.lw t4, (t1), t3
+	cv.lw t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbpost.d b/gas/testsuite/gas/riscv/cv-mem-sbpost.d
new file mode 100644
index 00000000000..ba240958d6a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-sbpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+81f3002b[ 	]+cv.sb[ 	]+t6,\(t1\),-2048
+[ 	]+4:[ 	]+07d3822b[ 	]+cv.sb[ 	]+t4,\(t2\),100
+[ 	]+8:[ 	]+7fce8fab[ 	]+cv.sb[ 	]+t3,\(t4\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbpost.s b/gas/testsuite/gas/riscv/cv-mem-sbpost.s
new file mode 100644
index 00000000000..1e3ff721468
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-sbpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.sb t6, (t1), -2048
+	cv.sb t4, (t2), 100
+	cv.sb t3, (t4), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbrr.d b/gas/testsuite/gas/riscv/cv-mem-sbrr.d
new file mode 100644
index 00000000000..806508957a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-sbrr.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+2853b32b[ 	]+cv.sb[ 	]+t0,t1\(t2\)
+[ 	]+4:[ 	]+29d33e2b[ 	]+cv.sb[ 	]+t4,t3\(t1\)
+[ 	]+8:[ 	]+29cf32ab[ 	]+cv.sb[ 	]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbrr.s b/gas/testsuite/gas/riscv/cv-mem-sbrr.s
new file mode 100644
index 00000000000..b3a9e5269d9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-sbrr.s
@@ -0,0 +1,4 @@
+target:
+	cv.sb t0, t1(t2)
+	cv.sb t4, t3(t1)
+	cv.sb t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbrrpost.d b/gas/testsuite/gas/riscv/cv-mem-sbrrpost.d
new file mode 100644
index 00000000000..830e4e42c71
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-sbrrpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+2053b32b[ 	]+cv.sb[ 	]+t0,\(t2\),t1
+[ 	]+4:[ 	]+21d33e2b[ 	]+cv.sb[ 	]+t4,\(t1\),t3
+[ 	]+8:[ 	]+21cf32ab[ 	]+cv.sb[ 	]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbrrpost.s b/gas/testsuite/gas/riscv/cv-mem-sbrrpost.s
new file mode 100644
index 00000000000..f4813052e0d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-sbrrpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.sb t0, (t2), t1
+	cv.sb t4, (t1), t3
+	cv.sb t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-shpost.d b/gas/testsuite/gas/riscv/cv-mem-shpost.d
new file mode 100644
index 00000000000..2fc477518cd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-shpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+81cf102b[ 	]+cv.sh[ 	]+t3,\(t5\),-2048
+[ 	]+4:[ 	]+026f9e2b[ 	]+cv.sh[ 	]+t1,\(t6\),60
+[ 	]+8:[ 	]+7e7e9fab[ 	]+cv.sh[ 	]+t2,\(t4\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-shpost.s b/gas/testsuite/gas/riscv/cv-mem-shpost.s
new file mode 100644
index 00000000000..d7ab1722d07
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-shpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.sh t3, (t5), -2048
+	cv.sh t1, (t6), 60
+	cv.sh t2, (t4), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-shrr.d b/gas/testsuite/gas/riscv/cv-mem-shrr.d
new file mode 100644
index 00000000000..0e88d9d320c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-shrr.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+2a6ebe2b[ 	]+cv.sh[ 	]+t1,t3\(t4\)
+[ 	]+4:[ 	]+2bd333ab[ 	]+cv.sh[ 	]+t4,t2\(t1\)
+[ 	]+8:[ 	]+2bf3bf2b[ 	]+cv.sh[ 	]+t6,t5\(t2\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-shrr.s b/gas/testsuite/gas/riscv/cv-mem-shrr.s
new file mode 100644
index 00000000000..2f5ee9859ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-shrr.s
@@ -0,0 +1,4 @@
+target:
+	cv.sh t1, t3(t4)
+	cv.sh t4, t2(t1)
+	cv.sh t6, t5(t2)
diff --git a/gas/testsuite/gas/riscv/cv-mem-shrrpost.d b/gas/testsuite/gas/riscv/cv-mem-shrrpost.d
new file mode 100644
index 00000000000..f43ceddd64e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-shrrpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+2263bfab[ 	]+cv.sh[ 	]+t1,\(t2\),t6
+[ 	]+4:[ 	]+22733f2b[ 	]+cv.sh[ 	]+t2,\(t1\),t5
+[ 	]+8:[ 	]+23ee3eab[ 	]+cv.sh[ 	]+t5,\(t3\),t4
diff --git a/gas/testsuite/gas/riscv/cv-mem-shrrpost.s b/gas/testsuite/gas/riscv/cv-mem-shrrpost.s
new file mode 100644
index 00000000000..922a94f7314
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-shrrpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.sh t1, (t2), t6
+	cv.sh t2, (t1), t5
+	cv.sh t5, (t3), t4
diff --git a/gas/testsuite/gas/riscv/cv-mem-swpost.d b/gas/testsuite/gas/riscv/cv-mem-swpost.d
new file mode 100644
index 00000000000..2a5fee9833a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-swpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+806ea02b[ 	]+cv.sw[ 	]+t1,\(t4\),-2048
+[ 	]+4:[ 	]+07cf222b[ 	]+cv.sw[ 	]+t3,\(t5\),100
+[ 	]+8:[ 	]+7e63afab[ 	]+cv.sw[ 	]+t1,\(t2\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-swpost.s b/gas/testsuite/gas/riscv/cv-mem-swpost.s
new file mode 100644
index 00000000000..7dd827ac111
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-swpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.sw t1, (t4), -2048
+	cv.sw t3, (t5), 100
+	cv.sw t1, (t2), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-swrr.d b/gas/testsuite/gas/riscv/cv-mem-swrr.d
new file mode 100644
index 00000000000..5bc0708cbb8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-swrr.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+2c6eb3ab[ 	]+cv.sw[ 	]+t1,t2\(t4\)
+[ 	]+4:[ 	]+2dcf33ab[ 	]+cv.sw[ 	]+t3,t2\(t5\)
+[ 	]+8:[ 	]+2c63bf2b[ 	]+cv.sw[ 	]+t1,t5\(t2\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-swrr.s b/gas/testsuite/gas/riscv/cv-mem-swrr.s
new file mode 100644
index 00000000000..652ac9a46f2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-swrr.s
@@ -0,0 +1,4 @@
+target:
+	cv.sw t1, t2(t4)
+	cv.sw t3, t2(t5)
+	cv.sw t1, t5(t2)
diff --git a/gas/testsuite/gas/riscv/cv-mem-swrrpost.d b/gas/testsuite/gas/riscv/cv-mem-swrrpost.d
new file mode 100644
index 00000000000..d3b338563bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-swrrpost.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+25e3bfab[ 	]+cv.sw[ 	]+t5,\(t2\),t6
+[ 	]+4:[ 	]+25ceb32b[ 	]+cv.sw[ 	]+t3,\(t4\),t1
+[ 	]+8:[ 	]+24733eab[ 	]+cv.sw[ 	]+t2,\(t1\),t4
diff --git a/gas/testsuite/gas/riscv/cv-mem-swrrpost.s b/gas/testsuite/gas/riscv/cv-mem-swrrpost.s
new file mode 100644
index 00000000000..6210e1e2628
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mem-swrrpost.s
@@ -0,0 +1,4 @@
+target:
+	cv.sw t5, (t2), t6
+	cv.sw t3, (t4), t1
+	cv.sw t2, (t1), t4
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index aa02dcf2f76..9e75bd7b434 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2432,6 +2432,37 @@
 #define MASK_CV_BNEIMM 0x707f
 #define MATCH_CV_BEQIMM 0x600b
 #define MASK_CV_BEQIMM 0x707f
+/* Vendor-specific (CORE-V) Xcvmem instructions. */
+#define MATCH_CV_LBPOST    0xb
+#define MATCH_CV_LBUPOST   0x400b
+#define MATCH_CV_LHPOST    0x100b
+#define MATCH_CV_LHUPOST   0x500b
+#define MATCH_CV_LWPOST    0x200b
+#define MATCH_CV_LBRRPOST  0x302b
+#define MATCH_CV_LBURRPOST 0x1000302b
+#define MATCH_CV_LHRRPOST  0x200302b
+#define MATCH_CV_LHURRPOST 0x1200302b
+#define MATCH_CV_LWRRPOST  0x400302b
+#define MATCH_CV_LBRR      0x800302b
+#define MATCH_CV_LBURR     0x1800302b
+#define MATCH_CV_LHRR      0xa00302b
+#define MATCH_CV_LHURR     0x1a00302b
+#define MATCH_CV_LWRR      0xc00302b
+#define MASK_CV_LPOST      0x707f
+#define MASK_CV_LRRPOST    0xfe00707f
+#define MASK_CV_LRR        0xfe00707f
+#define MATCH_CV_SBPOST   0x2b
+#define MATCH_CV_SHPOST   0x102b
+#define MATCH_CV_SWPOST   0x202b
+#define MATCH_CV_SBRRPOST 0x2000302b
+#define MATCH_CV_SHRRPOST 0x2200302b
+#define MATCH_CV_SWRRPOST 0x2400302b
+#define MATCH_CV_SBRR     0x2800302b
+#define MATCH_CV_SHRR     0x2a00302b
+#define MATCH_CV_SWRR     0x2c00302b
+#define MASK_CV_SPOST     0x707f
+#define MASK_CV_SRRPOST   0xfe00707f
+#define MASK_CV_SRR       0xfe00707f
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 #define MATCH_TH_ADDSL 0x0000100b
 #define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index c579ba85121..8cfbb893377 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -460,6 +460,7 @@ enum riscv_insn_class
   INSN_CLASS_XCVALU,
   INSN_CLASS_XCVELW,
   INSN_CLASS_XCVBI,
+  INSN_CLASS_XCVMEM,
   INSN_CLASS_XTHEADBA,
   INSN_CLASS_XTHEADBB,
   INSN_CLASS_XTHEADBS,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c3c809f4545..df7374afa66 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2107,6 +2107,32 @@ const struct riscv_opcode riscv_opcodes[] =
 {"cv.beqimm", 0, INSN_CLASS_XCVBI, "s,Xc4,p", MATCH_CV_BEQIMM, MASK_CV_BEQIMM, match_opcode, 0},
 {"cv.bneimm", 0, INSN_CLASS_XCVBI, "s,Xc4,p", MATCH_CV_BNEIMM, MASK_CV_BNEIMM, match_opcode, 0},
 
+/* Vendor-specific (CORE-V) Xcvmem instructions.  */
+{"cv.lb", 0, INSN_CLASS_XCVMEM, "d,(s),o", MATCH_CV_LBPOST,    MASK_CV_LPOST,    match_opcode, 0},
+{"cv.lb", 0, INSN_CLASS_XCVMEM, "d,(s),t", MATCH_CV_LBRRPOST,  MASK_CV_LRRPOST,  match_opcode, 0},
+{"cv.lb", 0, INSN_CLASS_XCVMEM, "d,t(s)",  MATCH_CV_LBRR,      MASK_CV_LRR,      match_opcode, 0},
+{"cv.lbu",0, INSN_CLASS_XCVMEM, "d,(s),o", MATCH_CV_LBUPOST,   MASK_CV_LPOST,    match_opcode, 0},
+{"cv.lbu",0, INSN_CLASS_XCVMEM, "d,(s),t", MATCH_CV_LBURRPOST, MASK_CV_LRRPOST,  match_opcode, 0},
+{"cv.lbu",0, INSN_CLASS_XCVMEM, "d,t(s)",  MATCH_CV_LBURR,     MASK_CV_LRR,      match_opcode, 0},
+{"cv.lh", 0, INSN_CLASS_XCVMEM, "d,(s),o", MATCH_CV_LHPOST,    MASK_CV_LPOST,    match_opcode, 0},
+{"cv.lh", 0, INSN_CLASS_XCVMEM, "d,(s),t", MATCH_CV_LHRRPOST,  MASK_CV_LRRPOST,  match_opcode, 0},
+{"cv.lh", 0, INSN_CLASS_XCVMEM, "d,t(s)",  MATCH_CV_LHRR,      MASK_CV_LRR,      match_opcode, 0},
+{"cv.lhu",0, INSN_CLASS_XCVMEM, "d,(s),o", MATCH_CV_LHUPOST,   MASK_CV_LPOST,    match_opcode, 0},
+{"cv.lhu",0, INSN_CLASS_XCVMEM, "d,(s),t", MATCH_CV_LHURRPOST, MASK_CV_LRRPOST,  match_opcode, 0},
+{"cv.lhu",0, INSN_CLASS_XCVMEM, "d,t(s)",  MATCH_CV_LHURR,     MASK_CV_LRR,      match_opcode, 0},
+{"cv.lw", 0, INSN_CLASS_XCVMEM, "d,(s),o", MATCH_CV_LWPOST,    MASK_CV_LPOST,    match_opcode, 0},
+{"cv.lw", 0, INSN_CLASS_XCVMEM, "d,(s),t", MATCH_CV_LWRRPOST,  MASK_CV_LRRPOST,  match_opcode, 0},
+{"cv.lw", 0, INSN_CLASS_XCVMEM, "d,t(s)",  MATCH_CV_LWRR,      MASK_CV_LRR,      match_opcode, 0},
+{"cv.sb", 0, INSN_CLASS_XCVMEM, "t,(s),q", MATCH_CV_SBPOST,    MASK_CV_SPOST,    match_opcode, 0},
+{"cv.sb", 0, INSN_CLASS_XCVMEM, "t,d(s)",  MATCH_CV_SBRR,      MASK_CV_SRR,      match_opcode, 0},
+{"cv.sb", 0, INSN_CLASS_XCVMEM, "t,(s),d", MATCH_CV_SBRRPOST,  MASK_CV_SRRPOST,  match_opcode, 0},
+{"cv.sh", 0, INSN_CLASS_XCVMEM, "t,(s),q", MATCH_CV_SHPOST,    MASK_CV_SPOST,    match_opcode, 0},
+{"cv.sh", 0, INSN_CLASS_XCVMEM, "t,d(s)",  MATCH_CV_SHRR,      MASK_CV_SRR,      match_opcode, 0},
+{"cv.sh", 0, INSN_CLASS_XCVMEM, "t,(s),d", MATCH_CV_SHRRPOST,  MASK_CV_SRRPOST,  match_opcode, 0},
+{"cv.sw", 0, INSN_CLASS_XCVMEM, "t,(s),q", MATCH_CV_SWPOST,    MASK_CV_SPOST,    match_opcode, 0},
+{"cv.sw", 0, INSN_CLASS_XCVMEM, "t,d(s)",  MATCH_CV_SWRR,      MASK_CV_SRR,      match_opcode, 0},
+{"cv.sw", 0, INSN_CLASS_XCVMEM, "t,(s),d", MATCH_CV_SWRRPOST,  MASK_CV_SRRPOST,  match_opcode, 0},
+
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 {"th.addsl",    0, INSN_CLASS_XTHEADBA,    "d,s,t,Xtu2@25",   MATCH_TH_ADDSL,    MASK_TH_ADDSL,    match_opcode, 0},
 
-- 
2.34.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P
  2023-11-13 12:14 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
@ 2023-11-21  4:20   ` Nelson Chu
  0 siblings, 0 replies; 5+ messages in thread
From: Nelson Chu @ 2023-11-21  4:20 UTC (permalink / raw)
  To: Mary Bennett; +Cc: binutils

[-- Attachment #1: Type: text/plain, Size: 18251 bytes --]

On Mon, Nov 13, 2023 at 8:15 PM Mary Bennett <mary.bennett@embecosm.com>
wrote:

> Spec:
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
>
> Contributors:
>   Mary Bennett <mary.bennett@embecosm.com>
>   Nandni Jamnadas <nandni.jamnadas@embecosm.com>
>   Pietra Ferreira <pietra.ferreira@embecosm.com>
>   Charlie Keaney
>   Jessica Mills
>   Craig Blackmore <craig.blackmore@embecosm.com>
>   Simon Cook <simon.cook@embecosm.com>
>   Jeremy Bennett <jeremy.bennett@embecosm.com>
>   Helene Chelin <helene.chelin@embecosm.com>
>
> bfd/ChangeLog:
>
>         * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw`
>           instruction class.
>         (riscv_multi_subset_supports_ext): Likewise.
>
> gas/ChangeLog:
>
>         * doc/c-riscv.texi: Note XCVelw as an additional ISA extension
>           for CORE-V.
>         * testsuite/gas/riscv/cv-elw-fail.d: New test.
>         * testsuite/gas/riscv/cv-elw-fail.l: New test.
>         * testsuite/gas/riscv/cv-elw-fail.s: New test.
>         * testsuite/gas/riscv/cv-elw-fail-march.d: New test.
>         * testsuite/gas/riscv/cv-elw-fail-march.l: New test.
>         * testsuite/gas/riscv/cv-elw-fail-march.s: New test.
>         * testsuite/gas/riscv/cv-elw-pass.d: New test.
>         * testsuite/gas/riscv/cv-elw-pass.s: New test.
>
> opcodes/ChangeLog:
>
>         * riscv-opc.c: (riscv_opcode) Add event load instructions.
>
> include/ChangeLog:
>
>         * opcode/riscv-opc.h: Add corresponding MATCH and MASK
>           instruction opcode macros.
>         * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
> ---
>  bfd/elfxx-riscv.c                           |  5 +++
>  gas/doc/c-riscv.texi                        |  5 +++
>  gas/testsuite/gas/riscv/cv-elw-fail-march.d |  3 ++
>  gas/testsuite/gas/riscv/cv-elw-fail-march.l | 38 +++++++++++++++++
>  gas/testsuite/gas/riscv/cv-elw-fail-march.s | 42 +++++++++++++++++++
>  gas/testsuite/gas/riscv/cv-elw-fail.d       |  3 ++
>  gas/testsuite/gas/riscv/cv-elw-fail.l       |  5 +++
>  gas/testsuite/gas/riscv/cv-elw-fail.s       |  8 ++++
>  gas/testsuite/gas/riscv/cv-elw-pass.d       | 46 +++++++++++++++++++++
>  gas/testsuite/gas/riscv/cv-elw-pass.s       | 42 +++++++++++++++++++
>  include/opcode/riscv-opc.h                  |  3 ++
>  include/opcode/riscv.h                      |  1 +
>  opcodes/riscv-opc.c                         |  3 ++
>  13 files changed, 204 insertions(+)
>  create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.d
>  create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.l
>  create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.s
>  create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.d
>  create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.l
>  create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.s
>  create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.d
>  create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index c9acf124626..545588b5afd 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1361,6 +1361,7 @@ static struct riscv_supported_ext
> riscv_supported_vendor_x_ext[] =
>  {
>    {"xcvmac",           ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>    {"xcvalu",           ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
> +  {"xcvelw",           ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>    {"xtheadba",         ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>    {"xtheadbb",         ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>    {"xtheadbs",         ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
> @@ -2556,6 +2557,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
>        return riscv_subset_supports (rps, "xcvmac");
>      case INSN_CLASS_XCVALU:
>        return riscv_subset_supports (rps, "xcvalu");
> +    case INSN_CLASS_XCVELW:
> +      return riscv_subset_supports (rps, "xcvelw");
>      case INSN_CLASS_XTHEADBA:
>        return riscv_subset_supports (rps, "xtheadba");
>      case INSN_CLASS_XTHEADBB:
> @@ -2800,6 +2803,8 @@ riscv_multi_subset_supports_ext
> (riscv_parse_subset_t *rps,
>        return "xcvmac";
>      case INSN_CLASS_XCVALU:
>        return "xcvalu";
> +    case INSN_CLASS_XCVELW:
> +      return "xcvelw";
>      case INSN_CLASS_XTHEADBA:
>        return "xtheadba";
>      case INSN_CLASS_XTHEADBB:
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index b23504648bd..8d2b8b2d4bb 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -754,6 +754,11 @@ The Xcvalu extension provides instructions for
> general ALU operations.
>
>  It is documented in @url{
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
> }
>
> +@item Xcvelw
> +The Xcvelw extension provides instructions for event load word operations.
> +
> +It is documented in @url{
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
> }
> +
>  @item XTheadBa
>  The XTheadBa extension provides instructions for address calculations.
>
> diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.d
> b/gas/testsuite/gas/riscv/cv-elw-fail-march.d
> new file mode 100644
> index 00000000000..5a3a6dba66b
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i
> +#source: cv-elw-fail-march.s
> +#error_output: cv-elw-fail-march.l
> diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.l
> b/gas/testsuite/gas/riscv/cv-elw-fail-march.l
> new file mode 100644
> index 00000000000..760a71b3827
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.l
> @@ -0,0 +1,38 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `cv.elw x5,-2048\(x6\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x5,0\(x6\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x5,20\(x6\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x5,2047\(x6\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x31,2047\(x31\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x0,0\(x0\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x1,1024\(x1\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x2,1024\(x2\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x3,1024\(x3\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x4,1024\(x4\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x5,1024\(x5\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x6,1024\(x6\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x7,1024\(x7\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x8,1024\(x8\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x9,1024\(x9\)', extension `xcvelw'
> required
> +.*: Error: unrecognized opcode `cv.elw x10,1024\(x10\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x11,1024\(x11\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x12,1024\(x12\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x13,1024\(x13\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x14,1024\(x14\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x15,1024\(x15\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x16,1024\(x16\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x17,1024\(x17\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x18,1024\(x18\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x19,1024\(x19\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x20,1024\(x20\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x21,1024\(x21\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x22,1024\(x22\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x23,1024\(x23\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x24,1024\(x24\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x25,1024\(x25\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x26,1024\(x26\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x27,1024\(x27\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x28,1024\(x28\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x29,1024\(x29\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x30,1024\(x30\)', extension
> `xcvelw' required
> +.*: Error: unrecognized opcode `cv.elw x31,1024\(x31\)', extension
> `xcvelw' required
> diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.s
> b/gas/testsuite/gas/riscv/cv-elw-fail-march.s
> new file mode 100644
> index 00000000000..8728f1cbdee
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.s
> @@ -0,0 +1,42 @@
> +target:
> +    # Immediate Boundary Tests
> +    cv.elw x5,-2048(x6)
> +    cv.elw x5,0(x6)
> +    cv.elw x5,20(x6)
> +    cv.elw x5,2047(x6)
> +    cv.elw x31,2047(x31)
> +
> +    # Register Boundary Tests
> +    cv.elw x0,0(x0)
> +    cv.elw x1,1024(x1)
> +    cv.elw x2,1024(x2)
> +    cv.elw x3,1024(x3)
> +    cv.elw x4,1024(x4)
> +    cv.elw x5,1024(x5)
> +    cv.elw x6,1024(x6)
> +    cv.elw x7,1024(x7)
> +    cv.elw x8,1024(x8)
> +    cv.elw x9,1024(x9)
> +    cv.elw x10,1024(x10)
> +    cv.elw x11,1024(x11)
> +    cv.elw x12,1024(x12)
> +    cv.elw x13,1024(x13)
> +    cv.elw x14,1024(x14)
> +    cv.elw x15,1024(x15)
> +    cv.elw x16,1024(x16)
> +    cv.elw x17,1024(x17)
> +    cv.elw x18,1024(x18)
> +    cv.elw x19,1024(x19)
> +    cv.elw x20,1024(x20)
> +    cv.elw x21,1024(x21)
> +    cv.elw x22,1024(x22)
> +    cv.elw x23,1024(x23)
> +    cv.elw x24,1024(x24)
> +    cv.elw x25,1024(x25)
> +    cv.elw x26,1024(x26)
> +    cv.elw x27,1024(x27)
> +    cv.elw x28,1024(x28)
> +    cv.elw x29,1024(x29)
> +    cv.elw x30,1024(x30)
> +    cv.elw x31,1024(x31)
> +
> \ No newline at end of file
> diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.d
> b/gas/testsuite/gas/riscv/cv-elw-fail.d
> new file mode 100644
> index 00000000000..d7fd1d1a6cb
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-elw-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvelw
> +#source: cv-elw-fail.s
> +#error_output: cv-elw-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.l
> b/gas/testsuite/gas/riscv/cv-elw-fail.l
> new file mode 100644
> index 00000000000..4d3f15ba138
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-elw-fail.l
> @@ -0,0 +1,5 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.elw x5,-2049\(x6\)'
> +.*: Error: illegal operands `cv.elw x5,2048\(x6\)'
> +.*: Error: illegal operands `cv.elw x-1,1024\(x-1\)'
> +.*: Error: illegal operands `cv.elw x32,1024\(x32\)'
> \ No newline at end of file
> diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.s
> b/gas/testsuite/gas/riscv/cv-elw-fail.s
> new file mode 100644
> index 00000000000..4ce122297f4
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-elw-fail.s
> @@ -0,0 +1,8 @@
> +target:
> +    # Immediate Boundary Tests
> +    cv.elw x5,-2049(x6)
> +    cv.elw x5,2048(x6)
> +
> +    # Register Boundary Tests
> +    cv.elw x-1,1024(x-1)
> +    cv.elw x32,1024(x32)
> diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.d
> b/gas/testsuite/gas/riscv/cv-elw-pass.d
> new file mode 100644
> index 00000000000..fed2c870e7e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-elw-pass.d
> @@ -0,0 +1,46 @@
> +#as: -march=rv32i_xcvelw
> +#source: cv-elw-pass.s
> +#objdump: -d
> +
> +.*:[   ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[  ]+0:[       ]+80036283[     ]+cv.elw[       ]+t0,-2048\(t1\)
> +[  ]+4:[       ]+00036283[     ]+cv.elw[       ]+t0,0\(t1\)
> +[  ]+8:[       ]+01436283[     ]+cv.elw[       ]+t0,20\(t1\)
> +[  ]+c:[       ]+7ff36283[     ]+cv.elw[       ]+t0,2047\(t1\)
> +[  ]+10:[      ]+7fffef83[     ]+cv.elw[       ]+t6,2047\(t6\)
> +[  ]+14:[      ]+00006003[     ]+cv.elw[       ]+zero,0\(zero\) # 0
> <target>
> +[  ]+18:[      ]+4000e083[     ]+cv.elw[       ]+ra,1024\(ra\)
> +[  ]+1c:[      ]+40016103[     ]+cv.elw[       ]+sp,1024\(sp\)
> +[  ]+20:[      ]+4001e183[     ]+cv.elw[       ]+gp,1024\(gp\)
> +[  ]+24:[      ]+40026203[     ]+cv.elw[       ]+tp,1024\(tp\) # 400
> <target\+0x400>
> +[  ]+28:[      ]+4002e283[     ]+cv.elw[       ]+t0,1024\(t0\)
> +[  ]+2c:[      ]+40036303[     ]+cv.elw[       ]+t1,1024\(t1\)
> +[  ]+30:[      ]+4003e383[     ]+cv.elw[       ]+t2,1024\(t2\)
> +[  ]+34:[      ]+40046403[     ]+cv.elw[       ]+s0,1024\(s0\)
> +[  ]+38:[      ]+4004e483[     ]+cv.elw[       ]+s1,1024\(s1\)
> +[  ]+3c:[      ]+40056503[     ]+cv.elw[       ]+a0,1024\(a0\)
> +[  ]+40:[      ]+4005e583[     ]+cv.elw[       ]+a1,1024\(a1\)
> +[  ]+44:[      ]+40066603[     ]+cv.elw[       ]+a2,1024\(a2\)
> +[  ]+48:[      ]+4006e683[     ]+cv.elw[       ]+a3,1024\(a3\)
> +[  ]+4c:[      ]+40076703[     ]+cv.elw[       ]+a4,1024\(a4\)
> +[  ]+50:[      ]+4007e783[     ]+cv.elw[       ]+a5,1024\(a5\)
> +[  ]+54:[      ]+40086803[     ]+cv.elw[       ]+a6,1024\(a6\)
> +[  ]+58:[      ]+4008e883[     ]+cv.elw[       ]+a7,1024\(a7\)
> +[  ]+5c:[      ]+40096903[     ]+cv.elw[       ]+s2,1024\(s2\)
> +[  ]+60:[      ]+4009e983[     ]+cv.elw[       ]+s3,1024\(s3\)
> +[  ]+64:[      ]+400a6a03[     ]+cv.elw[       ]+s4,1024\(s4\)
> +[  ]+68:[      ]+400aea83[     ]+cv.elw[       ]+s5,1024\(s5\)
> +[  ]+6c:[      ]+400b6b03[     ]+cv.elw[       ]+s6,1024\(s6\)
> +[  ]+70:[      ]+400beb83[     ]+cv.elw[       ]+s7,1024\(s7\)
> +[  ]+74:[      ]+400c6c03[     ]+cv.elw[       ]+s8,1024\(s8\)
> +[  ]+78:[      ]+400cec83[     ]+cv.elw[       ]+s9,1024\(s9\)
> +[  ]+7c:[      ]+400d6d03[     ]+cv.elw[       ]+s10,1024\(s10\)
> +[  ]+80:[      ]+400ded83[     ]+cv.elw[       ]+s11,1024\(s11\)
> +[  ]+84:[      ]+400e6e03[     ]+cv.elw[       ]+t3,1024\(t3\)
> +[  ]+88:[      ]+400eee83[     ]+cv.elw[       ]+t4,1024\(t4\)
> +[  ]+8c:[      ]+400f6f03[     ]+cv.elw[       ]+t5,1024\(t5\)
> +[  ]+90:[      ]+400fef83[     ]+cv.elw[       ]+t6,1024\(t6\)
> diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.s
> b/gas/testsuite/gas/riscv/cv-elw-pass.s
> new file mode 100644
> index 00000000000..ed6d1882f06
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-elw-pass.s
> @@ -0,0 +1,42 @@
> +target:
> +    # Immediate Boundary Tests
> +    cv.elw x5,-2048(x6)
> +    cv.elw x5,0(x6)
> +    cv.elw x5,20(x6)
> +    cv.elw x5,2047(x6)
> +    cv.elw x31,2047(x31)
> +
> +    # Register Boundary Tests
> +    cv.elw x0,0(x0)
> +    cv.elw x1,1024(x1)
> +    cv.elw x2,1024(x2)
> +    cv.elw x3,1024(x3)
> +    cv.elw x4,1024(x4)
> +    cv.elw x5,1024(x5)
> +    cv.elw x6,1024(x6)
> +    cv.elw x7,1024(x7)
> +    cv.elw x8,1024(x8)
> +    cv.elw x9,1024(x9)
> +    cv.elw x10,1024(x10)
> +    cv.elw x11,1024(x11)
> +    cv.elw x12,1024(x12)
> +    cv.elw x13,1024(x13)
> +    cv.elw x14,1024(x14)
> +    cv.elw x15,1024(x15)
> +    cv.elw x16,1024(x16)
> +    cv.elw x17,1024(x17)
> +    cv.elw x18,1024(x18)
> +    cv.elw x19,1024(x19)
> +    cv.elw x20,1024(x20)
> +    cv.elw x21,1024(x21)
> +    cv.elw x22,1024(x22)
> +    cv.elw x23,1024(x23)
> +    cv.elw x24,1024(x24)
> +    cv.elw x25,1024(x25)
> +    cv.elw x26,1024(x26)
> +    cv.elw x27,1024(x27)
> +    cv.elw x28,1024(x28)
> +    cv.elw x29,1024(x29)
> +    cv.elw x30,1024(x30)
> +    cv.elw x31,1024(x31)
> +
> \ No newline at end of file
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 24217062edc..3d521703b98 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2424,6 +2424,9 @@
>  #define MASK_CV_SUBRN 0xc000707f
>  #define MATCH_CV_SUBURN 0xc000305b
>  #define MASK_CV_SUBURN 0xc000707f
> +/* Vendor-specific (CORE-V) Xcvelw instructions. */
> +#define MATCH_CV_ELW 0x6003
> +#define MASK_CV_ELW 0x707f
>

Seems like this encoding is the same as standard 64-bit LWU.  So,
1. Could we just use MATCH/MASK_LWU to replace MATCH/MASK_CV_ELW?
2. Does that mean even if Xcvelw is enabled, under rv64 the cv.elw will
still be lwu?

Thanks
Nelson


>  /* Vendor-specific (T-Head) XTheadBa instructions.  */
>  #define MATCH_TH_ADDSL 0x0000100b
>  #define MASK_TH_ADDSL 0xf800707f
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 710a9b73189..df131aa3680 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -455,6 +455,7 @@ enum riscv_insn_class
>    INSN_CLASS_H,
>    INSN_CLASS_XCVMAC,
>    INSN_CLASS_XCVALU,
> +  INSN_CLASS_XCVELW,
>    INSN_CLASS_XTHEADBA,
>    INSN_CLASS_XTHEADBB,
>    INSN_CLASS_XTHEADBS,
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 72d727cd77e..c3fb20ec345 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -2100,6 +2100,9 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"cv.subrnr",  0, INSN_CLASS_XCVALU, "d,s,t",     MATCH_CV_SUBRNR,
> MASK_CV_SUBRNR, match_opcode, 0},
>  {"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t",     MATCH_CV_SUBURNR,
> MASK_CV_SUBURNR, match_opcode, 0},
>
> +/* Vendor-specific (CORE-V) Xcvelw instructions.  */
> +{"cv.elw", 0, INSN_CLASS_XCVELW, "d,o(s)",  MATCH_CV_ELW, MASK_CV_ELW,
> match_opcode, 0},
> +
>  /* Vendor-specific (T-Head) XTheadBa instructions.  */
>  {"th.addsl",    0, INSN_CLASS_XTHEADBA,    "d,s,t,Xtu2@25",
>  MATCH_TH_ADDSL,    MASK_TH_ADDSL,    match_opcode, 0},
>
> --
> 2.34.1
>
>

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2023-11-21  4:20 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-13 12:14 [PATCH 0/3] RISC-V: Support CORE-V XCVELW, XCVBI, and XCVMEM extensions Mary Bennett
2023-11-13 12:14 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-21  4:20   ` Nelson Chu
2023-11-13 12:14 ` [PATCH 2/3] RISC-V: Add support for XCVbi " Mary Bennett
2023-11-13 12:14 ` [PATCH 3/3] RISC-V: Add support for XCVmem " Mary Bennett

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