[PATCH 1/8] aarch64: rcpc3: Add +rcpc3 architectural feature support flag

[Victor Do Nascimento <victor.donascimento@arm.com>]

Indicating the presence of the Armv8.2-a feature adding further
support for the Release Consistency Model, the `+rcpc3' architectural
extension flag is added to the list of possible `-march' options in
Binutils, together with the necessary macro for encoding rcpc3
instructions.
---
 gas/config/tc-aarch64.c  | 1 +
 gas/doc/c-aarch64.texi   | 3 +++
 include/opcode/aarch64.h | 2 ++
 opcodes/aarch64-tbl.h    | 4 ++++
 4 files changed, 10 insertions(+)

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 7eb732adbb6..66df5b863dd 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10335,6 +10335,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"ite",		AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
   {"d128",		AARCH64_FEATURE (D128),
 			AARCH64_FEATURE (LSE128)},
+  {"rcpc3",		AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index ccf18ee2661..61044b78190 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -276,6 +276,9 @@ automatically cause those extensions to be disabled.
  @tab Enable TRCIT instruction.
 @item @code{d128} @tab Armv9.4-A @tab No
  @tab Enable the 128-bit Page Descriptor Extension.  This implies @code{lse128}.
+@item @code{rcpc3} @tab Armv9.4-A @tab No
+ @tab Enable the rcpc3 additional Support for Release Consistency Model
+ Extension.  This implies @code{rcpc2}.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9d64d7a0ebe..8ac48edf6a8 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -222,6 +222,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_PMUv3_ICNTR,
   /* Performance Monitors Synchronous-Exception-Based Event Extension.  */
   AARCH64_FEATURE_SEBEP,
+  /* RCPC3 instructions.  */
+  AARCH64_FEATURE_RCPC3,
   AARCH64_NUM_FEATURES
 };
 
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 0cf195d0321..708459e287d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2608,6 +2608,9 @@ static const aarch64_feature_set aarch64_feature_the =
   AARCH64_FEATURE (THE);
 static const aarch64_feature_set aarch64_feature_d128_the =
   AARCH64_FEATURES (2, D128, THE);
+static const aarch64_feature_set aarch64_feature_rcpc3 =
+  AARCH64_FEATURE (RCPC3);
+
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -2670,6 +2673,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
 #define D128	  &aarch64_feature_d128
 #define THE	  &aarch64_feature_the
 #define D128_THE  &aarch64_feature_d128_the
+#define RCPC3	  &aarch64_feature_rcpc3
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
-- 
2.42.0