From: Victor Do Nascimento <victor.donascimento@arm.com>
To: <binutils@sourceware.org>
Cc: <richard.earnshaw@arm.com>, <nickc@redhat.com>,
Victor Do Nascimento <victor.donascimento@arm.com>
Subject: [PATCH 4/8] aarch64: rcpc3: New RCPC3_ADDR operand types
Date: Fri, 12 Jan 2024 16:56:18 +0000 [thread overview]
Message-ID: <20240112165637.2522719-5-victor.donascimento@arm.com> (raw)
In-Reply-To: <20240112165637.2522719-1-victor.donascimento@arm.com>
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
- AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
- AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
---
gas/config/tc-aarch64.c | 65 ++++++++++++++++++++++++++++++++++++++++
include/opcode/aarch64.h | 5 ++++
opcodes/aarch64-opc.c | 5 ++++
opcodes/aarch64-tbl.h | 16 +++++++++-
4 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 66df5b863dd..9a3480b565b 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7263,7 +7263,52 @@ parse_operands (char *str, const aarch64_opcode *opcode)
inst.reloc.pc_rel = 1;
}
break;
+ case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_POSTIND:
+ po_misc_or_fail (parse_address (&str, info));
+ if (info->addr.writeback)
+ {
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+ }
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
+ {
+ char *start = str;
+ /* First use the normal address-parsing routines, to get
+ the usual syntax errors. */
+ po_misc_or_fail (parse_address (&str, info));
+ if ((operands[i] == AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
+ && info->addr.writeback && info->addr.preind)
+ || (operands[i] == AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
+ && info->addr.writeback && info->addr.postind))
+ {
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+ }
+ if (info->addr.pcrel || info->addr.offset.is_reg
+ || !info->addr.preind || info->addr.postind
+ || info->addr.writeback)
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ /* Then retry, matching the specific syntax of these addresses. */
+ str = start;
+ po_char_or_fail ('[');
+ po_reg_or_fail (REG_TYPE_R64_SP);
+ po_char_or_fail (']');
+ break;
+ }
case AARCH64_OPND_ADDR_SIMPLE:
case AARCH64_OPND_SIMD_ADDR_SIMPLE:
{
@@ -7384,6 +7429,26 @@ parse_operands (char *str, const aarch64_opcode *opcode)
/* skip_p */ 0);
break;
+ case AARCH64_OPND_RCPC3_ADDR_OFFSET:
+ po_misc_or_fail (parse_address (&str, info));
+ if (info->addr.pcrel || info->addr.offset.is_reg
+ || !info->addr.preind || info->addr.postind
+ || info->addr.writeback)
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ if (inst.reloc.type != BFD_RELOC_UNUSED)
+ {
+ set_syntax_error (_("relocation not allowed"));
+ goto failure;
+ }
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+
case AARCH64_OPND_ADDR_UIMM12:
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index dc9c98353d4..f337d14eb24 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -783,6 +783,11 @@ enum aarch64_opnd
AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */
AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */
AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */
+ AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND, /* [<Xn|SP>]{, #<imm>}. */
+ AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [<Xn|SP>] or [<Xn|SP>, #<imm>]!. */
+ AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [<Xn|SP>], #<imm>. */
+ AARCH64_OPND_RCPC3_ADDR_PREIND_WB, /* [<Xn|SP>, #<imm>]!. */
+ AARCH64_OPND_RCPC3_ADDR_OFFSET
};
/* Qualifier constrains an operand. It either specifies a variant of an
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 9d994c12f1a..cf0eabeb946 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4488,7 +4488,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_ADDR_SIMM10:
case AARCH64_OPND_ADDR_SIMM11:
case AARCH64_OPND_ADDR_SIMM13:
+ case AARCH64_OPND_RCPC3_ADDR_OFFSET:
case AARCH64_OPND_ADDR_OFFSET:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_POSTIND:
+ case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
case AARCH64_OPND_SME_ADDR_RI_U4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4x32:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 708459e287d..3176cb877c2 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6875,4 +6875,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8), \
"an 8-bit signed immediate") \
Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8), \
- "an 8-bit unsigned immediate")
+ "an 8-bit unsigned immediate") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_OPT_POSTIND", 0, F(FLD_opc2), \
+ "an address with post-incrementing by ammount of loaded bytes") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_OPT_PREIND_WB", 0, F(FLD_opc2), \
+ "an address with pre-incrementing with write-back by ammount of stored bytes") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_POSTIND", 0, F(), \
+ "an address with post-incrementing by ammount of loaded bytes") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_PREIND_WB", 0, F(), \
+ "an address with pre-incrementing with write-back by ammount of stored bytes") \
+ Y(ADDRESS, rcpc3_addr_offset, "RCPC3_ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9), \
+ "an address with an optional 8-bit signed immediate offset")
--
2.42.0
next prev parent reply other threads:[~2024-01-12 16:56 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 1/8] aarch64: rcpc3: Add +rcpc3 architectural feature support flag Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 2/8] aarch64: rcpc3: Create implicit load/store size calc function Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 3/8] aarch64: rcpc3: Define address operand fields and inserter/extractors Victor Do Nascimento
2024-01-12 16:56 ` Victor Do Nascimento [this message]
2024-01-12 16:56 ` [PATCH 5/8] aarch64: rcpc3: add support in general_constraint_met_p Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 6/8] aarch64: rcpc3: Define RCPC3_INSN macro Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 7/8] aarch64: rcpc3: Add integer load/store insns Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 8/8] aarch64: rcpc3: Add FP " Victor Do Nascimento
2024-01-15 11:55 ` [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Nick Clifton
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