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From: Victor Do Nascimento <victor.donascimento@arm.com>
To: <binutils@sourceware.org>
Cc: <richard.earnshaw@arm.com>, <nickc@redhat.com>,
	Victor Do Nascimento <victor.donascimento@arm.com>
Subject: [PATCH 2/8] aarch64: rcpc3: Create implicit load/store size calc function
Date: Fri, 12 Jan 2024 16:56:16 +0000	[thread overview]
Message-ID: <20240112165637.2522719-3-victor.donascimento@arm.com> (raw)
In-Reply-To: <20240112165637.2522719-1-victor.donascimento@arm.com>

The allowed immediate offsets in integer rcpc3 load store instructions
are not encoded explicitly in the instruction itself, being rather
implicitly equivalent to the amount of data loaded/stored by the
instruction.

This leads to the requirement that this quantity be calculated based on
the number of registers involved in the transfer, either as data
source or destination registers and their respective qualifiers.

This is done via `calc_ldst_datasize (const aarch64_opnd_info *opnds)'
implemented here, using a cumulative sum of qualifier sizes preceding
the address operand in the OPNDS operand list argument.
---
 include/opcode/aarch64.h |  3 +++
 opcodes/aarch64-opc.c    | 22 ++++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 8ac48edf6a8..fe54de7cffe 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1832,6 +1832,9 @@ aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
 extern bool
 aarch64_cpu_supports_inst_p (aarch64_feature_set, aarch64_inst *);
 
+extern int
+calc_ldst_datasize (const aarch64_opnd_info *opnds);
+
 #ifdef DEBUG_AARCH64
 extern int debug_dump;
 
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index e3ad32f5a1e..bf506546fd0 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1658,6 +1658,28 @@ check_za_access (const aarch64_opnd_info *opnd,
   return true;
 }
 
+/* Given a load/store operation, calculate the size of transferred data via a
+   cumulative sum of qualifier sizes preceding the address operand in the
+   OPNDS operand list argument.  */
+int
+calc_ldst_datasize (const aarch64_opnd_info *opnds)
+{
+  unsigned num_bytes = 0; /* total number of bytes transferred.  */
+  enum aarch64_operand_class opnd_class;
+  enum aarch64_opnd type;
+
+  for (int i = 0; i < AARCH64_MAX_OPND_NUM; i++)
+    {
+      type = opnds[i].type;
+      opnd_class = aarch64_operands[type].op_class;
+      if (opnd_class == AARCH64_OPND_CLASS_ADDRESS)
+	break;
+      num_bytes += aarch64_get_qualifier_esize (opnds[i].qualifier);
+    }
+  return num_bytes;
+}
+
+
 /* General constraint checking based on operand code.
 
    Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
-- 
2.42.0


  parent reply	other threads:[~2024-01-12 16:56 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 1/8] aarch64: rcpc3: Add +rcpc3 architectural feature support flag Victor Do Nascimento
2024-01-12 16:56 ` Victor Do Nascimento [this message]
2024-01-12 16:56 ` [PATCH 3/8] aarch64: rcpc3: Define address operand fields and inserter/extractors Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 4/8] aarch64: rcpc3: New RCPC3_ADDR operand types Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 5/8] aarch64: rcpc3: add support in general_constraint_met_p Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 6/8] aarch64: rcpc3: Define RCPC3_INSN macro Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 7/8] aarch64: rcpc3: Add integer load/store insns Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 8/8] aarch64: rcpc3: Add FP " Victor Do Nascimento
2024-01-15 11:55 ` [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Nick Clifton

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