From: Victor Do Nascimento <victor.donascimento@arm.com>
To: <binutils@sourceware.org>
Cc: <richard.earnshaw@arm.com>, <nickc@redhat.com>,
Victor Do Nascimento <victor.donascimento@arm.com>
Subject: [PATCH 5/8] aarch64: rcpc3: add support in general_constraint_met_p
Date: Fri, 12 Jan 2024 16:56:19 +0000 [thread overview]
Message-ID: <20240112165637.2522719-6-victor.donascimento@arm.com> (raw)
In-Reply-To: <20240112165637.2522719-1-victor.donascimento@arm.com>
Given the introduction of the new address operand types for rcpc3
instructions, this patch adds the necessary logic to teach
`general_constraint_met_p` how to proper handle these.
---
opcodes/aarch64-opc.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index cf0eabeb946..e6f2d937875 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2046,6 +2046,19 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
return 0;
}
break;
+ case rcpc3:
+ if (opnd->addr.writeback)
+ if ((type == AARCH64_OPND_RCPC3_ADDR_PREIND_WB
+ && !opnd->addr.preind)
+ || (type == AARCH64_OPND_RCPC3_ADDR_POSTIND
+ && !opnd->addr.postind))
+ {
+ set_syntax_error (mismatch_detail, idx,
+ _("unexpected address writeback"));
+ return 0;
+ }
+
+ break;
default:
assert (opnd->addr.writeback == 0);
break;
@@ -2425,6 +2438,33 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
modifiers = 1 << AARCH64_MOD_UXTW;
goto sve_zz_operand;
+ case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
+ case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_POSTIND:
+ {
+ int num_bytes = calc_ldst_datasize (opnds);
+ int abs_offset = (type == AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
+ || type == AARCH64_OPND_RCPC3_ADDR_PREIND_WB)
+ ? opnd->addr.offset.imm * -1
+ : opnd->addr.offset.imm;
+ if ((int) num_bytes != abs_offset
+ && opnd->addr.offset.imm != 0)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid increment amount"));
+ return 0;
+ }
+ }
+ break;
+
+ case AARCH64_OPND_RCPC3_ADDR_OFFSET:
+ if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, -256, 255);
+ return 0;
+ }
+
default:
break;
}
--
2.42.0
next prev parent reply other threads:[~2024-01-12 16:56 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 1/8] aarch64: rcpc3: Add +rcpc3 architectural feature support flag Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 2/8] aarch64: rcpc3: Create implicit load/store size calc function Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 3/8] aarch64: rcpc3: Define address operand fields and inserter/extractors Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 4/8] aarch64: rcpc3: New RCPC3_ADDR operand types Victor Do Nascimento
2024-01-12 16:56 ` Victor Do Nascimento [this message]
2024-01-12 16:56 ` [PATCH 6/8] aarch64: rcpc3: Define RCPC3_INSN macro Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 7/8] aarch64: rcpc3: Add integer load/store insns Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 8/8] aarch64: rcpc3: Add FP " Victor Do Nascimento
2024-01-15 11:55 ` [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Nick Clifton
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