From: Matthieu Longo <matthieu.longo@arm.com>
To: binutils@sourceware.org
Cc: Richard Earnshaw <richard.earnshaw@arm.com>,
Nick Clifton <nickc@redhat.com>,
Matthieu Longo <matthieu.longo@arm.com>
Subject: [PATCH v1 3/4] aarch64: testsuite: reorder write and read to match macro order
Date: Tue, 27 Feb 2024 10:59:16 +0000 [thread overview]
Message-ID: <20240227105917.295899-4-matthieu.longo@arm.com> (raw)
In-Reply-To: <20240227105917.295899-1-matthieu.longo@arm.com>
[-- Attachment #1: Type: text/plain, Size: 868 bytes --]
This patch aims at grouping write and read for a same system register
one after another so that the diff for the macro replacement does not
generate too much noise.
---
.../aarch64/sysreg/armv8_9-a-sysregs-bad.l | 56 ++--
.../gas/aarch64/sysreg/armv8_9-a-sysregs.d | 88 +++---
.../gas/aarch64/sysreg/armv8_9-a-sysregs.s | 90 +++---
gas/testsuite/gas/aarch64/sysreg/sysreg-7.d | 16 +-
gas/testsuite/gas/aarch64/sysreg/sysreg-7.s | 20 +-
gas/testsuite/gas/aarch64/sysreg/sysreg-8.d | 258 +++++++++---------
gas/testsuite/gas/aarch64/sysreg/sysreg-8.s | 2 +-
gas/testsuite/gas/aarch64/sysreg/sysreg.d | 10 +-
gas/testsuite/gas/aarch64/sysreg/sysreg.s | 14 +-
gas/testsuite/gas/aarch64/sysreg/sysreg128.d | 22 +-
gas/testsuite/gas/aarch64/sysreg/sysreg128.s | 2 +-
11 files changed, 286 insertions(+), 292 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0003-aarch64-testsuite-reorder-write-and-read-to-match.patch --]
[-- Type: text/x-patch; name="v1-0003-aarch64-testsuite-reorder-write-and-read-to-match.patch", Size: 41540 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l
index 02d9cac392c..d98c2ed573a 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l
+++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l
@@ -3,79 +3,79 @@
.*: Error: selected processor does not support system register name 'pmsdsfr_el1'
.*: Error: selected processor does not support system register name 'erxgsr_el1'
.*: Error: selected processor does not support system register name 'sctlr2_el1'
-.*: Error: selected processor does not support system register name 'sctlr2_el12'
-.*: Error: selected processor does not support system register name 'sctlr2_el2'
-.*: Error: selected processor does not support system register name 'sctlr2_el3'
.*: Error: selected processor does not support system register name 'sctlr2_el1'
.*: Error: selected processor does not support system register name 'sctlr2_el12'
+.*: Error: selected processor does not support system register name 'sctlr2_el12'
.*: Error: selected processor does not support system register name 'sctlr2_el2'
+.*: Error: selected processor does not support system register name 'sctlr2_el2'
+.*: Error: selected processor does not support system register name 'sctlr2_el3'
.*: Error: selected processor does not support system register name 'sctlr2_el3'
.*: Error: selected processor does not support system register name 'hdfgrtr2_el2'
-.*: Error: selected processor does not support system register name 'hdfgwtr2_el2'
-.*: Error: selected processor does not support system register name 'hfgrtr2_el2'
-.*: Error: selected processor does not support system register name 'hfgwtr2_el2'
.*: Error: selected processor does not support system register name 'hdfgrtr2_el2'
.*: Error: selected processor does not support system register name 'hdfgwtr2_el2'
+.*: Error: selected processor does not support system register name 'hdfgwtr2_el2'
+.*: Error: selected processor does not support system register name 'hfgrtr2_el2'
.*: Error: selected processor does not support system register name 'hfgrtr2_el2'
.*: Error: selected processor does not support system register name 'hfgwtr2_el2'
+.*: Error: selected processor does not support system register name 'hfgwtr2_el2'
.*: Error: selected processor does not support system register name 'pfar_el1'
-.*: Error: selected processor does not support system register name 'pfar_el2'
-.*: Error: selected processor does not support system register name 'pfar_el12'
.*: Error: selected processor does not support system register name 'pfar_el1'
.*: Error: selected processor does not support system register name 'pfar_el2'
+.*: Error: selected processor does not support system register name 'pfar_el2'
+.*: Error: selected processor does not support system register name 'pfar_el12'
.*: Error: selected processor does not support system register name 'pfar_el12'
.*: Error: selected processor does not support system register name 's1e1a'
.*: Error: selected processor does not support system register name 's1e2a'
.*: Error: selected processor does not support system register name 's1e3a'
.*: Error: selected processor does not support system register name 'amair2_el1'
-.*: Error: selected processor does not support system register name 'amair2_el12'
-.*: Error: selected processor does not support system register name 'amair2_el2'
-.*: Error: selected processor does not support system register name 'amair2_el3'
-.*: Error: selected processor does not support system register name 'mair2_el1'
-.*: Error: selected processor does not support system register name 'mair2_el12'
-.*: Error: selected processor does not support system register name 'mair2_el2'
-.*: Error: selected processor does not support system register name 'mair2_el3'
.*: Error: selected processor does not support system register name 'amair2_el1'
.*: Error: selected processor does not support system register name 'amair2_el12'
+.*: Error: selected processor does not support system register name 'amair2_el12'
+.*: Error: selected processor does not support system register name 'amair2_el2'
.*: Error: selected processor does not support system register name 'amair2_el2'
.*: Error: selected processor does not support system register name 'amair2_el3'
+.*: Error: selected processor does not support system register name 'amair2_el3'
+.*: Error: selected processor does not support system register name 'mair2_el1'
.*: Error: selected processor does not support system register name 'mair2_el1'
.*: Error: selected processor does not support system register name 'mair2_el12'
+.*: Error: selected processor does not support system register name 'mair2_el12'
.*: Error: selected processor does not support system register name 'mair2_el2'
+.*: Error: selected processor does not support system register name 'mair2_el2'
+.*: Error: selected processor does not support system register name 'mair2_el3'
.*: Error: selected processor does not support system register name 'mair2_el3'
.*: Error: selected processor does not support system register name 'pir_el1'
-.*: Error: selected processor does not support system register name 'pir_el12'
-.*: Error: selected processor does not support system register name 'pir_el2'
-.*: Error: selected processor does not support system register name 'pir_el3'
-.*: Error: selected processor does not support system register name 'pire0_el1'
-.*: Error: selected processor does not support system register name 'pire0_el12'
-.*: Error: selected processor does not support system register name 'pire0_el2'
.*: Error: selected processor does not support system register name 'pir_el1'
.*: Error: selected processor does not support system register name 'pir_el12'
+.*: Error: selected processor does not support system register name 'pir_el12'
.*: Error: selected processor does not support system register name 'pir_el2'
+.*: Error: selected processor does not support system register name 'pir_el2'
+.*: Error: selected processor does not support system register name 'pir_el3'
.*: Error: selected processor does not support system register name 'pir_el3'
.*: Error: selected processor does not support system register name 'pire0_el1'
+.*: Error: selected processor does not support system register name 'pire0_el1'
+.*: Error: selected processor does not support system register name 'pire0_el12'
.*: Error: selected processor does not support system register name 'pire0_el12'
.*: Error: selected processor does not support system register name 'pire0_el2'
+.*: Error: selected processor does not support system register name 'pire0_el2'
.*: Error: selected processor does not support system register name 's2pir_el2'
.*: Error: selected processor does not support system register name 's2pir_el2'
.*: Error: selected processor does not support system register name 'por_el0'
-.*: Error: selected processor does not support system register name 'por_el1'
-.*: Error: selected processor does not support system register name 'por_el12'
-.*: Error: selected processor does not support system register name 'por_el2'
-.*: Error: selected processor does not support system register name 'por_el3'
.*: Error: selected processor does not support system register name 'por_el0'
.*: Error: selected processor does not support system register name 'por_el1'
+.*: Error: selected processor does not support system register name 'por_el1'
+.*: Error: selected processor does not support system register name 'por_el12'
.*: Error: selected processor does not support system register name 'por_el12'
.*: Error: selected processor does not support system register name 'por_el2'
+.*: Error: selected processor does not support system register name 'por_el2'
+.*: Error: selected processor does not support system register name 'por_el3'
.*: Error: selected processor does not support system register name 'por_el3'
.*: Error: selected processor does not support system register name 's2por_el1'
.*: Error: selected processor does not support system register name 's2por_el1'
.*: Error: selected processor does not support system register name 'tcr2_el1'
-.*: Error: selected processor does not support system register name 'tcr2_el12'
-.*: Error: selected processor does not support system register name 'tcr2_el2'
.*: Error: selected processor does not support system register name 'tcr2_el1'
.*: Error: selected processor does not support system register name 'tcr2_el12'
+.*: Error: selected processor does not support system register name 'tcr2_el12'
+.*: Error: selected processor does not support system register name 'tcr2_el2'
.*: Error: selected processor does not support system register name 'tcr2_el2'
.*: Error: selected processor does not support system register name 'mdselr_el1'
.*: Error: selected processor does not support system register name 'mdselr_el1'
@@ -123,4 +123,4 @@
.*: Error: selected processor does not support system register name 'pmecr_el1'
.*: Error: selected processor does not support system register name 'pmecr_el1'
.*: Error: selected processor does not support system register name 'pmiar_el1'
-.*: Error: selected processor does not support system register name 'pmiar_el1'
+.*: Error: selected processor does not support system register name 'pmiar_el1'
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d
index dc1e8bc1fa8..ac32b80b40c 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d
@@ -6,92 +6,92 @@
Disassembly of section \.text:
0+ <.*>:
-.*: d53c9a83 mrs x3, pmsdsfr_el1
.*: d51c9a83 msr pmsdsfr_el1, x3
+.*: d53c9a83 mrs x3, pmsdsfr_el1
.*: d5385340 mrs x0, erxgsr_el1
.*: d5181063 msr sctlr2_el1, x3
-.*: d51d1063 msr sctlr2_el12, x3
-.*: d51c1063 msr sctlr2_el2, x3
-.*: d51e1063 msr sctlr2_el3, x3
.*: d5381063 mrs x3, sctlr2_el1
+.*: d51d1063 msr sctlr2_el12, x3
.*: d53d1063 mrs x3, sctlr2_el12
+.*: d51c1063 msr sctlr2_el2, x3
.*: d53c1063 mrs x3, sctlr2_el2
+.*: d51e1063 msr sctlr2_el3, x3
.*: d53e1063 mrs x3, sctlr2_el3
-.*: d53c3103 mrs x3, hdfgrtr2_el2
-.*: d53c3123 mrs x3, hdfgwtr2_el2
-.*: d53c3143 mrs x3, hfgrtr2_el2
-.*: d53c3163 mrs x3, hfgwtr2_el2
.*: d51c3103 msr hdfgrtr2_el2, x3
+.*: d53c3103 mrs x3, hdfgrtr2_el2
.*: d51c3123 msr hdfgwtr2_el2, x3
+.*: d53c3123 mrs x3, hdfgwtr2_el2
.*: d51c3143 msr hfgrtr2_el2, x3
+.*: d53c3143 mrs x3, hfgrtr2_el2
.*: d51c3163 msr hfgwtr2_el2, x3
-.*: d53860a0 mrs x0, pfar_el1
-.*: d53c60a0 mrs x0, pfar_el2
-.*: d53d60a0 mrs x0, pfar_el12
+.*: d53c3163 mrs x3, hfgwtr2_el2
.*: d51860a0 msr pfar_el1, x0
+.*: d53860a0 mrs x0, pfar_el1
.*: d51c60a0 msr pfar_el2, x0
+.*: d53c60a0 mrs x0, pfar_el2
.*: d51d60a0 msr pfar_el12, x0
+.*: d53d60a0 mrs x0, pfar_el12
.*: d5087941 at s1e1a, x1
.*: d50c7943 at s1e2a, x3
.*: d50e7945 at s1e3a, x5
-.*: d538a320 mrs x0, amair2_el1
-.*: d53da320 mrs x0, amair2_el12
-.*: d53ca320 mrs x0, amair2_el2
-.*: d53ea320 mrs x0, amair2_el3
-.*: d538a220 mrs x0, mair2_el1
-.*: d53da220 mrs x0, mair2_el12
-.*: d53ca120 mrs x0, mair2_el2
-.*: d53ea120 mrs x0, mair2_el3
.*: d518a320 msr amair2_el1, x0
+.*: d538a320 mrs x0, amair2_el1
.*: d51da320 msr amair2_el12, x0
+.*: d53da320 mrs x0, amair2_el12
.*: d51ca320 msr amair2_el2, x0
+.*: d53ca320 mrs x0, amair2_el2
.*: d51ea320 msr amair2_el3, x0
+.*: d53ea320 mrs x0, amair2_el3
.*: d518a220 msr mair2_el1, x0
+.*: d538a220 mrs x0, mair2_el1
.*: d51da220 msr mair2_el12, x0
+.*: d53da220 mrs x0, mair2_el12
.*: d51ca120 msr mair2_el2, x0
+.*: d53ca120 mrs x0, mair2_el2
.*: d51ea120 msr mair2_el3, x0
-.*: d538a260 mrs x0, pir_el1
-.*: d53da260 mrs x0, pir_el12
-.*: d53ca260 mrs x0, pir_el2
-.*: d53ea260 mrs x0, pir_el3
-.*: d538a240 mrs x0, pire0_el1
-.*: d53da240 mrs x0, pire0_el12
-.*: d53ca240 mrs x0, pire0_el2
+.*: d53ea120 mrs x0, mair2_el3
.*: d518a260 msr pir_el1, x0
+.*: d538a260 mrs x0, pir_el1
.*: d51da260 msr pir_el12, x0
+.*: d53da260 mrs x0, pir_el12
.*: d51ca260 msr pir_el2, x0
+.*: d53ca260 mrs x0, pir_el2
.*: d51ea260 msr pir_el3, x0
+.*: d53ea260 mrs x0, pir_el3
.*: d518a240 msr pire0_el1, x0
+.*: d538a240 mrs x0, pire0_el1
.*: d51da240 msr pire0_el12, x0
+.*: d53da240 mrs x0, pire0_el12
.*: d51ca240 msr pire0_el2, x0
-.*: d53ca2a0 mrs x0, s2pir_el2
+.*: d53ca240 mrs x0, pire0_el2
.*: d51ca2a0 msr s2pir_el2, x0
-.*: d53ba280 mrs x0, por_el0
-.*: d538a280 mrs x0, por_el1
-.*: d53da280 mrs x0, por_el12
-.*: d53ca280 mrs x0, por_el2
-.*: d53ea280 mrs x0, por_el3
+.*: d53ca2a0 mrs x0, s2pir_el2
.*: d51ba280 msr por_el0, x0
+.*: d53ba280 mrs x0, por_el0
.*: d518a280 msr por_el1, x0
+.*: d538a280 mrs x0, por_el1
.*: d51da280 msr por_el12, x0
+.*: d53da280 mrs x0, por_el12
.*: d51ca280 msr por_el2, x0
+.*: d53ca280 mrs x0, por_el2
.*: d51ea280 msr por_el3, x0
-.*: d538a2a0 mrs x0, s2por_el1
+.*: d53ea280 mrs x0, por_el3
.*: d518a2a0 msr s2por_el1, x0
-.*: d5382060 mrs x0, tcr2_el1
-.*: d53d2060 mrs x0, tcr2_el12
-.*: d53c2060 mrs x0, tcr2_el2
+.*: d538a2a0 mrs x0, s2por_el1
.*: d5182060 msr tcr2_el1, x0
+.*: d5382060 mrs x0, tcr2_el1
.*: d51d2060 msr tcr2_el12, x0
+.*: d53d2060 mrs x0, tcr2_el12
.*: d51c2060 msr tcr2_el2, x0
-.*: d5300440 mrs x0, mdselr_el1
+.*: d53c2060 mrs x0, tcr2_el2
.*: d5100440 msr mdselr_el1, x0
-.*: d5389e80 mrs x0, pmuacr_el1
+.*: d5300440 mrs x0, mdselr_el1
.*: d5189e80 msr pmuacr_el1, x0
+.*: d5389e80 mrs x0, pmuacr_el1
.*: d530ebe0 mrs x0, pmccntsvr_el1
.*: d530ec00 mrs x0, pmicntsvr_el1
-.*: d5389d60 mrs x0, pmsscr_el1
.*: d5189d60 msr pmsscr_el1, x0
+.*: d5389d60 mrs x0, pmsscr_el1
.*: d530e800 mrs x0, pmevcntsvr0_el1
.*: d530e940 mrs x0, pmevcntsvr10_el1
.*: d530e960 mrs x0, pmevcntsvr11_el1
@@ -122,12 +122,12 @@ Disassembly of section \.text:
.*: d530e8e0 mrs x0, pmevcntsvr7_el1
.*: d530e900 mrs x0, pmevcntsvr8_el1
.*: d530e920 mrs x0, pmevcntsvr9_el1
-.*: d53b9400 mrs x0, pmicntr_el0
.*: d51b9400 msr pmicntr_el0, x0
-.*: d53b9600 mrs x0, pmicfiltr_el0
+.*: d53b9400 mrs x0, pmicntr_el0
.*: d51b9600 msr pmicfiltr_el0, x0
+.*: d53b9600 mrs x0, pmicfiltr_el0
.*: d51b9d80 msr pmzr_el0, x0
-.*: d5389ea0 mrs x0, pmecr_el1
.*: d5189ea0 msr pmecr_el1, x0
-.*: d5389ee0 mrs x0, pmiar_el1
-.*: d5189ee0 msr pmiar_el1, x0
\ No newline at end of file
+.*: d5389ea0 mrs x0, pmecr_el1
+.*: d5189ee0 msr pmiar_el1, x0
+.*: d5389ee0 mrs x0, pmiar_el1
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s
index 536631823f5..bf9019c9ac8 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s
@@ -1,32 +1,32 @@
- mrs x3, PMSDSFR_EL1
msr PMSDSFR_EL1, x3
+ mrs x3, PMSDSFR_EL1
mrs x0, ERXGSR_EL1
msr SCTLR2_EL1, x3
- msr SCTLR2_EL12, x3
- msr SCTLR2_EL2, x3
- msr SCTLR2_EL3, x3
mrs x3, SCTLR2_EL1
+ msr SCTLR2_EL12, x3
mrs x3, SCTLR2_EL12
+ msr SCTLR2_EL2, x3
mrs x3, SCTLR2_EL2
+ msr SCTLR2_EL3, x3
mrs x3, SCTLR2_EL3
- mrs x3, HDFGRTR2_EL2
- mrs x3, HDFGWTR2_EL2
- mrs x3, HFGRTR2_EL2
- mrs x3, HFGWTR2_EL2
msr HDFGRTR2_EL2, x3
+ mrs x3, HDFGRTR2_EL2
msr HDFGWTR2_EL2, x3
+ mrs x3, HDFGWTR2_EL2
msr HFGRTR2_EL2, x3
+ mrs x3, HFGRTR2_EL2
msr HFGWTR2_EL2, x3
+ mrs x3, HFGWTR2_EL2
- mrs x0, PFAR_EL1
- mrs x0, PFAR_EL2
- mrs x0, PFAR_EL12
msr PFAR_EL1, x0
+ mrs x0, PFAR_EL1
msr PFAR_EL2, x0
+ mrs x0, PFAR_EL2
msr PFAR_EL12, x0
+ mrs x0, PFAR_EL12
/* AT. */
at s1e1a, x1
@@ -34,84 +34,80 @@
at s1e3a, x5
/* FEAT_AIE. */
- mrs x0, amair2_el1
- mrs x0, amair2_el12
- mrs x0, amair2_el2
- mrs x0, amair2_el3
- mrs x0, mair2_el1
- mrs x0, mair2_el12
- mrs x0, mair2_el2
- mrs x0, mair2_el3
-
msr amair2_el1, x0
+ mrs x0, amair2_el1
msr amair2_el12, x0
+ mrs x0, amair2_el12
msr amair2_el2, x0
+ mrs x0, amair2_el2
msr amair2_el3, x0
+ mrs x0, amair2_el3
msr mair2_el1, x0
+ mrs x0, mair2_el1
msr mair2_el12, x0
+ mrs x0, mair2_el12
msr mair2_el2, x0
+ mrs x0, mair2_el2
msr mair2_el3, x0
+ mrs x0, mair2_el3
/* FEAT_S1PIE. */
- mrs x0, pir_el1
- mrs x0, pir_el12
- mrs x0, pir_el2
- mrs x0, pir_el3
- mrs x0, pire0_el1
- mrs x0, pire0_el12
- mrs x0, pire0_el2
-
msr pir_el1, x0
+ mrs x0, pir_el1
msr pir_el12, x0
+ mrs x0, pir_el12
msr pir_el2, x0
+ mrs x0, pir_el2
msr pir_el3, x0
+ mrs x0, pir_el3
msr pire0_el1, x0
+ mrs x0, pire0_el1
msr pire0_el12, x0
+ mrs x0, pire0_el12
msr pire0_el2, x0
+ mrs x0, pire0_el2
/* FEAT_S2PIE. */
- mrs x0, s2pir_el2
msr s2pir_el2, x0
+ mrs x0, s2pir_el2
/* FEAT_S1POE. */
- mrs x0, por_el0
- mrs x0, por_el1
- mrs x0, por_el12
- mrs x0, por_el2
- mrs x0, por_el3
-
msr por_el0, x0
+ mrs x0, por_el0
msr por_el1, x0
+ mrs x0, por_el1
msr por_el12, x0
+ mrs x0, por_el12
msr por_el2, x0
+ mrs x0, por_el2
msr por_el3, x0
+ mrs x0, por_el3
/* FEAT_S21POE. */
- mrs x0, s2por_el1
msr s2por_el1, x0
+ mrs x0, s2por_el1
/* FEAT_TCR2. */
- mrs x0, tcr2_el1
- mrs x0, tcr2_el12
- mrs x0, tcr2_el2
-
msr tcr2_el1, x0
+ mrs x0, tcr2_el1
msr tcr2_el12, x0
+ mrs x0, tcr2_el12
msr tcr2_el2, x0
+ mrs x0, tcr2_el2
/* FEAT_DEBUGv8p9 Extension. */
- mrs x0, mdselr_el1
msr mdselr_el1, x0
+ mrs x0, mdselr_el1
/* FEAT_PMUv3p9 Extension. */
- mrs x0, pmuacr_el1
msr pmuacr_el1, x0
+ mrs x0, pmuacr_el1
/* FEAT_PMUv3_SS Extension. */
mrs x0, pmccntsvr_el1
mrs x0, pmicntsvr_el1
- mrs x0, pmsscr_el1
msr pmsscr_el1, x0
+ mrs x0, pmsscr_el1
mrs x0, pmevcntsvr0_el1
mrs x0, pmevcntsvr10_el1
mrs x0, pmevcntsvr11_el1
@@ -144,14 +140,14 @@
mrs x0, pmevcntsvr9_el1
/* FEAT_PMUv3_ICNTR Extension. */
- mrs x0, pmicntr_el0
msr pmicntr_el0, x0
- mrs x0, pmicfiltr_el0
+ mrs x0, pmicntr_el0
msr pmicfiltr_el0, x0
+ mrs x0, pmicfiltr_el0
msr pmzr_el0, x0
/* FEAT_SEBEP Extension. */
- mrs x0, pmecr_el1
msr pmecr_el1, x0
- mrs x0, pmiar_el1
+ mrs x0, pmecr_el1
msr pmiar_el1, x0
+ mrs x0, pmiar_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d
index 1564f530c67..5d74fd7056b 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d
@@ -6,20 +6,20 @@ Disassembly of section \.text:
0+ <.*>:
+.*: d518a460 msr lorc_el1, x0
.*: d538a460 mrs x0, lorc_el1
+.*: d518a420 msr lorea_el1, x0
.*: d538a420 mrs x0, lorea_el1
+.*: d518a440 msr lorn_el1, x0
.*: d538a440 mrs x0, lorn_el1
+.*: d518a400 msr lorsa_el1, x0
.*: d538a400 mrs x0, lorsa_el1
+.*: d51ecc80 msr icc_ctlr_el3, x0
.*: d53ecc80 mrs x0, icc_ctlr_el3
+.*: d518cca0 msr icc_sre_el1, x0
.*: d538cca0 mrs x0, icc_sre_el1
+.*: d51cc9a0 msr icc_sre_el2, x0
.*: d53cc9a0 mrs x0, icc_sre_el2
+.*: d51ecca0 msr icc_sre_el3, x0
.*: d53ecca0 mrs x0, icc_sre_el3
.*: d53ccb20 mrs x0, ich_vtr_el2
-.*: d518a460 msr lorc_el1, x0
-.*: d518a420 msr lorea_el1, x0
-.*: d518a440 msr lorn_el1, x0
-.*: d518a400 msr lorsa_el1, x0
-.*: d51ecc80 msr icc_ctlr_el3, x0
-.*: d518cca0 msr icc_sre_el1, x0
-.*: d51cc9a0 msr icc_sre_el2, x0
-.*: d51ecca0 msr icc_sre_el3, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s
index 94dd85b1a03..8354a44a813 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s
@@ -1,22 +1,20 @@
.arch armv8-a+lor
-/* Read from system registers. */
+msr lorc_el1, x0
mrs x0, lorc_el1
+msr lorea_el1, x0
mrs x0, lorea_el1
+msr lorn_el1, x0
mrs x0, lorn_el1
+msr lorsa_el1, x0
mrs x0, lorsa_el1
+msr icc_ctlr_el3, x0
mrs x0, icc_ctlr_el3
+msr icc_sre_el1, x0
mrs x0, icc_sre_el1
+msr icc_sre_el2, x0
mrs x0, icc_sre_el2
+msr icc_sre_el3, x0
mrs x0, icc_sre_el3
-mrs x0, ich_vtr_el2
-/* Write to system registers. */
-msr lorc_el1, x0
-msr lorea_el1, x0
-msr lorn_el1, x0
-msr lorsa_el1, x0
-msr icc_ctlr_el3, x0
-msr icc_sre_el1, x0
-msr icc_sre_el2, x0
-msr icc_sre_el3, x0
+mrs x0, ich_vtr_el2
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d
index 3f048849836..d93b4c7da40 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d
@@ -9,29 +9,29 @@ Disassembly of section \.text:
[^:]*: d53803a0 mrs x0, id_dfr1_el1
[^:]*: d53803c0 mrs x0, id_mmfr5_el1
[^:]*: d53802e0 mrs x0, id_isar6_el1
-[^:]*: d5384600 mrs x0, icc_pmr_el1
[^:]*: d5184600 msr icc_pmr_el1, x0
+[^:]*: d5384600 mrs x0, icc_pmr_el1
[^:]*: d538c800 mrs x0, icc_iar0_el1
[^:]*: d518c820 msr icc_eoir0_el1, x0
[^:]*: d538c840 mrs x0, icc_hppir0_el1
-[^:]*: d538c860 mrs x0, icc_bpr0_el1
[^:]*: d518c860 msr icc_bpr0_el1, x0
-[^:]*: d538c880 mrs x0, icc_ap0r0_el1
+[^:]*: d538c860 mrs x0, icc_bpr0_el1
[^:]*: d518c880 msr icc_ap0r0_el1, x0
-[^:]*: d538c8a0 mrs x0, icc_ap0r1_el1
+[^:]*: d538c880 mrs x0, icc_ap0r0_el1
[^:]*: d518c8a0 msr icc_ap0r1_el1, x0
-[^:]*: d538c8c0 mrs x0, icc_ap0r2_el1
+[^:]*: d538c8a0 mrs x0, icc_ap0r1_el1
[^:]*: d518c8c0 msr icc_ap0r2_el1, x0
-[^:]*: d538c8e0 mrs x0, icc_ap0r3_el1
+[^:]*: d538c8c0 mrs x0, icc_ap0r2_el1
[^:]*: d518c8e0 msr icc_ap0r3_el1, x0
-[^:]*: d538c900 mrs x0, icc_ap1r0_el1
+[^:]*: d538c8e0 mrs x0, icc_ap0r3_el1
[^:]*: d518c900 msr icc_ap1r0_el1, x0
-[^:]*: d538c920 mrs x0, icc_ap1r1_el1
+[^:]*: d538c900 mrs x0, icc_ap1r0_el1
[^:]*: d518c920 msr icc_ap1r1_el1, x0
-[^:]*: d538c940 mrs x0, icc_ap1r2_el1
+[^:]*: d538c920 mrs x0, icc_ap1r1_el1
[^:]*: d518c940 msr icc_ap1r2_el1, x0
-[^:]*: d538c960 mrs x0, icc_ap1r3_el1
+[^:]*: d538c940 mrs x0, icc_ap1r2_el1
[^:]*: d518c960 msr icc_ap1r3_el1, x0
+[^:]*: d538c960 mrs x0, icc_ap1r3_el1
[^:]*: d518cb20 msr icc_dir_el1, x0
[^:]*: d538cb60 mrs x0, icc_rpr_el1
[^:]*: d518cba0 msr icc_sgi1r_el1, x0
@@ -40,256 +40,256 @@ Disassembly of section \.text:
[^:]*: d538cc00 mrs x0, icc_iar1_el1
[^:]*: d518cc20 msr icc_eoir1_el1, x0
[^:]*: d538cc40 mrs x0, icc_hppir1_el1
-[^:]*: d538cc60 mrs x0, icc_bpr1_el1
[^:]*: d518cc60 msr icc_bpr1_el1, x0
-[^:]*: d538cc80 mrs x0, icc_ctlr_el1
+[^:]*: d538cc60 mrs x0, icc_bpr1_el1
[^:]*: d518cc80 msr icc_ctlr_el1, x0
-[^:]*: d538ccc0 mrs x0, icc_igrpen0_el1
+[^:]*: d538cc80 mrs x0, icc_ctlr_el1
[^:]*: d518ccc0 msr icc_igrpen0_el1, x0
-[^:]*: d538cce0 mrs x0, icc_igrpen1_el1
+[^:]*: d538ccc0 mrs x0, icc_igrpen0_el1
[^:]*: d518cce0 msr icc_igrpen1_el1, x0
-[^:]*: d53cc800 mrs x0, ich_ap0r0_el2
+[^:]*: d538cce0 mrs x0, icc_igrpen1_el1
[^:]*: d51cc800 msr ich_ap0r0_el2, x0
-[^:]*: d53cc820 mrs x0, ich_ap0r1_el2
+[^:]*: d53cc800 mrs x0, ich_ap0r0_el2
[^:]*: d51cc820 msr ich_ap0r1_el2, x0
-[^:]*: d53cc840 mrs x0, ich_ap0r2_el2
+[^:]*: d53cc820 mrs x0, ich_ap0r1_el2
[^:]*: d51cc840 msr ich_ap0r2_el2, x0
-[^:]*: d53cc860 mrs x0, ich_ap0r3_el2
+[^:]*: d53cc840 mrs x0, ich_ap0r2_el2
[^:]*: d51cc860 msr ich_ap0r3_el2, x0
-[^:]*: d53cc900 mrs x0, ich_ap1r0_el2
+[^:]*: d53cc860 mrs x0, ich_ap0r3_el2
[^:]*: d51cc900 msr ich_ap1r0_el2, x0
-[^:]*: d53cc920 mrs x0, ich_ap1r1_el2
+[^:]*: d53cc900 mrs x0, ich_ap1r0_el2
[^:]*: d51cc920 msr ich_ap1r1_el2, x0
-[^:]*: d53cc940 mrs x0, ich_ap1r2_el2
+[^:]*: d53cc920 mrs x0, ich_ap1r1_el2
[^:]*: d51cc940 msr ich_ap1r2_el2, x0
-[^:]*: d53cc960 mrs x0, ich_ap1r3_el2
+[^:]*: d53cc940 mrs x0, ich_ap1r2_el2
[^:]*: d51cc960 msr ich_ap1r3_el2, x0
-[^:]*: d53ccb00 mrs x0, ich_hcr_el2
+[^:]*: d53cc960 mrs x0, ich_ap1r3_el2
[^:]*: d51ccb00 msr ich_hcr_el2, x0
+[^:]*: d53ccb00 mrs x0, ich_hcr_el2
[^:]*: d53ccb40 mrs x0, ich_misr_el2
[^:]*: d53ccb60 mrs x0, ich_eisr_el2
[^:]*: d53ccba0 mrs x0, ich_elrsr_el2
-[^:]*: d53ccbe0 mrs x0, ich_vmcr_el2
[^:]*: d51ccbe0 msr ich_vmcr_el2, x0
-[^:]*: d53ccc00 mrs x0, ich_lr0_el2
+[^:]*: d53ccbe0 mrs x0, ich_vmcr_el2
[^:]*: d51ccc00 msr ich_lr0_el2, x0
-[^:]*: d53ccc20 mrs x0, ich_lr1_el2
+[^:]*: d53ccc00 mrs x0, ich_lr0_el2
[^:]*: d51ccc20 msr ich_lr1_el2, x0
-[^:]*: d53ccc40 mrs x0, ich_lr2_el2
+[^:]*: d53ccc20 mrs x0, ich_lr1_el2
[^:]*: d51ccc40 msr ich_lr2_el2, x0
-[^:]*: d53ccc60 mrs x0, ich_lr3_el2
+[^:]*: d53ccc40 mrs x0, ich_lr2_el2
[^:]*: d51ccc60 msr ich_lr3_el2, x0
-[^:]*: d53ccc80 mrs x0, ich_lr4_el2
+[^:]*: d53ccc60 mrs x0, ich_lr3_el2
[^:]*: d51ccc80 msr ich_lr4_el2, x0
-[^:]*: d53ccca0 mrs x0, ich_lr5_el2
+[^:]*: d53ccc80 mrs x0, ich_lr4_el2
[^:]*: d51ccca0 msr ich_lr5_el2, x0
-[^:]*: d53cccc0 mrs x0, ich_lr6_el2
+[^:]*: d53ccca0 mrs x0, ich_lr5_el2
[^:]*: d51cccc0 msr ich_lr6_el2, x0
-[^:]*: d53ccce0 mrs x0, ich_lr7_el2
+[^:]*: d53cccc0 mrs x0, ich_lr6_el2
[^:]*: d51ccce0 msr ich_lr7_el2, x0
-[^:]*: d53ccd00 mrs x0, ich_lr8_el2
+[^:]*: d53ccce0 mrs x0, ich_lr7_el2
[^:]*: d51ccd00 msr ich_lr8_el2, x0
-[^:]*: d53ccd20 mrs x0, ich_lr9_el2
+[^:]*: d53ccd00 mrs x0, ich_lr8_el2
[^:]*: d51ccd20 msr ich_lr9_el2, x0
-[^:]*: d53ccd40 mrs x0, ich_lr10_el2
+[^:]*: d53ccd20 mrs x0, ich_lr9_el2
[^:]*: d51ccd40 msr ich_lr10_el2, x0
-[^:]*: d53ccd60 mrs x0, ich_lr11_el2
+[^:]*: d53ccd40 mrs x0, ich_lr10_el2
[^:]*: d51ccd60 msr ich_lr11_el2, x0
-[^:]*: d53ccd80 mrs x0, ich_lr12_el2
+[^:]*: d53ccd60 mrs x0, ich_lr11_el2
[^:]*: d51ccd80 msr ich_lr12_el2, x0
-[^:]*: d53ccda0 mrs x0, ich_lr13_el2
+[^:]*: d53ccd80 mrs x0, ich_lr12_el2
[^:]*: d51ccda0 msr ich_lr13_el2, x0
-[^:]*: d53ccdc0 mrs x0, ich_lr14_el2
+[^:]*: d53ccda0 mrs x0, ich_lr13_el2
[^:]*: d51ccdc0 msr ich_lr14_el2, x0
-[^:]*: d53ccde0 mrs x0, ich_lr15_el2
+[^:]*: d53ccdc0 mrs x0, ich_lr14_el2
[^:]*: d51ccde0 msr ich_lr15_el2, x0
-[^:]*: d53ecce0 mrs x0, icc_igrpen1_el3
+[^:]*: d53ccde0 mrs x0, ich_lr15_el2
[^:]*: d51ecce0 msr icc_igrpen1_el3, x0
+[^:]*: d53ecce0 mrs x0, icc_igrpen1_el3
[^:]*: d538a4e0 mrs x0, lorid_el1
[^:]*: d5390040 mrs x0, ccsidr2_el1
-[^:]*: d5381220 mrs x0, trfcr_el1
[^:]*: d5181220 msr trfcr_el1, x0
+[^:]*: d5381220 mrs x0, trfcr_el1
[^:]*: d5389ec0 mrs x0, pmmir_el1
-[^:]*: d53c1220 mrs x0, trfcr_el2
[^:]*: d51c1220 msr trfcr_el2, x0
-[^:]*: d53d1220 mrs x0, trfcr_el12
+[^:]*: d53c1220 mrs x0, trfcr_el2
[^:]*: d51d1220 msr trfcr_el12, x0
-[^:]*: d53bd200 mrs x0, amcr_el0
+[^:]*: d53d1220 mrs x0, trfcr_el12
[^:]*: d51bd200 msr amcr_el0, x0
+[^:]*: d53bd200 mrs x0, amcr_el0
[^:]*: d53bd220 mrs x0, amcfgr_el0
[^:]*: d53bd240 mrs x0, amcgcr_el0
-[^:]*: d53bd260 mrs x0, amuserenr_el0
[^:]*: d51bd260 msr amuserenr_el0, x0
-[^:]*: d53bd280 mrs x0, amcntenclr0_el0
+[^:]*: d53bd260 mrs x0, amuserenr_el0
[^:]*: d51bd280 msr amcntenclr0_el0, x0
-[^:]*: d53bd2a0 mrs x0, amcntenset0_el0
+[^:]*: d53bd280 mrs x0, amcntenclr0_el0
[^:]*: d51bd2a0 msr amcntenset0_el0, x0
-[^:]*: d53bd300 mrs x0, amcntenclr1_el0
+[^:]*: d53bd2a0 mrs x0, amcntenset0_el0
[^:]*: d51bd300 msr amcntenclr1_el0, x0
-[^:]*: d53bd320 mrs x0, amcntenset1_el0
+[^:]*: d53bd300 mrs x0, amcntenclr1_el0
[^:]*: d51bd320 msr amcntenset1_el0, x0
-[^:]*: d53bd400 mrs x0, amevcntr00_el0
+[^:]*: d53bd320 mrs x0, amcntenset1_el0
[^:]*: d51bd400 msr amevcntr00_el0, x0
-[^:]*: d53bd420 mrs x0, amevcntr01_el0
+[^:]*: d53bd400 mrs x0, amevcntr00_el0
[^:]*: d51bd420 msr amevcntr01_el0, x0
-[^:]*: d53bd440 mrs x0, amevcntr02_el0
+[^:]*: d53bd420 mrs x0, amevcntr01_el0
[^:]*: d51bd440 msr amevcntr02_el0, x0
-[^:]*: d53bd460 mrs x0, amevcntr03_el0
+[^:]*: d53bd440 mrs x0, amevcntr02_el0
[^:]*: d51bd460 msr amevcntr03_el0, x0
+[^:]*: d53bd460 mrs x0, amevcntr03_el0
[^:]*: d53bd600 mrs x0, amevtyper00_el0
[^:]*: d53bd620 mrs x0, amevtyper01_el0
[^:]*: d53bd640 mrs x0, amevtyper02_el0
[^:]*: d53bd660 mrs x0, amevtyper03_el0
-[^:]*: d53bdc00 mrs x0, amevcntr10_el0
[^:]*: d51bdc00 msr amevcntr10_el0, x0
-[^:]*: d53bdc20 mrs x0, amevcntr11_el0
+[^:]*: d53bdc00 mrs x0, amevcntr10_el0
[^:]*: d51bdc20 msr amevcntr11_el0, x0
-[^:]*: d53bdc40 mrs x0, amevcntr12_el0
+[^:]*: d53bdc20 mrs x0, amevcntr11_el0
[^:]*: d51bdc40 msr amevcntr12_el0, x0
-[^:]*: d53bdc60 mrs x0, amevcntr13_el0
+[^:]*: d53bdc40 mrs x0, amevcntr12_el0
[^:]*: d51bdc60 msr amevcntr13_el0, x0
-[^:]*: d53bdc80 mrs x0, amevcntr14_el0
+[^:]*: d53bdc60 mrs x0, amevcntr13_el0
[^:]*: d51bdc80 msr amevcntr14_el0, x0
-[^:]*: d53bdca0 mrs x0, amevcntr15_el0
+[^:]*: d53bdc80 mrs x0, amevcntr14_el0
[^:]*: d51bdca0 msr amevcntr15_el0, x0
-[^:]*: d53bdcc0 mrs x0, amevcntr16_el0
+[^:]*: d53bdca0 mrs x0, amevcntr15_el0
[^:]*: d51bdcc0 msr amevcntr16_el0, x0
-[^:]*: d53bdce0 mrs x0, amevcntr17_el0
+[^:]*: d53bdcc0 mrs x0, amevcntr16_el0
[^:]*: d51bdce0 msr amevcntr17_el0, x0
-[^:]*: d53bdd00 mrs x0, amevcntr18_el0
+[^:]*: d53bdce0 mrs x0, amevcntr17_el0
[^:]*: d51bdd00 msr amevcntr18_el0, x0
-[^:]*: d53bdd20 mrs x0, amevcntr19_el0
+[^:]*: d53bdd00 mrs x0, amevcntr18_el0
[^:]*: d51bdd20 msr amevcntr19_el0, x0
-[^:]*: d53bdd40 mrs x0, amevcntr110_el0
+[^:]*: d53bdd20 mrs x0, amevcntr19_el0
[^:]*: d51bdd40 msr amevcntr110_el0, x0
-[^:]*: d53bdd60 mrs x0, amevcntr111_el0
+[^:]*: d53bdd40 mrs x0, amevcntr110_el0
[^:]*: d51bdd60 msr amevcntr111_el0, x0
-[^:]*: d53bdd80 mrs x0, amevcntr112_el0
+[^:]*: d53bdd60 mrs x0, amevcntr111_el0
[^:]*: d51bdd80 msr amevcntr112_el0, x0
-[^:]*: d53bdda0 mrs x0, amevcntr113_el0
+[^:]*: d53bdd80 mrs x0, amevcntr112_el0
[^:]*: d51bdda0 msr amevcntr113_el0, x0
-[^:]*: d53bddc0 mrs x0, amevcntr114_el0
+[^:]*: d53bdda0 mrs x0, amevcntr113_el0
[^:]*: d51bddc0 msr amevcntr114_el0, x0
-[^:]*: d53bdde0 mrs x0, amevcntr115_el0
+[^:]*: d53bddc0 mrs x0, amevcntr114_el0
[^:]*: d51bdde0 msr amevcntr115_el0, x0
-[^:]*: d53bde00 mrs x0, amevtyper10_el0
+[^:]*: d53bdde0 mrs x0, amevcntr115_el0
[^:]*: d51bde00 msr amevtyper10_el0, x0
-[^:]*: d53bde20 mrs x0, amevtyper11_el0
+[^:]*: d53bde00 mrs x0, amevtyper10_el0
[^:]*: d51bde20 msr amevtyper11_el0, x0
-[^:]*: d53bde40 mrs x0, amevtyper12_el0
+[^:]*: d53bde20 mrs x0, amevtyper11_el0
[^:]*: d51bde40 msr amevtyper12_el0, x0
-[^:]*: d53bde60 mrs x0, amevtyper13_el0
+[^:]*: d53bde40 mrs x0, amevtyper12_el0
[^:]*: d51bde60 msr amevtyper13_el0, x0
-[^:]*: d53bde80 mrs x0, amevtyper14_el0
+[^:]*: d53bde60 mrs x0, amevtyper13_el0
[^:]*: d51bde80 msr amevtyper14_el0, x0
-[^:]*: d53bdea0 mrs x0, amevtyper15_el0
+[^:]*: d53bde80 mrs x0, amevtyper14_el0
[^:]*: d51bdea0 msr amevtyper15_el0, x0
-[^:]*: d53bdec0 mrs x0, amevtyper16_el0
+[^:]*: d53bdea0 mrs x0, amevtyper15_el0
[^:]*: d51bdec0 msr amevtyper16_el0, x0
-[^:]*: d53bdee0 mrs x0, amevtyper17_el0
+[^:]*: d53bdec0 mrs x0, amevtyper16_el0
[^:]*: d51bdee0 msr amevtyper17_el0, x0
-[^:]*: d53bdf00 mrs x0, amevtyper18_el0
+[^:]*: d53bdee0 mrs x0, amevtyper17_el0
[^:]*: d51bdf00 msr amevtyper18_el0, x0
-[^:]*: d53bdf20 mrs x0, amevtyper19_el0
+[^:]*: d53bdf00 mrs x0, amevtyper18_el0
[^:]*: d51bdf20 msr amevtyper19_el0, x0
-[^:]*: d53bdf40 mrs x0, amevtyper110_el0
+[^:]*: d53bdf20 mrs x0, amevtyper19_el0
[^:]*: d51bdf40 msr amevtyper110_el0, x0
-[^:]*: d53bdf60 mrs x0, amevtyper111_el0
+[^:]*: d53bdf40 mrs x0, amevtyper110_el0
[^:]*: d51bdf60 msr amevtyper111_el0, x0
-[^:]*: d53bdf80 mrs x0, amevtyper112_el0
+[^:]*: d53bdf60 mrs x0, amevtyper111_el0
[^:]*: d51bdf80 msr amevtyper112_el0, x0
-[^:]*: d53bdfa0 mrs x0, amevtyper113_el0
+[^:]*: d53bdf80 mrs x0, amevtyper112_el0
[^:]*: d51bdfa0 msr amevtyper113_el0, x0
-[^:]*: d53bdfc0 mrs x0, amevtyper114_el0
+[^:]*: d53bdfa0 mrs x0, amevtyper113_el0
[^:]*: d51bdfc0 msr amevtyper114_el0, x0
-[^:]*: d53bdfe0 mrs x0, amevtyper115_el0
+[^:]*: d53bdfc0 mrs x0, amevtyper114_el0
[^:]*: d51bdfe0 msr amevtyper115_el0, x0
+[^:]*: d53bdfe0 mrs x0, amevtyper115_el0
[^:]*: d53bd2c0 mrs x0, amcg1idr_el0
[^:]*: d53be0a0 mrs x0, cntpctss_el0
[^:]*: d53be0c0 mrs x0, cntvctss_el0
-[^:]*: d53c1180 mrs x0, hfgrtr_el2
[^:]*: d51c1180 msr hfgrtr_el2, x0
-[^:]*: d53c11a0 mrs x0, hfgwtr_el2
+[^:]*: d53c1180 mrs x0, hfgrtr_el2
[^:]*: d51c11a0 msr hfgwtr_el2, x0
-[^:]*: d53c11c0 mrs x0, hfgitr_el2
+[^:]*: d53c11a0 mrs x0, hfgwtr_el2
[^:]*: d51c11c0 msr hfgitr_el2, x0
-[^:]*: d53c3180 mrs x0, hdfgrtr_el2
+[^:]*: d53c11c0 mrs x0, hfgitr_el2
[^:]*: d51c3180 msr hdfgrtr_el2, x0
-[^:]*: d53c31a0 mrs x0, hdfgwtr_el2
+[^:]*: d53c3180 mrs x0, hdfgrtr_el2
[^:]*: d51c31a0 msr hdfgwtr_el2, x0
-[^:]*: d53c31c0 mrs x0, hafgrtr_el2
+[^:]*: d53c31a0 mrs x0, hdfgwtr_el2
[^:]*: d51c31c0 msr hafgrtr_el2, x0
-[^:]*: d53cd800 mrs x0, amevcntvoff00_el2
+[^:]*: d53c31c0 mrs x0, hafgrtr_el2
[^:]*: d51cd800 msr amevcntvoff00_el2, x0
-[^:]*: d53cd820 mrs x0, amevcntvoff01_el2
+[^:]*: d53cd800 mrs x0, amevcntvoff00_el2
[^:]*: d51cd820 msr amevcntvoff01_el2, x0
-[^:]*: d53cd840 mrs x0, amevcntvoff02_el2
+[^:]*: d53cd820 mrs x0, amevcntvoff01_el2
[^:]*: d51cd840 msr amevcntvoff02_el2, x0
-[^:]*: d53cd860 mrs x0, amevcntvoff03_el2
+[^:]*: d53cd840 mrs x0, amevcntvoff02_el2
[^:]*: d51cd860 msr amevcntvoff03_el2, x0
-[^:]*: d53cd880 mrs x0, amevcntvoff04_el2
+[^:]*: d53cd860 mrs x0, amevcntvoff03_el2
[^:]*: d51cd880 msr amevcntvoff04_el2, x0
-[^:]*: d53cd8a0 mrs x0, amevcntvoff05_el2
+[^:]*: d53cd880 mrs x0, amevcntvoff04_el2
[^:]*: d51cd8a0 msr amevcntvoff05_el2, x0
-[^:]*: d53cd8c0 mrs x0, amevcntvoff06_el2
+[^:]*: d53cd8a0 mrs x0, amevcntvoff05_el2
[^:]*: d51cd8c0 msr amevcntvoff06_el2, x0
-[^:]*: d53cd8e0 mrs x0, amevcntvoff07_el2
+[^:]*: d53cd8c0 mrs x0, amevcntvoff06_el2
[^:]*: d51cd8e0 msr amevcntvoff07_el2, x0
-[^:]*: d53cd900 mrs x0, amevcntvoff08_el2
+[^:]*: d53cd8e0 mrs x0, amevcntvoff07_el2
[^:]*: d51cd900 msr amevcntvoff08_el2, x0
-[^:]*: d53cd920 mrs x0, amevcntvoff09_el2
+[^:]*: d53cd900 mrs x0, amevcntvoff08_el2
[^:]*: d51cd920 msr amevcntvoff09_el2, x0
-[^:]*: d53cd940 mrs x0, amevcntvoff010_el2
+[^:]*: d53cd920 mrs x0, amevcntvoff09_el2
[^:]*: d51cd940 msr amevcntvoff010_el2, x0
-[^:]*: d53cd960 mrs x0, amevcntvoff011_el2
+[^:]*: d53cd940 mrs x0, amevcntvoff010_el2
[^:]*: d51cd960 msr amevcntvoff011_el2, x0
-[^:]*: d53cd980 mrs x0, amevcntvoff012_el2
+[^:]*: d53cd960 mrs x0, amevcntvoff011_el2
[^:]*: d51cd980 msr amevcntvoff012_el2, x0
-[^:]*: d53cd9a0 mrs x0, amevcntvoff013_el2
+[^:]*: d53cd980 mrs x0, amevcntvoff012_el2
[^:]*: d51cd9a0 msr amevcntvoff013_el2, x0
-[^:]*: d53cd9c0 mrs x0, amevcntvoff014_el2
+[^:]*: d53cd9a0 mrs x0, amevcntvoff013_el2
[^:]*: d51cd9c0 msr amevcntvoff014_el2, x0
-[^:]*: d53cd9e0 mrs x0, amevcntvoff015_el2
+[^:]*: d53cd9c0 mrs x0, amevcntvoff014_el2
[^:]*: d51cd9e0 msr amevcntvoff015_el2, x0
-[^:]*: d53cda00 mrs x0, amevcntvoff10_el2
+[^:]*: d53cd9e0 mrs x0, amevcntvoff015_el2
[^:]*: d51cda00 msr amevcntvoff10_el2, x0
-[^:]*: d53cda20 mrs x0, amevcntvoff11_el2
+[^:]*: d53cda00 mrs x0, amevcntvoff10_el2
[^:]*: d51cda20 msr amevcntvoff11_el2, x0
-[^:]*: d53cda40 mrs x0, amevcntvoff12_el2
+[^:]*: d53cda20 mrs x0, amevcntvoff11_el2
[^:]*: d51cda40 msr amevcntvoff12_el2, x0
-[^:]*: d53cda60 mrs x0, amevcntvoff13_el2
+[^:]*: d53cda40 mrs x0, amevcntvoff12_el2
[^:]*: d51cda60 msr amevcntvoff13_el2, x0
-[^:]*: d53cda80 mrs x0, amevcntvoff14_el2
+[^:]*: d53cda60 mrs x0, amevcntvoff13_el2
[^:]*: d51cda80 msr amevcntvoff14_el2, x0
-[^:]*: d53cdaa0 mrs x0, amevcntvoff15_el2
+[^:]*: d53cda80 mrs x0, amevcntvoff14_el2
[^:]*: d51cdaa0 msr amevcntvoff15_el2, x0
-[^:]*: d53cdac0 mrs x0, amevcntvoff16_el2
+[^:]*: d53cdaa0 mrs x0, amevcntvoff15_el2
[^:]*: d51cdac0 msr amevcntvoff16_el2, x0
-[^:]*: d53cdae0 mrs x0, amevcntvoff17_el2
+[^:]*: d53cdac0 mrs x0, amevcntvoff16_el2
[^:]*: d51cdae0 msr amevcntvoff17_el2, x0
-[^:]*: d53cdb00 mrs x0, amevcntvoff18_el2
+[^:]*: d53cdae0 mrs x0, amevcntvoff17_el2
[^:]*: d51cdb00 msr amevcntvoff18_el2, x0
-[^:]*: d53cdb20 mrs x0, amevcntvoff19_el2
+[^:]*: d53cdb00 mrs x0, amevcntvoff18_el2
[^:]*: d51cdb20 msr amevcntvoff19_el2, x0
-[^:]*: d53cdb40 mrs x0, amevcntvoff110_el2
+[^:]*: d53cdb20 mrs x0, amevcntvoff19_el2
[^:]*: d51cdb40 msr amevcntvoff110_el2, x0
-[^:]*: d53cdb60 mrs x0, amevcntvoff111_el2
+[^:]*: d53cdb40 mrs x0, amevcntvoff110_el2
[^:]*: d51cdb60 msr amevcntvoff111_el2, x0
-[^:]*: d53cdb80 mrs x0, amevcntvoff112_el2
+[^:]*: d53cdb60 mrs x0, amevcntvoff111_el2
[^:]*: d51cdb80 msr amevcntvoff112_el2, x0
-[^:]*: d53cdba0 mrs x0, amevcntvoff113_el2
+[^:]*: d53cdb80 mrs x0, amevcntvoff112_el2
[^:]*: d51cdba0 msr amevcntvoff113_el2, x0
-[^:]*: d53cdbc0 mrs x0, amevcntvoff114_el2
+[^:]*: d53cdba0 mrs x0, amevcntvoff113_el2
[^:]*: d51cdbc0 msr amevcntvoff114_el2, x0
-[^:]*: d53cdbe0 mrs x0, amevcntvoff115_el2
+[^:]*: d53cdbc0 mrs x0, amevcntvoff114_el2
[^:]*: d51cdbe0 msr amevcntvoff115_el2, x0
-[^:]*: d53ce0c0 mrs x0, cntpoff_el2
+[^:]*: d53cdbe0 mrs x0, amevcntvoff115_el2
[^:]*: d51ce0c0 msr cntpoff_el2, x0
-[^:]*: d5389920 mrs x0, pmsnevfr_el1
+[^:]*: d53ce0c0 mrs x0, cntpoff_el2
[^:]*: d5189920 msr pmsnevfr_el1, x0
-[^:]*: d53c1240 mrs x0, hcrx_el2
+[^:]*: d5389920 mrs x0, pmsnevfr_el1
[^:]*: d51c1240 msr hcrx_el2, x0
-[^:]*: d538d0c0 mrs x0, rcwmask_el1
+[^:]*: d53c1240 mrs x0, hcrx_el2
[^:]*: d518d0c0 msr rcwmask_el1, x0
-[^:]*: d538d060 mrs x0, rcwsmask_el1
+[^:]*: d538d0c0 mrs x0, rcwmask_el1
[^:]*: d518d060 msr rcwsmask_el1, x0
+[^:]*: d538d060 mrs x0, rcwsmask_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s
index bf555d23b82..04bd30d08d1 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s
@@ -7,8 +7,8 @@
.endm
.macro rwreg, name
- mrs x0, \name
msr \name, x0
+ mrs x0, \name
.endm
roreg id_dfr1_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
index 90b5be3cabf..6dfad54a72c 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
@@ -24,12 +24,12 @@ Disassembly of section \.text:
.*: d5380260 mrs x0, id_isar3_el1
.*: d5380280 mrs x0, id_isar4_el1
.*: d53802a0 mrs x0, id_isar5_el1
-.*: d538cf00 mrs x0, s3_0_c12_c15_0
-.*: d5384b00 mrs x0, s3_0_c4_c11_0
-.*: d5184b00 msr s3_0_c4_c11_0, x0
-.*: d5310300 mrs x0, trcstatr
-.*: d5110300 msr trcstatr, x0
.*: d5380640 mrs x0, id_aa64isar2_el1
.*: d538065e mrs x30, id_aa64isar2_el1
.*: d5380660 mrs x0, id_aa64isar3_el1
.*: d538067e mrs x30, id_aa64isar3_el1
+.*: d538cf00 mrs x0, s3_0_c12_c15_0
+.*: d5184b00 msr s3_0_c4_c11_0, x0
+.*: d5384b00 mrs x0, s3_0_c4_c11_0
+.*: d5110300 msr trcstatr, x0
+.*: d5310300 mrs x0, trcstatr
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.s b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
index a3f5b793620..998f31596bd 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
@@ -24,15 +24,15 @@
mrs x0, id_isar4_el1
mrs x0, id_isar5_el1
- mrs x0, s3_0_c12_c15_0
- mrs x0, s3_0_c4_c11_0
- msr s3_0_c4_c11_0, x0
-
- mrs x0, s2_1_c0_c3_0
- msr s2_1_c0_c3_0, x0
-
mrs x0, id_aa64isar2_el1
mrs x30, id_aa64isar2_el1
mrs x0, id_aa64isar3_el1
mrs x30, id_aa64isar3_el1
+
+ mrs x0, s3_0_c12_c15_0
+ msr s3_0_c4_c11_0, x0
+ mrs x0, s3_0_c4_c11_0
+
+ msr s2_1_c0_c3_0, x0
+ mrs x0, s2_1_c0_c3_0
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg128.d b/gas/testsuite/gas/aarch64/sysreg/sysreg128.d
index cb895c64503..2998c7b79a2 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg128.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg128.d
@@ -6,23 +6,23 @@
Disassembly of section \.text:
0+ <\.text>:
-[^:]*: d5787402 mrrs x2, x3, par_el1
[^:]*: d5587402 msrr par_el1, x2, x3
-[^:]*: d578d0c2 mrrs x2, x3, rcwmask_el1
+[^:]*: d5787402 mrrs x2, x3, par_el1
[^:]*: d558d0c2 msrr rcwmask_el1, x2, x3
-[^:]*: d578d062 mrrs x2, x3, rcwsmask_el1
+[^:]*: d578d0c2 mrrs x2, x3, rcwmask_el1
[^:]*: d558d062 msrr rcwsmask_el1, x2, x3
-[^:]*: d5782002 mrrs x2, x3, ttbr0_el1
+[^:]*: d578d062 mrrs x2, x3, rcwsmask_el1
[^:]*: d5582002 msrr ttbr0_el1, x2, x3
-[^:]*: d57d2002 mrrs x2, x3, ttbr0_el12
+[^:]*: d5782002 mrrs x2, x3, ttbr0_el1
[^:]*: d55d2002 msrr ttbr0_el12, x2, x3
-[^:]*: d57c2002 mrrs x2, x3, ttbr0_el2
+[^:]*: d57d2002 mrrs x2, x3, ttbr0_el12
[^:]*: d55c2002 msrr ttbr0_el2, x2, x3
-[^:]*: d5782022 mrrs x2, x3, ttbr1_el1
+[^:]*: d57c2002 mrrs x2, x3, ttbr0_el2
[^:]*: d5582022 msrr ttbr1_el1, x2, x3
-[^:]*: d57d2022 mrrs x2, x3, ttbr1_el12
+[^:]*: d5782022 mrrs x2, x3, ttbr1_el1
[^:]*: d55d2022 msrr ttbr1_el12, x2, x3
-[^:]*: d57c2022 mrrs x2, x3, ttbr1_el2
+[^:]*: d57d2022 mrrs x2, x3, ttbr1_el12
[^:]*: d55c2022 msrr ttbr1_el2, x2, x3
-[^:]*: d57c2102 mrrs x2, x3, vttbr_el2
-[^:]*: d55c2102 msrr vttbr_el2, x2, x3
\ No newline at end of file
+[^:]*: d57c2022 mrrs x2, x3, ttbr1_el2
+[^:]*: d55c2102 msrr vttbr_el2, x2, x3
+[^:]*: d57c2102 mrrs x2, x3, vttbr_el2
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg128.s b/gas/testsuite/gas/aarch64/sysreg/sysreg128.s
index 09c9dace9b5..ee1d7cda3fa 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg128.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg128.s
@@ -1,8 +1,8 @@
.arch armv9.4-a+d128+the
.macro rwreg128, name
- mrrs x2, x3, \name
msrr \name, x2, x3
+ mrrs x2, x3, \name
.endm
rwreg128 par_el1
next prev parent reply other threads:[~2024-02-27 11:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-27 10:59 [PATCH v1 0/4][Binutils] aarch64: testsuite: refactoring of some tests to share test macros Matthieu Longo
2024-02-27 10:59 ` [PATCH v1 1/4] aarch64: testsuite: replace instruction addresses by regex Matthieu Longo
2024-05-10 10:34 ` Richard Earnshaw (lists)
2024-02-27 10:59 ` [PATCH v1 2/4] aarch64: testsuite: use same regs for read and write tests Matthieu Longo
2024-05-10 10:37 ` Richard Earnshaw (lists)
2024-02-27 10:59 ` Matthieu Longo [this message]
2024-05-10 10:40 ` [PATCH v1 3/4] aarch64: testsuite: reorder write and read to match macro order Richard Earnshaw (lists)
2024-02-27 10:59 ` [PATCH v1 4/4] aarch64: testsuite: share test utils macros and use them Matthieu Longo
2024-02-27 16:31 ` Andrew Carlotti
2024-03-01 10:10 ` Matthieu Longo
2024-03-04 14:43 ` Andrew Carlotti
2024-05-10 10:34 ` Richard Earnshaw (lists)
2024-05-10 10:42 ` Richard Earnshaw (lists)
2024-04-24 10:48 ` [PATCH v1 0/4][Binutils] aarch64: testsuite: refactoring of some tests to share test macros Matthieu Longo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240227105917.295899-4-matthieu.longo@arm.com \
--to=matthieu.longo@arm.com \
--cc=binutils@sourceware.org \
--cc=nickc@redhat.com \
--cc=richard.earnshaw@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).