[PATCH 00/11] aarch64: New feature flags and flag fixes

[PATCH 00/11] aarch64: New feature flags and flag fixes

[Andrew Carlotti]

This patch series adds new feature flags for instructions that are already
present in Binutils, to allow the instructions to be enabled without specifying
a higher architecture version.  With the exception of patch 11/11 (cleaning up
dead code), each patch is independent of the others.

Aside from adding new feature flags (or otherwise eliminating architecture
version dependencies), there are also three small bug fixes, in patches 1/11,
3/11 and 9/11.

I have run the tests affected by each commit after that commit, and I have also
run the entire testsuite on the series as a whole, with no test failures.  Is
this ok for master?  I don't have write access, so will need help to commit
these.

[PATCH 01/11] aarch64: Fix +lse feature flag dependency

[Andrew Carlotti]

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 6d8c3566008d322253e46220cc039fbaa8c20bb3..94b35ecadcc7fd3f6ba8aa8cec2a465eef8c52a1 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10268,7 +10268,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_FEATURE (SIMD)},
   {"fp",		AARCH64_FEATURE (FP), AARCH64_NO_FEATURES},
   {"lse",		AARCH64_FEATURE (LSE), AARCH64_NO_FEATURES},
-  {"lse128",		AARCH64_FEATURES (2, LSE, LSE128), AARCH64_NO_FEATURES},
+  {"lse128",		AARCH64_FEATURE (LSE128), AARCH64_FEATURE (LSE)},
   {"simd",		AARCH64_FEATURE (SIMD), AARCH64_FEATURE (FP)},
   {"pan",		AARCH64_FEATURE (PAN), AARCH64_NO_FEATURES},
   {"lor",		AARCH64_FEATURE (LOR), AARCH64_NO_FEATURES},

[PATCH 02/11] aarch64: Add +fcma alias for +compnum

[Andrew Carlotti]

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 94b35ecadcc7fd3f6ba8aa8cec2a465eef8c52a1..6b11c4e3368c25fa5bc176d5282a5804a2174db9 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10279,6 +10279,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"profile",		AARCH64_FEATURE (PROFILE), AARCH64_NO_FEATURES},
   {"sve",		AARCH64_FEATURE (SVE), AARCH64_FEATURE (COMPNUM)},
   {"tme",		AARCH64_FEATURE (TME), AARCH64_NO_FEATURES},
+  {"fcma",		AARCH64_FEATURE (COMPNUM),
+			AARCH64_FEATURES (2, F16, SIMD)},
   {"compnum",		AARCH64_FEATURE (COMPNUM),
 			AARCH64_FEATURES (2, F16, SIMD)},
   {"rcpc",		AARCH64_FEATURE (RCPC), AARCH64_NO_FEATURES},
diff --git a/gas/testsuite/gas/aarch64/advsimd-compnum.d b/gas/testsuite/gas/aarch64/advsimd-compnum.d
index 821508e1de6cc790307fde039b9737d170d6c035..29e7f8a1eb27a84579d8914a5b2c0113c07f8f80 100644
--- a/gas/testsuite/gas/aarch64/advsimd-compnum.d
+++ b/gas/testsuite/gas/aarch64/advsimd-compnum.d
@@ -1,4 +1,5 @@
 #as: -march=armv8.2-a+compnum -I$srcdir/$subdir
+#as: -march=armv8.2-a+fcma -I$srcdir/$subdir
 #objdump: -dr
 
 .*:     file format .*

[PATCH 03/11] aarch64: Fix option parsing to disallow prefixes of valid options

[Andrew Carlotti]

Add "+rdm" as an explicit alias for "+rdma", to maintain existing compatibility
with Clang.


diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 6b11c4e3368c25fa5bc176d5282a5804a2174db9..c2f77a40ef225efc6998855885ae0d0757a86479 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10274,6 +10274,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"lor",		AARCH64_FEATURE (LOR), AARCH64_NO_FEATURES},
   {"ras",		AARCH64_FEATURE (RAS), AARCH64_NO_FEATURES},
   {"rdma",		AARCH64_FEATURE (RDMA), AARCH64_FEATURE (SIMD)},
+  {"rdm",		AARCH64_FEATURE (RDMA), AARCH64_FEATURE (SIMD)},
   {"fp16",		AARCH64_FEATURE (F16), AARCH64_FEATURE (FP)},
   {"fp16fml",		AARCH64_FEATURE (F16_FML), AARCH64_FEATURE (F16)},
   {"profile",		AARCH64_FEATURE (PROFILE), AARCH64_NO_FEATURES},
@@ -10438,7 +10439,8 @@ aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p,
       gas_assert (adding_value != -1);
 
       for (opt = aarch64_features; opt->name != NULL; opt++)
-	if (strncmp (opt->name, str, optlen) == 0)
+	if (optlen == (int) strlen(opt->name)
+	    && strncmp (opt->name, str, optlen) == 0)
 	  {
 	    aarch64_feature_set set;
 
diff --git a/gas/testsuite/gas/aarch64/opt-invalid.d b/gas/testsuite/gas/aarch64/opt-invalid.d
new file mode 100644
index 0000000000000000000000000000000000000000..500c68ad3497792f7b9d336b2c0674ef8844d30a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/opt-invalid.d
@@ -0,0 +1 @@
+#error: .*: Error: unknown architectural extension `s'
diff --git a/gas/testsuite/gas/aarch64/opt-invalid.s b/gas/testsuite/gas/aarch64/opt-invalid.s
new file mode 100644
index 0000000000000000000000000000000000000000..058d4c1c8895f5f7aace9747c8cf2de09b633427
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/opt-invalid.s
@@ -0,0 +1 @@
+.arch armv8-a+s
diff --git a/gas/testsuite/gas/aarch64/rdma.d b/gas/testsuite/gas/aarch64/rdma.d
index d634909c21d2b614366667b1095ef64bddfdd583..b506d7d89357e54457018ab8a08445687b906eac 100644
--- a/gas/testsuite/gas/aarch64/rdma.d
+++ b/gas/testsuite/gas/aarch64/rdma.d
@@ -1,5 +1,6 @@
 #objdump: -dr
 #as: -march=armv8-a+rdma
+#as: -march=armv8-a+rdm
 
 .*:     file format .*
 

[PATCH 04/11] aarch64: Add +jscvt flag for existing fjcvtzs instruction

[Andrew Carlotti]

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c2f77a40ef225efc6998855885ae0d0757a86479..b77b160fe1f95409afaed399e6aaf8888476d912 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10284,6 +10284,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_FEATURES (2, F16, SIMD)},
   {"compnum",		AARCH64_FEATURE (COMPNUM),
 			AARCH64_FEATURES (2, F16, SIMD)},
+  {"jscvt",		AARCH64_FEATURE (JSCVT), AARCH64_FEATURE (FP)},
   {"rcpc",		AARCH64_FEATURE (RCPC), AARCH64_NO_FEATURES},
   {"dotprod",		AARCH64_FEATURE (DOTPROD), AARCH64_FEATURE (SIMD)},
   {"sha2",		AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)},
diff --git a/gas/testsuite/gas/aarch64/fp-armv8_3.d b/gas/testsuite/gas/aarch64/fp-armv8_3.d
index dd37a1180f29e38242e85052a13722e08d0ea861..a502c582b12e4c0866bda39b94ded34dd11b6701 100644
--- a/gas/testsuite/gas/aarch64/fp-armv8_3.d
+++ b/gas/testsuite/gas/aarch64/fp-armv8_3.d
@@ -1,5 +1,6 @@
 #objdump: -dr
 #as: -march=armv8.3-a
+#as: -march=armv8-a+jscvt
 
 .*:     file .*
 
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 95fe50249871ecff0dbffc920a041b39eedb1516..eb42b87a00263cfa633e4bd6c35fd912941a15a8 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -99,6 +99,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_RCPC,
   /* Complex # instructions.  */
   AARCH64_FEATURE_COMPNUM,
+  /* JavaScript conversion instructions.  */
+  AARCH64_FEATURE_JSCVT,
   /* Dot Product instructions.  */
   AARCH64_FEATURE_DOTPROD,
   /* SM3 & SM4 instructions.  */
@@ -246,7 +248,8 @@ enum aarch64_feature_bit {
 #define AARCH64_ARCH_V8_3A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_3A)	\
 					 | AARCH64_FEATBIT (X, PAC)	\
 					 | AARCH64_FEATBIT (X, RCPC)	\
-					 | AARCH64_FEATBIT (X, COMPNUM))
+					 | AARCH64_FEATBIT (X, COMPNUM) \
+					 | AARCH64_FEATBIT (X, JSCVT))
 #define AARCH64_ARCH_V8_4A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_4A)	\
 					 | AARCH64_FEATBIT (X, DOTPROD)	\
 					 | AARCH64_FEATBIT (X, FLAGM)	\
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 2ddeca99d0bff80869216368f5f0f47cea5ae99f..007bf018af89c4bc74e59bc70e8560caacb3eac7 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2518,6 +2518,8 @@ static const aarch64_feature_set aarch64_feature_pac =
   AARCH64_FEATURE (PAC);
 static const aarch64_feature_set aarch64_feature_compnum =
   AARCH64_FEATURE (COMPNUM);
+static const aarch64_feature_set aarch64_feature_jscvt =
+  AARCH64_FEATURE (JSCVT);
 static const aarch64_feature_set aarch64_feature_rcpc =
   AARCH64_FEATURE (RCPC);
 static const aarch64_feature_set aarch64_feature_dotprod =
@@ -2631,6 +2633,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
 #define FP_V8_3A	&aarch64_feature_fp_v8_3a
 #define PAC		&aarch64_feature_pac
 #define COMPNUM		&aarch64_feature_compnum
+#define JSCVT		&aarch64_feature_jscvt
 #define RCPC		&aarch64_feature_rcpc
 #define SHA2		&aarch64_feature_sha2
 #define AES		&aarch64_feature_aes
@@ -2717,6 +2720,8 @@ static const aarch64_feature_set aarch64_feature_d128_the =
   { NAME, OPCODE, MASK, CLASS, 0, PAC, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define JSCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, JSCVT, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -3741,7 +3746,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
   __FP_INSN ("fmov",  0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0),
   __FP_INSN ("fmov",  0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0),
-  {"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3A, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, 0, NULL },
+  JSCVT_INSN ("fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_W_D, 0),
   /* Floating-point conditional compare.  */
   __FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE),
   FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE),

[PATCH 05/11] aarch64: Add +frintts flag for existing instructions

[Andrew Carlotti]

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index b77b160fe1f95409afaed399e6aaf8888476d912..9df0e3b8d324abdcd47b788dc5d59eab56ef9aa3 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10288,6 +10288,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"rcpc",		AARCH64_FEATURE (RCPC), AARCH64_NO_FEATURES},
   {"dotprod",		AARCH64_FEATURE (DOTPROD), AARCH64_FEATURE (SIMD)},
   {"sha2",		AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)},
+  {"frintts",		AARCH64_FEATURE (FRINTTS), AARCH64_FEATURE (SIMD)},
   {"sb",		AARCH64_FEATURE (SB), AARCH64_NO_FEATURES},
   {"predres",		AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES},
   {"predres2",		AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)},
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-dp.d b/gas/testsuite/gas/aarch64/armv8_5-a-frintts.d
similarity index 94%
rename from gas/testsuite/gas/aarch64/armv8_5-a-dp.d
rename to gas/testsuite/gas/aarch64/armv8_5-a-frintts.d
index d0667543f94ddc6fe2767895134ea1d15d7717e8..5bc98fc6ff98c5d099e2858fdd5a0e0810be2b06 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-dp.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-frintts.d
@@ -1,4 +1,5 @@
 #as: -march=armv8.5-a
+#as: -march=armv8-a+frintts
 # objdump: -d
 
 .*: .*
@@ -7,8 +8,6 @@
 Disassembly of section \.text:
 
 0+0 <func>:
-.*:	d500403f 	xaflag
-.*:	d500405f 	axflag
 .*:	1e284041 	frint32z	s1, s2
 .*:	1e684062 	frint32z	d2, d3
 .*:	1e28c041 	frint32x	s1, s2
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-dp.s b/gas/testsuite/gas/aarch64/armv8_5-a-frintts.s
similarity index 94%
rename from gas/testsuite/gas/aarch64/armv8_5-a-dp.s
rename to gas/testsuite/gas/aarch64/armv8_5-a-frintts.s
index ecc924460fdc24119f1815e9a8645980f35d814e..96d800700a7fd1a78b528a360c3268d32068fa09 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-dp.s
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-frintts.s
@@ -13,7 +13,5 @@
 	.endr
 	.endm
 func:
-	xaflag
-	axflag
 	expand frint,0
 	expand frint,1
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-flagm2.d b/gas/testsuite/gas/aarch64/armv8_5-a-flagm2.d
new file mode 100644
index 0000000000000000000000000000000000000000..83361e0c0b58d742f9b883d4a9a56e39eb4dbdca
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-flagm2.d
@@ -0,0 +1,11 @@
+#as: -march=armv8.5-a
+# objdump: -d
+
+.*: .*
+
+
+Disassembly of section \.text:
+
+0+0 <func>:
+.*:	d500403f 	xaflag
+.*:	d500405f 	axflag
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-flagm2.s b/gas/testsuite/gas/aarch64/armv8_5-a-flagm2.s
new file mode 100644
index 0000000000000000000000000000000000000000..7e7929ceb637e1d707dcb14a7cc8f90acd478e00
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-flagm2.s
@@ -0,0 +1,3 @@
+func:
+	xaflag
+	axflag

[PATCH 06/11] aarch64: Add +flagm2 flag for existing instructions

[Andrew Carlotti]

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 9df0e3b8d324abdcd47b788dc5d59eab56ef9aa3..63c649a2fad29d198a822ec145fb6d20f11f57c5 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10320,6 +10320,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"f64mm",		AARCH64_FEATURE (F64MM), AARCH64_FEATURE (SVE)},
   {"ls64",		AARCH64_FEATURE (LS64), AARCH64_NO_FEATURES},
   {"flagm",		AARCH64_FEATURE (FLAGM), AARCH64_NO_FEATURES},
+  {"flagm2",		AARCH64_FEATURE (FLAGMANIP), AARCH64_FEATURE (FLAGM)},
   {"pauth",		AARCH64_FEATURE (PAC), AARCH64_NO_FEATURES},
   {"mops",		AARCH64_FEATURE (MOPS), AARCH64_NO_FEATURES},
   {"hbc",		AARCH64_FEATURE (HBC), AARCH64_NO_FEATURES},
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-flagm2.d b/gas/testsuite/gas/aarch64/armv8_5-a-flagm2.d
index 83361e0c0b58d742f9b883d4a9a56e39eb4dbdca..84144c032e5c5d0b37adda9a379c75e9c1f20b27 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-flagm2.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-flagm2.d
@@ -1,4 +1,5 @@
 #as: -march=armv8.5-a
+#as: -march=armv8-a+flagm2
 # objdump: -d
 
 .*: .*

[PATCH 07/11] aarch64: Add +rcpc2 flag for existing instructions

[Andrew Carlotti]

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 63c649a2fad29d198a822ec145fb6d20f11f57c5..df71e67a5a68047d70abe65d8f178fdfae114306 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10286,6 +10286,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_FEATURES (2, F16, SIMD)},
   {"jscvt",		AARCH64_FEATURE (JSCVT), AARCH64_FEATURE (FP)},
   {"rcpc",		AARCH64_FEATURE (RCPC), AARCH64_NO_FEATURES},
+  {"rcpc2",		AARCH64_FEATURE (RCPC2), AARCH64_FEATURE (RCPC)},
   {"dotprod",		AARCH64_FEATURE (DOTPROD), AARCH64_FEATURE (SIMD)},
   {"sha2",		AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)},
   {"frintts",		AARCH64_FEATURE (FRINTTS), AARCH64_FEATURE (SIMD)},
diff --git a/gas/testsuite/gas/aarch64/armv8_4-a.d b/gas/testsuite/gas/aarch64/armv8_4-a.d
index 4b1a4e37757b63755903b61b2ef3e194ffd54994..ae0a27f0b4bc4b7682a59fe078e04464adcc17fd 100644
--- a/gas/testsuite/gas/aarch64/armv8_4-a.d
+++ b/gas/testsuite/gas/aarch64/armv8_4-a.d
@@ -2202,4 +2202,4 @@ Disassembly of section \.text:
 [^:]+:\s+998033fe 	ldapursw	x30, \[sp, #3\]
 [^:]+:\s+998523fe 	ldapursw	x30, \[sp, #82\]
 [^:]+:\s+9980d3fe 	ldapursw	x30, \[sp, #13\]
-[^:]+:\s+d500401f 	cfinv
\ No newline at end of file
+[^:]+:\s+d500401f 	cfinv
diff --git a/gas/testsuite/gas/aarch64/rcpc2.d b/gas/testsuite/gas/aarch64/rcpc2.d
new file mode 100644
index 0000000000000000000000000000000000000000..3de4be7b347ad91001b7138cab0ffd34f3c42f39
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc2.d
@@ -0,0 +1,2088 @@
+#as: -march=armv8-a+rcpc2
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+:\s+19000060 	stlurb	w0, \[x3\]
+[^:]+:\s+19000160 	stlurb	w0, \[x11\]
+[^:]+:\s+190001e0 	stlurb	w0, \[x15\]
+[^:]+:\s+19000068 	stlurb	w8, \[x3\]
+[^:]+:\s+19000168 	stlurb	w8, \[x11\]
+[^:]+:\s+190001e8 	stlurb	w8, \[x15\]
+[^:]+:\s+1900006c 	stlurb	w12, \[x3\]
+[^:]+:\s+1900016c 	stlurb	w12, \[x11\]
+[^:]+:\s+190001ec 	stlurb	w12, \[x15\]
+[^:]+:\s+19000060 	stlurb	w0, \[x3\]
+[^:]+:\s+19000160 	stlurb	w0, \[x11\]
+[^:]+:\s+190001e0 	stlurb	w0, \[x15\]
+[^:]+:\s+19000068 	stlurb	w8, \[x3\]
+[^:]+:\s+19000168 	stlurb	w8, \[x11\]
+[^:]+:\s+190001e8 	stlurb	w8, \[x15\]
+[^:]+:\s+1900006c 	stlurb	w12, \[x3\]
+[^:]+:\s+1900016c 	stlurb	w12, \[x11\]
+[^:]+:\s+190001ec 	stlurb	w12, \[x15\]
+[^:]+:\s+19000060 	stlurb	w0, \[x3\]
+[^:]+:\s+19000160 	stlurb	w0, \[x11\]
+[^:]+:\s+190001e0 	stlurb	w0, \[x15\]
+[^:]+:\s+19000068 	stlurb	w8, \[x3\]
+[^:]+:\s+19000168 	stlurb	w8, \[x11\]
+[^:]+:\s+190001e8 	stlurb	w8, \[x15\]
+[^:]+:\s+1900006c 	stlurb	w12, \[x3\]
+[^:]+:\s+1900016c 	stlurb	w12, \[x11\]
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+[^:]+:\s+9900b11e 	stlur	w30, \[x8, #11\]
+[^:]+:\s+9900f11e 	stlur	w30, \[x8, #15\]
+[^:]+:\s+9900319e 	stlur	w30, \[x12, #3\]
+[^:]+:\s+9900b19e 	stlur	w30, \[x12, #11\]
+[^:]+:\s+9900f19e 	stlur	w30, \[x12, #15\]
+[^:]+:\s+990033e0 	stlur	w0, \[sp, #3\]
+[^:]+:\s+990523e0 	stlur	w0, \[sp, #82\]
+[^:]+:\s+9900d3e0 	stlur	w0, \[sp, #13\]
+[^:]+:\s+990033e7 	stlur	w7, \[sp, #3\]
+[^:]+:\s+990523e7 	stlur	w7, \[sp, #82\]
+[^:]+:\s+9900d3e7 	stlur	w7, \[sp, #13\]
+[^:]+:\s+990033f0 	stlur	w16, \[sp, #3\]
+[^:]+:\s+990523f0 	stlur	w16, \[sp, #82\]
+[^:]+:\s+9900d3f0 	stlur	w16, \[sp, #13\]
+[^:]+:\s+990033fe 	stlur	w30, \[sp, #3\]
+[^:]+:\s+990523fe 	stlur	w30, \[sp, #82\]
+[^:]+:\s+9900d3fe 	stlur	w30, \[sp, #13\]
+[^:]+:\s+d9000060 	stlur	x0, \[x3\]
+[^:]+:\s+d9000160 	stlur	x0, \[x11\]
+[^:]+:\s+d90001e0 	stlur	x0, \[x15\]
+[^:]+:\s+d9000068 	stlur	x8, \[x3\]
+[^:]+:\s+d9000168 	stlur	x8, \[x11\]
+[^:]+:\s+d90001e8 	stlur	x8, \[x15\]
+[^:]+:\s+d900006c 	stlur	x12, \[x3\]
+[^:]+:\s+d900016c 	stlur	x12, \[x11\]
+[^:]+:\s+d90001ec 	stlur	x12, \[x15\]
+[^:]+:\s+d9000060 	stlur	x0, \[x3\]
+[^:]+:\s+d9000160 	stlur	x0, \[x11\]
+[^:]+:\s+d90001e0 	stlur	x0, \[x15\]
+[^:]+:\s+d9000068 	stlur	x8, \[x3\]
+[^:]+:\s+d9000168 	stlur	x8, \[x11\]
+[^:]+:\s+d90001e8 	stlur	x8, \[x15\]
+[^:]+:\s+d900006c 	stlur	x12, \[x3\]
+[^:]+:\s+d900016c 	stlur	x12, \[x11\]
+[^:]+:\s+d90001ec 	stlur	x12, \[x15\]
+[^:]+:\s+d9000060 	stlur	x0, \[x3\]
+[^:]+:\s+d9000160 	stlur	x0, \[x11\]
+[^:]+:\s+d90001e0 	stlur	x0, \[x15\]
+[^:]+:\s+d9000068 	stlur	x8, \[x3\]
+[^:]+:\s+d9000168 	stlur	x8, \[x11\]
+[^:]+:\s+d90001e8 	stlur	x8, \[x15\]
+[^:]+:\s+d900006c 	stlur	x12, \[x3\]
+[^:]+:\s+d900016c 	stlur	x12, \[x11\]
+[^:]+:\s+d90001ec 	stlur	x12, \[x15\]
+[^:]+:\s+d9000060 	stlur	x0, \[x3\]
+[^:]+:\s+d9000160 	stlur	x0, \[x11\]
+[^:]+:\s+d90001e0 	stlur	x0, \[x15\]
+[^:]+:\s+d9000068 	stlur	x8, \[x3\]
+[^:]+:\s+d9000168 	stlur	x8, \[x11\]
+[^:]+:\s+d90001e8 	stlur	x8, \[x15\]
+[^:]+:\s+d900006c 	stlur	x12, \[x3\]
+[^:]+:\s+d900016c 	stlur	x12, \[x11\]
+[^:]+:\s+d90001ec 	stlur	x12, \[x15\]
+[^:]+:\s+d90003e0 	stlur	x0, \[sp\]
+[^:]+:\s+d90003e7 	stlur	x7, \[sp\]
+[^:]+:\s+d90003f0 	stlur	x16, \[sp\]
+[^:]+:\s+d90003fe 	stlur	x30, \[sp\]
+[^:]+:\s+d9003002 	stlur	x2, \[x0, #3\]
+[^:]+:\s+d900b002 	stlur	x2, \[x0, #11\]
+[^:]+:\s+d900f002 	stlur	x2, \[x0, #15\]
+[^:]+:\s+d9003102 	stlur	x2, \[x8, #3\]
+[^:]+:\s+d900b102 	stlur	x2, \[x8, #11\]
+[^:]+:\s+d900f102 	stlur	x2, \[x8, #15\]
+[^:]+:\s+d9003182 	stlur	x2, \[x12, #3\]
+[^:]+:\s+d900b182 	stlur	x2, \[x12, #11\]
+[^:]+:\s+d900f182 	stlur	x2, \[x12, #15\]
+[^:]+:\s+d900300f 	stlur	x15, \[x0, #3\]
+[^:]+:\s+d900b00f 	stlur	x15, \[x0, #11\]
+[^:]+:\s+d900f00f 	stlur	x15, \[x0, #15\]
+[^:]+:\s+d900310f 	stlur	x15, \[x8, #3\]
+[^:]+:\s+d900b10f 	stlur	x15, \[x8, #11\]
+[^:]+:\s+d900f10f 	stlur	x15, \[x8, #15\]
+[^:]+:\s+d900318f 	stlur	x15, \[x12, #3\]
+[^:]+:\s+d900b18f 	stlur	x15, \[x12, #11\]
+[^:]+:\s+d900f18f 	stlur	x15, \[x12, #15\]
+[^:]+:\s+d900301e 	stlur	x30, \[x0, #3\]
+[^:]+:\s+d900b01e 	stlur	x30, \[x0, #11\]
+[^:]+:\s+d900f01e 	stlur	x30, \[x0, #15\]
+[^:]+:\s+d900311e 	stlur	x30, \[x8, #3\]
+[^:]+:\s+d900b11e 	stlur	x30, \[x8, #11\]
+[^:]+:\s+d900f11e 	stlur	x30, \[x8, #15\]
+[^:]+:\s+d900319e 	stlur	x30, \[x12, #3\]
+[^:]+:\s+d900b19e 	stlur	x30, \[x12, #11\]
+[^:]+:\s+d900f19e 	stlur	x30, \[x12, #15\]
+[^:]+:\s+d9003002 	stlur	x2, \[x0, #3\]
+[^:]+:\s+d900b002 	stlur	x2, \[x0, #11\]
+[^:]+:\s+d900f002 	stlur	x2, \[x0, #15\]
+[^:]+:\s+d9003102 	stlur	x2, \[x8, #3\]
+[^:]+:\s+d900b102 	stlur	x2, \[x8, #11\]
+[^:]+:\s+d900f102 	stlur	x2, \[x8, #15\]
+[^:]+:\s+d9003182 	stlur	x2, \[x12, #3\]
+[^:]+:\s+d900b182 	stlur	x2, \[x12, #11\]
+[^:]+:\s+d900f182 	stlur	x2, \[x12, #15\]
+[^:]+:\s+d900300f 	stlur	x15, \[x0, #3\]
+[^:]+:\s+d900b00f 	stlur	x15, \[x0, #11\]
+[^:]+:\s+d900f00f 	stlur	x15, \[x0, #15\]
+[^:]+:\s+d900310f 	stlur	x15, \[x8, #3\]
+[^:]+:\s+d900b10f 	stlur	x15, \[x8, #11\]
+[^:]+:\s+d900f10f 	stlur	x15, \[x8, #15\]
+[^:]+:\s+d900318f 	stlur	x15, \[x12, #3\]
+[^:]+:\s+d900b18f 	stlur	x15, \[x12, #11\]
+[^:]+:\s+d900f18f 	stlur	x15, \[x12, #15\]
+[^:]+:\s+d900301e 	stlur	x30, \[x0, #3\]
+[^:]+:\s+d900b01e 	stlur	x30, \[x0, #11\]
+[^:]+:\s+d900f01e 	stlur	x30, \[x0, #15\]
+[^:]+:\s+d900311e 	stlur	x30, \[x8, #3\]
+[^:]+:\s+d900b11e 	stlur	x30, \[x8, #11\]
+[^:]+:\s+d900f11e 	stlur	x30, \[x8, #15\]
+[^:]+:\s+d900319e 	stlur	x30, \[x12, #3\]
+[^:]+:\s+d900b19e 	stlur	x30, \[x12, #11\]
+[^:]+:\s+d900f19e 	stlur	x30, \[x12, #15\]
+[^:]+:\s+d9003002 	stlur	x2, \[x0, #3\]
+[^:]+:\s+d900b002 	stlur	x2, \[x0, #11\]
+[^:]+:\s+d900f002 	stlur	x2, \[x0, #15\]
+[^:]+:\s+d9003102 	stlur	x2, \[x8, #3\]
+[^:]+:\s+d900b102 	stlur	x2, \[x8, #11\]
+[^:]+:\s+d900f102 	stlur	x2, \[x8, #15\]
+[^:]+:\s+d9003182 	stlur	x2, \[x12, #3\]
+[^:]+:\s+d900b182 	stlur	x2, \[x12, #11\]
+[^:]+:\s+d900f182 	stlur	x2, \[x12, #15\]
+[^:]+:\s+d900300f 	stlur	x15, \[x0, #3\]
+[^:]+:\s+d900b00f 	stlur	x15, \[x0, #11\]
+[^:]+:\s+d900f00f 	stlur	x15, \[x0, #15\]
+[^:]+:\s+d900310f 	stlur	x15, \[x8, #3\]
+[^:]+:\s+d900b10f 	stlur	x15, \[x8, #11\]
+[^:]+:\s+d900f10f 	stlur	x15, \[x8, #15\]
+[^:]+:\s+d900318f 	stlur	x15, \[x12, #3\]
+[^:]+:\s+d900b18f 	stlur	x15, \[x12, #11\]
+[^:]+:\s+d900f18f 	stlur	x15, \[x12, #15\]
+[^:]+:\s+d900301e 	stlur	x30, \[x0, #3\]
+[^:]+:\s+d900b01e 	stlur	x30, \[x0, #11\]
+[^:]+:\s+d900f01e 	stlur	x30, \[x0, #15\]
+[^:]+:\s+d900311e 	stlur	x30, \[x8, #3\]
+[^:]+:\s+d900b11e 	stlur	x30, \[x8, #11\]
+[^:]+:\s+d900f11e 	stlur	x30, \[x8, #15\]
+[^:]+:\s+d900319e 	stlur	x30, \[x12, #3\]
+[^:]+:\s+d900b19e 	stlur	x30, \[x12, #11\]
+[^:]+:\s+d900f19e 	stlur	x30, \[x12, #15\]
+[^:]+:\s+d9003002 	stlur	x2, \[x0, #3\]
+[^:]+:\s+d900b002 	stlur	x2, \[x0, #11\]
+[^:]+:\s+d900f002 	stlur	x2, \[x0, #15\]
+[^:]+:\s+d9003102 	stlur	x2, \[x8, #3\]
+[^:]+:\s+d900b102 	stlur	x2, \[x8, #11\]
+[^:]+:\s+d900f102 	stlur	x2, \[x8, #15\]
+[^:]+:\s+d9003182 	stlur	x2, \[x12, #3\]
+[^:]+:\s+d900b182 	stlur	x2, \[x12, #11\]
+[^:]+:\s+d900f182 	stlur	x2, \[x12, #15\]
+[^:]+:\s+d900300f 	stlur	x15, \[x0, #3\]
+[^:]+:\s+d900b00f 	stlur	x15, \[x0, #11\]
+[^:]+:\s+d900f00f 	stlur	x15, \[x0, #15\]
+[^:]+:\s+d900310f 	stlur	x15, \[x8, #3\]
+[^:]+:\s+d900b10f 	stlur	x15, \[x8, #11\]
+[^:]+:\s+d900f10f 	stlur	x15, \[x8, #15\]
+[^:]+:\s+d900318f 	stlur	x15, \[x12, #3\]
+[^:]+:\s+d900b18f 	stlur	x15, \[x12, #11\]
+[^:]+:\s+d900f18f 	stlur	x15, \[x12, #15\]
+[^:]+:\s+d900301e 	stlur	x30, \[x0, #3\]
+[^:]+:\s+d900b01e 	stlur	x30, \[x0, #11\]
+[^:]+:\s+d900f01e 	stlur	x30, \[x0, #15\]
+[^:]+:\s+d900311e 	stlur	x30, \[x8, #3\]
+[^:]+:\s+d900b11e 	stlur	x30, \[x8, #11\]
+[^:]+:\s+d900f11e 	stlur	x30, \[x8, #15\]
+[^:]+:\s+d900319e 	stlur	x30, \[x12, #3\]
+[^:]+:\s+d900b19e 	stlur	x30, \[x12, #11\]
+[^:]+:\s+d900f19e 	stlur	x30, \[x12, #15\]
+[^:]+:\s+d90033e0 	stlur	x0, \[sp, #3\]
+[^:]+:\s+d90523e0 	stlur	x0, \[sp, #82\]
+[^:]+:\s+d900d3e0 	stlur	x0, \[sp, #13\]
+[^:]+:\s+d90033e7 	stlur	x7, \[sp, #3\]
+[^:]+:\s+d90523e7 	stlur	x7, \[sp, #82\]
+[^:]+:\s+d900d3e7 	stlur	x7, \[sp, #13\]
+[^:]+:\s+d90033f0 	stlur	x16, \[sp, #3\]
+[^:]+:\s+d90523f0 	stlur	x16, \[sp, #82\]
+[^:]+:\s+d900d3f0 	stlur	x16, \[sp, #13\]
+[^:]+:\s+d90033fe 	stlur	x30, \[sp, #3\]
+[^:]+:\s+d90523fe 	stlur	x30, \[sp, #82\]
+[^:]+:\s+d900d3fe 	stlur	x30, \[sp, #13\]
+[^:]+:\s+99400060 	ldapur	w0, \[x3\]
+[^:]+:\s+99400160 	ldapur	w0, \[x11\]
+[^:]+:\s+994001e0 	ldapur	w0, \[x15\]
+[^:]+:\s+99400068 	ldapur	w8, \[x3\]
+[^:]+:\s+99400168 	ldapur	w8, \[x11\]
+[^:]+:\s+994001e8 	ldapur	w8, \[x15\]
+[^:]+:\s+9940006c 	ldapur	w12, \[x3\]
+[^:]+:\s+9940016c 	ldapur	w12, \[x11\]
+[^:]+:\s+994001ec 	ldapur	w12, \[x15\]
+[^:]+:\s+99400060 	ldapur	w0, \[x3\]
+[^:]+:\s+99400160 	ldapur	w0, \[x11\]
+[^:]+:\s+994001e0 	ldapur	w0, \[x15\]
+[^:]+:\s+99400068 	ldapur	w8, \[x3\]
+[^:]+:\s+99400168 	ldapur	w8, \[x11\]
+[^:]+:\s+994001e8 	ldapur	w8, \[x15\]
+[^:]+:\s+9940006c 	ldapur	w12, \[x3\]
+[^:]+:\s+9940016c 	ldapur	w12, \[x11\]
+[^:]+:\s+994001ec 	ldapur	w12, \[x15\]
+[^:]+:\s+99400060 	ldapur	w0, \[x3\]
+[^:]+:\s+99400160 	ldapur	w0, \[x11\]
+[^:]+:\s+994001e0 	ldapur	w0, \[x15\]
+[^:]+:\s+99400068 	ldapur	w8, \[x3\]
+[^:]+:\s+99400168 	ldapur	w8, \[x11\]
+[^:]+:\s+994001e8 	ldapur	w8, \[x15\]
+[^:]+:\s+9940006c 	ldapur	w12, \[x3\]
+[^:]+:\s+9940016c 	ldapur	w12, \[x11\]
+[^:]+:\s+994001ec 	ldapur	w12, \[x15\]
+[^:]+:\s+99400060 	ldapur	w0, \[x3\]
+[^:]+:\s+99400160 	ldapur	w0, \[x11\]
+[^:]+:\s+994001e0 	ldapur	w0, \[x15\]
+[^:]+:\s+99400068 	ldapur	w8, \[x3\]
+[^:]+:\s+99400168 	ldapur	w8, \[x11\]
+[^:]+:\s+994001e8 	ldapur	w8, \[x15\]
+[^:]+:\s+9940006c 	ldapur	w12, \[x3\]
+[^:]+:\s+9940016c 	ldapur	w12, \[x11\]
+[^:]+:\s+994001ec 	ldapur	w12, \[x15\]
+[^:]+:\s+994003e0 	ldapur	w0, \[sp\]
+[^:]+:\s+994003e7 	ldapur	w7, \[sp\]
+[^:]+:\s+994003f0 	ldapur	w16, \[sp\]
+[^:]+:\s+994003fe 	ldapur	w30, \[sp\]
+[^:]+:\s+99403002 	ldapur	w2, \[x0, #3\]
+[^:]+:\s+9940b002 	ldapur	w2, \[x0, #11\]
+[^:]+:\s+9940f002 	ldapur	w2, \[x0, #15\]
+[^:]+:\s+99403102 	ldapur	w2, \[x8, #3\]
+[^:]+:\s+9940b102 	ldapur	w2, \[x8, #11\]
+[^:]+:\s+9940f102 	ldapur	w2, \[x8, #15\]
+[^:]+:\s+99403182 	ldapur	w2, \[x12, #3\]
+[^:]+:\s+9940b182 	ldapur	w2, \[x12, #11\]
+[^:]+:\s+9940f182 	ldapur	w2, \[x12, #15\]
+[^:]+:\s+9940300f 	ldapur	w15, \[x0, #3\]
+[^:]+:\s+9940b00f 	ldapur	w15, \[x0, #11\]
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+[^:]+:\s+9940300f 	ldapur	w15, \[x0, #3\]
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+[^:]+:\s+9980f002 	ldapursw	x2, \[x0, #15\]
+[^:]+:\s+99803102 	ldapursw	x2, \[x8, #3\]
+[^:]+:\s+9980b102 	ldapursw	x2, \[x8, #11\]
+[^:]+:\s+9980f102 	ldapursw	x2, \[x8, #15\]
+[^:]+:\s+99803182 	ldapursw	x2, \[x12, #3\]
+[^:]+:\s+9980b182 	ldapursw	x2, \[x12, #11\]
+[^:]+:\s+9980f182 	ldapursw	x2, \[x12, #15\]
+[^:]+:\s+9980300f 	ldapursw	x15, \[x0, #3\]
+[^:]+:\s+9980b00f 	ldapursw	x15, \[x0, #11\]
+[^:]+:\s+9980f00f 	ldapursw	x15, \[x0, #15\]
+[^:]+:\s+9980310f 	ldapursw	x15, \[x8, #3\]
+[^:]+:\s+9980b10f 	ldapursw	x15, \[x8, #11\]
+[^:]+:\s+9980f10f 	ldapursw	x15, \[x8, #15\]
+[^:]+:\s+9980318f 	ldapursw	x15, \[x12, #3\]
+[^:]+:\s+9980b18f 	ldapursw	x15, \[x12, #11\]
+[^:]+:\s+9980f18f 	ldapursw	x15, \[x12, #15\]
+[^:]+:\s+9980301e 	ldapursw	x30, \[x0, #3\]
+[^:]+:\s+9980b01e 	ldapursw	x30, \[x0, #11\]
+[^:]+:\s+9980f01e 	ldapursw	x30, \[x0, #15\]
+[^:]+:\s+9980311e 	ldapursw	x30, \[x8, #3\]
+[^:]+:\s+9980b11e 	ldapursw	x30, \[x8, #11\]
+[^:]+:\s+9980f11e 	ldapursw	x30, \[x8, #15\]
+[^:]+:\s+9980319e 	ldapursw	x30, \[x12, #3\]
+[^:]+:\s+9980b19e 	ldapursw	x30, \[x12, #11\]
+[^:]+:\s+9980f19e 	ldapursw	x30, \[x12, #15\]
+[^:]+:\s+99803002 	ldapursw	x2, \[x0, #3\]
+[^:]+:\s+9980b002 	ldapursw	x2, \[x0, #11\]
+[^:]+:\s+9980f002 	ldapursw	x2, \[x0, #15\]
+[^:]+:\s+99803102 	ldapursw	x2, \[x8, #3\]
+[^:]+:\s+9980b102 	ldapursw	x2, \[x8, #11\]
+[^:]+:\s+9980f102 	ldapursw	x2, \[x8, #15\]
+[^:]+:\s+99803182 	ldapursw	x2, \[x12, #3\]
+[^:]+:\s+9980b182 	ldapursw	x2, \[x12, #11\]
+[^:]+:\s+9980f182 	ldapursw	x2, \[x12, #15\]
+[^:]+:\s+9980300f 	ldapursw	x15, \[x0, #3\]
+[^:]+:\s+9980b00f 	ldapursw	x15, \[x0, #11\]
+[^:]+:\s+9980f00f 	ldapursw	x15, \[x0, #15\]
+[^:]+:\s+9980310f 	ldapursw	x15, \[x8, #3\]
+[^:]+:\s+9980b10f 	ldapursw	x15, \[x8, #11\]
+[^:]+:\s+9980f10f 	ldapursw	x15, \[x8, #15\]
+[^:]+:\s+9980318f 	ldapursw	x15, \[x12, #3\]
+[^:]+:\s+9980b18f 	ldapursw	x15, \[x12, #11\]
+[^:]+:\s+9980f18f 	ldapursw	x15, \[x12, #15\]
+[^:]+:\s+9980301e 	ldapursw	x30, \[x0, #3\]
+[^:]+:\s+9980b01e 	ldapursw	x30, \[x0, #11\]
+[^:]+:\s+9980f01e 	ldapursw	x30, \[x0, #15\]
+[^:]+:\s+9980311e 	ldapursw	x30, \[x8, #3\]
+[^:]+:\s+9980b11e 	ldapursw	x30, \[x8, #11\]
+[^:]+:\s+9980f11e 	ldapursw	x30, \[x8, #15\]
+[^:]+:\s+9980319e 	ldapursw	x30, \[x12, #3\]
+[^:]+:\s+9980b19e 	ldapursw	x30, \[x12, #11\]
+[^:]+:\s+9980f19e 	ldapursw	x30, \[x12, #15\]
+[^:]+:\s+99803002 	ldapursw	x2, \[x0, #3\]
+[^:]+:\s+9980b002 	ldapursw	x2, \[x0, #11\]
+[^:]+:\s+9980f002 	ldapursw	x2, \[x0, #15\]
+[^:]+:\s+99803102 	ldapursw	x2, \[x8, #3\]
+[^:]+:\s+9980b102 	ldapursw	x2, \[x8, #11\]
+[^:]+:\s+9980f102 	ldapursw	x2, \[x8, #15\]
+[^:]+:\s+99803182 	ldapursw	x2, \[x12, #3\]
+[^:]+:\s+9980b182 	ldapursw	x2, \[x12, #11\]
+[^:]+:\s+9980f182 	ldapursw	x2, \[x12, #15\]
+[^:]+:\s+9980300f 	ldapursw	x15, \[x0, #3\]
+[^:]+:\s+9980b00f 	ldapursw	x15, \[x0, #11\]
+[^:]+:\s+9980f00f 	ldapursw	x15, \[x0, #15\]
+[^:]+:\s+9980310f 	ldapursw	x15, \[x8, #3\]
+[^:]+:\s+9980b10f 	ldapursw	x15, \[x8, #11\]
+[^:]+:\s+9980f10f 	ldapursw	x15, \[x8, #15\]
+[^:]+:\s+9980318f 	ldapursw	x15, \[x12, #3\]
+[^:]+:\s+9980b18f 	ldapursw	x15, \[x12, #11\]
+[^:]+:\s+9980f18f 	ldapursw	x15, \[x12, #15\]
+[^:]+:\s+9980301e 	ldapursw	x30, \[x0, #3\]
+[^:]+:\s+9980b01e 	ldapursw	x30, \[x0, #11\]
+[^:]+:\s+9980f01e 	ldapursw	x30, \[x0, #15\]
+[^:]+:\s+9980311e 	ldapursw	x30, \[x8, #3\]
+[^:]+:\s+9980b11e 	ldapursw	x30, \[x8, #11\]
+[^:]+:\s+9980f11e 	ldapursw	x30, \[x8, #15\]
+[^:]+:\s+9980319e 	ldapursw	x30, \[x12, #3\]
+[^:]+:\s+9980b19e 	ldapursw	x30, \[x12, #11\]
+[^:]+:\s+9980f19e 	ldapursw	x30, \[x12, #15\]
+[^:]+:\s+998033e0 	ldapursw	x0, \[sp, #3\]
+[^:]+:\s+998523e0 	ldapursw	x0, \[sp, #82\]
+[^:]+:\s+9980d3e0 	ldapursw	x0, \[sp, #13\]
+[^:]+:\s+998033e7 	ldapursw	x7, \[sp, #3\]
+[^:]+:\s+998523e7 	ldapursw	x7, \[sp, #82\]
+[^:]+:\s+9980d3e7 	ldapursw	x7, \[sp, #13\]
+[^:]+:\s+998033f0 	ldapursw	x16, \[sp, #3\]
+[^:]+:\s+998523f0 	ldapursw	x16, \[sp, #82\]
+[^:]+:\s+9980d3f0 	ldapursw	x16, \[sp, #13\]
+[^:]+:\s+998033fe 	ldapursw	x30, \[sp, #3\]
+[^:]+:\s+998523fe 	ldapursw	x30, \[sp, #82\]
+[^:]+:\s+9980d3fe 	ldapursw	x30, \[sp, #13\]
diff --git a/gas/testsuite/gas/aarch64/rcpc2.s b/gas/testsuite/gas/aarch64/rcpc2.s
new file mode 100644
index 0000000000000000000000000000000000000000..8496dbe19877301503bc68961e683ea623571017
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc2.s
@@ -0,0 +1,143 @@
+	# Print a 4 operand instruction
+	.macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w	, pw1=, pw2=
+	.ifnb \d
+		\op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
+	.else
+	.ifnb \n
+		\op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
+	.else
+		\op \pm1\m\()\pm2, \pw1\w\()\pw2
+	.endif
+	.endif
+	.endm
+
+	.macro gen4reg_iter_d_offset op, d, pd1=, pd2=, r
+	.irp m, 03, 82, 13
+		\op \pd1\d\()\pd2, [\r, \m]
+	.endr
+	.endm
+
+	.macro gen4reg_iter_d_n_w op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, pw1=, pw2=
+	.irp w, 3, 11, 15
+		print_gen4reg \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \w, \pw1, \pw2
+	.endr
+	.endm
+
+	.macro gen4reg_iter_d_n op, d, pd1=, pd2=, n, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
+	.irp m, 0, 8, 12
+		gen4reg_iter_d_n_w \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \pw1, \pw2
+	.endr
+	.endm
+
+	.macro gen4reg_iter_d op, d, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
+	.irp n, 2, 15, 30
+		gen4reg_iter_d_n \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
+	.endr
+	.endm
+
+	.macro gen4reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
+	.irp d, 0, 7, 16, 30
+		gen4reg_iter_d \op, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
+	.endr
+	.endm
+
+	# Print a 3 operand instruction
+	.macro gen3reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=
+	.irp d, 0, 7, 16, 30
+		gen4reg_iter_d \op,,, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2
+	.endr
+	.endm
+
+	.macro gen3reg_iter_lane op, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=, x:vararg
+	.irp l, \x
+		gen4reg_iter_d \op,,,, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2[\l]
+	.endr
+	.endm
+
+	# Print a 2 operand instruction
+	.macro gen2reg_iter op, pd1=, pd2=, pn1=, pn2=
+	.irp d, 0, 7, 16, 30
+		gen4reg_iter_d_n \op,,,,,, \d, \pd1, \pd2, \pn1, \pn2
+	.endr
+	.endm
+
+	.macro gen2reg_iter_offset op, pd1=, pd2=, r
+	.irp d, 0, 7, 16, 30
+		gen4reg_iter_d_offset \op, \d, \pd1, \pd2, \r,
+	.endr
+	.endm
+
+	# Print a 1 operand instruction
+	.macro gen1reg_iter op, pd1=, pd2=
+	.irp d, 0, 7, 16, 30
+		\op \pd1\d\()\pd2
+	.endr
+	.endm
+
+	.text
+func:
+	gen2reg_iter stlurb w,,[x,]
+	gen1reg_iter stlurb w,", [sp]"
+	gen3reg_iter stlurb w,, [x,,,]
+	gen2reg_iter_offset stlurb w,,sp
+
+	gen2reg_iter ldapurb w,,[x,]
+	gen1reg_iter ldapurb w,", [sp]"
+	gen3reg_iter ldapurb w,, [x,,,]
+	gen2reg_iter_offset ldapurb w,,sp
+
+	gen2reg_iter ldapursb w,,[x,]
+	gen1reg_iter ldapursb w,", [sp]"
+	gen3reg_iter ldapursb w,, [x,,,]
+	gen2reg_iter_offset ldapursb w,,sp
+
+	gen2reg_iter ldapursb x,,[x,]
+	gen1reg_iter ldapursb x,", [sp]"
+	gen3reg_iter ldapursb x,, [x,,,]
+	gen2reg_iter_offset ldapursb x,,sp
+
+	gen2reg_iter stlurh w,,[x,]
+	gen1reg_iter stlurh w,", [sp]"
+	gen3reg_iter stlurh w,, [x,,,]
+	gen2reg_iter_offset stlurh w,,sp
+
+	gen2reg_iter ldapurh w,,[x,]
+	gen1reg_iter ldapurh w,", [sp]"
+	gen3reg_iter ldapurh w,, [x,,,]
+	gen2reg_iter_offset ldapurh w,,sp
+
+	gen2reg_iter ldapursh w,,[x,]
+	gen1reg_iter ldapursh w,", [sp]"
+	gen3reg_iter ldapursh w,, [x,,,]
+	gen2reg_iter_offset ldapursh w,,sp
+
+	gen2reg_iter ldapursh x,,[x,]
+	gen1reg_iter ldapursh x,", [sp]"
+	gen3reg_iter ldapursh x,, [x,,,]
+	gen2reg_iter_offset ldapursh x,,sp
+
+	gen2reg_iter stlur w,,[x,]
+	gen1reg_iter stlur w,", [sp]"
+	gen3reg_iter stlur w,, [x,,,]
+	gen2reg_iter_offset stlur w,,sp
+
+	gen2reg_iter stlur x,,[x,]
+	gen1reg_iter stlur x,", [sp]"
+	gen3reg_iter stlur x,, [x,,,]
+	gen2reg_iter_offset stlur x,,sp
+
+	gen2reg_iter ldapur w,,[x,]
+	gen1reg_iter ldapur w,", [sp]"
+	gen3reg_iter ldapur w,, [x,,,]
+	gen2reg_iter_offset ldapur w,,sp
+
+	gen2reg_iter ldapur x,,[x,]
+	gen1reg_iter ldapur x,", [sp]"
+	gen3reg_iter ldapur x,, [x,,,]
+	gen2reg_iter_offset ldapur x,,sp
+
+	gen2reg_iter ldapursw x,,[x,]
+	gen1reg_iter ldapursw x,", [sp]"
+	gen3reg_iter ldapursw x,, [x,,,]
+	gen2reg_iter_offset ldapursw x,,sp
+
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index eb42b87a00263cfa633e4bd6c35fd912941a15a8..6674f34ab29d06df2e26dc2e62e0365c067c9e82 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -97,6 +97,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SVE,
   /* RCPC instructions.  */
   AARCH64_FEATURE_RCPC,
+  /* RCPC2 instructions.  */
+  AARCH64_FEATURE_RCPC2,
   /* Complex # instructions.  */
   AARCH64_FEATURE_COMPNUM,
   /* JavaScript conversion instructions.  */
@@ -251,6 +253,7 @@ enum aarch64_feature_bit {
 					 | AARCH64_FEATBIT (X, COMPNUM) \
 					 | AARCH64_FEATBIT (X, JSCVT))
 #define AARCH64_ARCH_V8_4A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_4A)	\
+					 | AARCH64_FEATBIT (X, RCPC2)	\
 					 | AARCH64_FEATBIT (X, DOTPROD)	\
 					 | AARCH64_FEATBIT (X, FLAGM)	\
 					 | AARCH64_FEATBIT (X, F16_FML))
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 007bf018af89c4bc74e59bc70e8560caacb3eac7..1838f99a960c7348c1d36e50c0b9aba5e87b5196 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2522,6 +2522,8 @@ static const aarch64_feature_set aarch64_feature_jscvt =
   AARCH64_FEATURE (JSCVT);
 static const aarch64_feature_set aarch64_feature_rcpc =
   AARCH64_FEATURE (RCPC);
+static const aarch64_feature_set aarch64_feature_rcpc2 =
+  AARCH64_FEATURE (RCPC2);
 static const aarch64_feature_set aarch64_feature_dotprod =
   AARCH64_FEATURE (DOTPROD);
 static const aarch64_feature_set aarch64_feature_sha2 =
@@ -2635,6 +2637,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
 #define COMPNUM		&aarch64_feature_compnum
 #define JSCVT		&aarch64_feature_jscvt
 #define RCPC		&aarch64_feature_rcpc
+#define RCPC2		&aarch64_feature_rcpc2
 #define SHA2		&aarch64_feature_sha2
 #define AES		&aarch64_feature_aes
 #define ARMV8_4A	&aarch64_feature_v8_4a
@@ -2724,6 +2727,8 @@ static const aarch64_feature_set aarch64_feature_d128_the =
   { NAME, OPCODE, MASK, CLASS, 0, JSCVT, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define RCPC2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, RCPC2, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -6040,19 +6045,19 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   FLAGM_INSN ("setf8",  0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
   FLAGM_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
   /* Memory access instructions ARMv8.4-a.  */
-  V8_4A_INSN ("stlurb" ,  0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
-  V8_4A_INSN ("ldapurb",  0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
-  V8_4A_INSN ("ldapursb", 0x19c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
-  V8_4A_INSN ("ldapursb", 0x19800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
-  V8_4A_INSN ("stlurh",   0x59000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
-  V8_4A_INSN ("ldapurh",  0x59400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
-  V8_4A_INSN ("ldapursh", 0x59c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
-  V8_4A_INSN ("ldapursh", 0x59800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
-  V8_4A_INSN ("stlur",    0x99000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
-  V8_4A_INSN ("ldapur",   0x99400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
-  V8_4A_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
-  V8_4A_INSN ("stlur",    0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
-  V8_4A_INSN ("ldapur",   0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
+  RCPC2_INSN ("stlurb" ,  0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
+  RCPC2_INSN ("ldapurb",  0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
+  RCPC2_INSN ("ldapursb", 0x19c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
+  RCPC2_INSN ("ldapursb", 0x19800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
+  RCPC2_INSN ("stlurh",   0x59000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
+  RCPC2_INSN ("ldapurh",  0x59400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
+  RCPC2_INSN ("ldapursh", 0x59c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
+  RCPC2_INSN ("ldapursh", 0x59800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
+  RCPC2_INSN ("stlur",    0x99000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
+  RCPC2_INSN ("ldapur",   0x99400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
+  RCPC2_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
+  RCPC2_INSN ("stlur",    0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
+  RCPC2_INSN ("ldapur",   0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
 
   /* Matrix Multiply instructions.  */
   INT8MATMUL_SVE_INSNC ("smmla",  0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),

[PATCH 08/11] aarch64: Add +wfxt flag for existing instructions

[Andrew Carlotti]

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index df71e67a5a68047d70abe65d8f178fdfae114306..5b3cdd837b3f042a1f0d8e8b98c7dde1b604a49c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10323,6 +10323,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"flagm",		AARCH64_FEATURE (FLAGM), AARCH64_NO_FEATURES},
   {"flagm2",		AARCH64_FEATURE (FLAGMANIP), AARCH64_FEATURE (FLAGM)},
   {"pauth",		AARCH64_FEATURE (PAC), AARCH64_NO_FEATURES},
+  {"wfxt",		AARCH64_FEATURE (WFXT), AARCH64_NO_FEATURES},
   {"mops",		AARCH64_FEATURE (MOPS), AARCH64_NO_FEATURES},
   {"hbc",		AARCH64_FEATURE (HBC), AARCH64_NO_FEATURES},
   {"cssc",		AARCH64_FEATURE (CSSC), AARCH64_NO_FEATURES},
diff --git a/gas/testsuite/gas/aarch64/system-5.d b/gas/testsuite/gas/aarch64/system-5.d
index 935e843a5063eca7e054eef678786358d1790fa8..a24173942cef614d3158de7197d955c9380d017f 100644
--- a/gas/testsuite/gas/aarch64/system-5.d
+++ b/gas/testsuite/gas/aarch64/system-5.d
@@ -68,3 +68,65 @@ Disassembly of section \.text:
 .*:	d503103c 	wfit	x28
 .*:	d503103d 	wfit	x29
 .*:	d503103e 	wfit	x30
+.*:	d5031000 	wfet	x0
+.*:	d5031001 	wfet	x1
+.*:	d5031002 	wfet	x2
+.*:	d5031003 	wfet	x3
+.*:	d5031004 	wfet	x4
+.*:	d5031005 	wfet	x5
+.*:	d5031006 	wfet	x6
+.*:	d5031007 	wfet	x7
+.*:	d5031008 	wfet	x8
+.*:	d5031009 	wfet	x9
+.*:	d503100a 	wfet	x10
+.*:	d503100b 	wfet	x11
+.*:	d503100c 	wfet	x12
+.*:	d503100d 	wfet	x13
+.*:	d503100e 	wfet	x14
+.*:	d503100f 	wfet	x15
+.*:	d5031010 	wfet	x16
+.*:	d5031011 	wfet	x17
+.*:	d5031012 	wfet	x18
+.*:	d5031013 	wfet	x19
+.*:	d5031014 	wfet	x20
+.*:	d5031015 	wfet	x21
+.*:	d5031016 	wfet	x22
+.*:	d5031017 	wfet	x23
+.*:	d5031018 	wfet	x24
+.*:	d5031019 	wfet	x25
+.*:	d503101a 	wfet	x26
+.*:	d503101b 	wfet	x27
+.*:	d503101c 	wfet	x28
+.*:	d503101d 	wfet	x29
+.*:	d503101e 	wfet	x30
+.*:	d5031020 	wfit	x0
+.*:	d5031021 	wfit	x1
+.*:	d5031022 	wfit	x2
+.*:	d5031023 	wfit	x3
+.*:	d5031024 	wfit	x4
+.*:	d5031025 	wfit	x5
+.*:	d5031026 	wfit	x6
+.*:	d5031027 	wfit	x7
+.*:	d5031028 	wfit	x8
+.*:	d5031029 	wfit	x9
+.*:	d503102a 	wfit	x10
+.*:	d503102b 	wfit	x11
+.*:	d503102c 	wfit	x12
+.*:	d503102d 	wfit	x13
+.*:	d503102e 	wfit	x14
+.*:	d503102f 	wfit	x15
+.*:	d5031030 	wfit	x16
+.*:	d5031031 	wfit	x17
+.*:	d5031032 	wfit	x18
+.*:	d5031033 	wfit	x19
+.*:	d5031034 	wfit	x20
+.*:	d5031035 	wfit	x21
+.*:	d5031036 	wfit	x22
+.*:	d5031037 	wfit	x23
+.*:	d5031038 	wfit	x24
+.*:	d5031039 	wfit	x25
+.*:	d503103a 	wfit	x26
+.*:	d503103b 	wfit	x27
+.*:	d503103c 	wfit	x28
+.*:	d503103d 	wfit	x29
+.*:	d503103e 	wfit	x30
diff --git a/gas/testsuite/gas/aarch64/system-5.s b/gas/testsuite/gas/aarch64/system-5.s
index ec2c58c890ff7d64722e7c88b27518b2b0c26321..cacb4489521305b047e6f484907d9c3402534b71 100644
--- a/gas/testsuite/gas/aarch64/system-5.s
+++ b/gas/testsuite/gas/aarch64/system-5.s
@@ -66,3 +66,73 @@
     wfit x28
     wfit x29
     wfit x30
+
+
+/* Wait For Event with Timeout is also available with +wfxt.  */
+.arch armv8-a+wfxt
+
+    wfet x0
+    wfet x1
+    wfet x2
+    wfet x3
+    wfet x4
+    wfet x5
+    wfet x6
+    wfet x7
+    wfet x8
+    wfet x9
+    wfet x10
+    wfet x11
+    wfet x12
+    wfet x13
+    wfet x14
+    wfet x15
+    wfet x16
+    wfet x17
+    wfet x18
+    wfet x19
+    wfet x20
+    wfet x21
+    wfet x22
+    wfet x23
+    wfet x24
+    wfet x25
+    wfet x26
+    wfet x27
+    wfet x28
+    wfet x29
+    wfet x30
+
+/* Wait For Interrupt with Timeout.  */
+
+    wfit x0
+    wfit x1
+    wfit x2
+    wfit x3
+    wfit x4
+    wfit x5
+    wfit x6
+    wfit x7
+    wfit x8
+    wfit x9
+    wfit x10
+    wfit x11
+    wfit x12
+    wfit x13
+    wfit x14
+    wfit x15
+    wfit x16
+    wfit x17
+    wfit x18
+    wfit x19
+    wfit x20
+    wfit x21
+    wfit x22
+    wfit x23
+    wfit x24
+    wfit x25
+    wfit x26
+    wfit x27
+    wfit x28
+    wfit x29
+    wfit x30
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6674f34ab29d06df2e26dc2e62e0365c067c9e82..973118c0d577da770ee2cce5599f25a73bd56782 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -141,6 +141,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_MEMTAG,
   /* Transactional Memory Extension.  */
   AARCH64_FEATURE_TME,
+  /* WFx instructions with timeout.  */
+  AARCH64_FEATURE_WFXT,
   /* Standardization of memory operations.  */
   AARCH64_FEATURE_MOPS,
   /* Hinted conditional branches.  */
@@ -271,6 +273,7 @@ enum aarch64_feature_bit {
 					 | AARCH64_FEATBIT (X, BFLOAT16) \
 					 | AARCH64_FEATBIT (X, I8MM))
 #define AARCH64_ARCH_V8_7A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_7A)	\
+					 | AARCH64_FEATBIT (X, WFXT)    \
 					 | AARCH64_FEATBIT (X, LS64))
 #define AARCH64_ARCH_V8_8A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_8A)	\
 					 | AARCH64_FEATBIT (X, MOPS)	\
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 1838f99a960c7348c1d36e50c0b9aba5e87b5196..f6538aa5536d355881016442a82458334477ec58 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2598,6 +2598,8 @@ static const aarch64_feature_set aarch64_feature_ls64 =
   AARCH64_FEATURE (LS64);
 static const aarch64_feature_set aarch64_feature_flagm =
   AARCH64_FEATURE (FLAGM);
+static const aarch64_feature_set aarch64_feature_wfxt =
+  AARCH64_FEATURE (WFXT);
 static const aarch64_feature_set aarch64_feature_mops =
   AARCH64_FEATURE (MOPS);
 static const aarch64_feature_set aarch64_feature_mops_memtag =
@@ -2676,6 +2678,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
 #define ARMV8_7A  &aarch64_feature_v8_7a
 #define LS64	  &aarch64_feature_ls64
 #define FLAGM	  &aarch64_feature_flagm
+#define WFXT	  &aarch64_feature_wfxt
 #define MOPS	  &aarch64_feature_mops
 #define MOPS_MEMTAG &aarch64_feature_mops_memtag
 #define HBC	  &aarch64_feature_hbc
@@ -2825,6 +2828,8 @@ static const aarch64_feature_set aarch64_feature_d128_the =
   { NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define V8_7A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, ARMV8_7A, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define WFXT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, WFXT, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -4245,8 +4250,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("ic",  0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
   CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
   D128_INSN ("tlbip",0xd5480000, 0xfff80000, OP3 (SYSREG_TLBIP, Rt_SYS, PAIRREG_OR_XZR), QL_SRC_X2, F_ALIAS| F_OPD1_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)),
-  V8_7A_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
-  V8_7A_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
+  WFXT_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
+  WFXT_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
   PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),

[PATCH 09/11] aarch64: Add +xs flag for existing instructions

[Andrew Carlotti]

Additionally, change FEAT_XS tlbi variants to be gated on "+xs" instead of
"+d128".  This is an incremental improvement; there are still some FEAT_XS tlbi
variants that are gated incorrectly or missing entirely.


diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5b3cdd837b3f042a1f0d8e8b98c7dde1b604a49c..7eb732adbb6c85fdf4db7c4b14d0be5fafa370b6 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10323,6 +10323,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"flagm",		AARCH64_FEATURE (FLAGM), AARCH64_NO_FEATURES},
   {"flagm2",		AARCH64_FEATURE (FLAGMANIP), AARCH64_FEATURE (FLAGM)},
   {"pauth",		AARCH64_FEATURE (PAC), AARCH64_NO_FEATURES},
+  {"xs",		AARCH64_FEATURE (XS), AARCH64_NO_FEATURES},
   {"wfxt",		AARCH64_FEATURE (WFXT), AARCH64_NO_FEATURES},
   {"mops",		AARCH64_FEATURE (MOPS), AARCH64_NO_FEATURES},
   {"hbc",		AARCH64_FEATURE (HBC), AARCH64_NO_FEATURES},
diff --git a/gas/testsuite/gas/aarch64/system-4.d b/gas/testsuite/gas/aarch64/system-4.d
index 0f600f80abda8f9f697f6765753c09d3083afa59..5673436823ad4427a1f2021759c659fc519bbdb4 100644
--- a/gas/testsuite/gas/aarch64/system-4.d
+++ b/gas/testsuite/gas/aarch64/system-4.d
@@ -14,3 +14,11 @@ Disassembly of section \.text:
 .*:	d503363f 	dsb	nshnxs
 .*:	d5033a3f 	dsb	ishnxs
 .*:	d5033e3f 	dsb	synxs
+.*:	d503323f 	dsb	oshnxs
+.*:	d503363f 	dsb	nshnxs
+.*:	d5033a3f 	dsb	ishnxs
+.*:	d5033e3f 	dsb	synxs
+.*:	d503323f 	dsb	oshnxs
+.*:	d503363f 	dsb	nshnxs
+.*:	d5033a3f 	dsb	ishnxs
+.*:	d5033e3f 	dsb	synxs
diff --git a/gas/testsuite/gas/aarch64/system-4.s b/gas/testsuite/gas/aarch64/system-4.s
index f95eb35df567657b8c5a17811814c17eb19ffeb7..fbf92caf7bcbd41015d8fe093bbfe6f35a8c0860 100644
--- a/gas/testsuite/gas/aarch64/system-4.s
+++ b/gas/testsuite/gas/aarch64/system-4.s
@@ -10,3 +10,15 @@
     dsb nshnxs
     dsb ishnxs
     dsb synxs
+
+.arch armv8-a+xs
+
+    dsb #16
+    dsb #20
+    dsb #24
+    dsb #28
+
+    dsb oshnxs
+    dsb nshnxs
+    dsb ishnxs
+    dsb synxs
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 973118c0d577da770ee2cce5599f25a73bd56782..9d64d7a0ebefa4014f30a46c5be7bda124666327 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -141,6 +141,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_MEMTAG,
   /* Transactional Memory Extension.  */
   AARCH64_FEATURE_TME,
+  /* XS memory attribute.  */
+  AARCH64_FEATURE_XS,
   /* WFx instructions with timeout.  */
   AARCH64_FEATURE_WFXT,
   /* Standardization of memory operations.  */
@@ -273,6 +275,7 @@ enum aarch64_feature_bit {
 					 | AARCH64_FEATBIT (X, BFLOAT16) \
 					 | AARCH64_FEATBIT (X, I8MM))
 #define AARCH64_ARCH_V8_7A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_7A)	\
+					 | AARCH64_FEATBIT (X, XS)      \
 					 | AARCH64_FEATBIT (X, WFXT)    \
 					 | AARCH64_FEATBIT (X, LS64))
 #define AARCH64_ARCH_V8_8A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_8A)	\
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 2e7472ac3e78419ceb508c2092da847e4d146dc7..e3ad32f5a1e070fe1cc464e1c0df2b0f4347f45f 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -5171,7 +5171,7 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
        || reg_value == CPENS (6, C9, C6, 5)
        || reg_value == CPENS (6, C9, C7, 1)
        || reg_value == CPENS (6, C9, C7, 5))
-      && AARCH64_CPU_HAS_FEATURE (features, D128))
+      && AARCH64_CPU_HAS_FEATURE (features, XS))
     return true;
 
   /* AT S1E1RP, AT S1E1WP.  Values are from aarch64_sys_regs_at.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index f6538aa5536d355881016442a82458334477ec58..95f7757e8ebaa5ca1958be212283aa17cacdcc5b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2598,6 +2598,8 @@ static const aarch64_feature_set aarch64_feature_ls64 =
   AARCH64_FEATURE (LS64);
 static const aarch64_feature_set aarch64_feature_flagm =
   AARCH64_FEATURE (FLAGM);
+static const aarch64_feature_set aarch64_feature_xs =
+  AARCH64_FEATURE (XS);
 static const aarch64_feature_set aarch64_feature_wfxt =
   AARCH64_FEATURE (WFXT);
 static const aarch64_feature_set aarch64_feature_mops =
@@ -2678,6 +2680,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
 #define ARMV8_7A  &aarch64_feature_v8_7a
 #define LS64	  &aarch64_feature_ls64
 #define FLAGM	  &aarch64_feature_flagm
+#define XS	  &aarch64_feature_xs
 #define WFXT	  &aarch64_feature_wfxt
 #define MOPS	  &aarch64_feature_mops
 #define MOPS_MEMTAG &aarch64_feature_mops_memtag
@@ -2828,6 +2831,8 @@ static const aarch64_feature_set aarch64_feature_d128_the =
   { NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define V8_7A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, ARMV8_7A, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define XS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, XS, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define WFXT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, WFXT, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -4225,7 +4230,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("clearbhb", 0xd50322df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
   CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
   CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS),
-  V8_7A_INSN ("dsb", 0xd503323f, 0xfffff3ff, ic_system, OP1 (BARRIER_DSB_NXS), {}, F_HAS_ALIAS),
+  XS_INSN ("dsb", 0xd503323f, 0xfffff3ff, ic_system, OP1 (BARRIER_DSB_NXS), {}, F_HAS_ALIAS),
   V8R_INSN ("dfb", 0xd5033c9f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
   CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
   CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),

[PATCH 10/11] aarch64: Make FEAT_ASMv8p2 instruction aliases always available

[Andrew Carlotti]

There's no reason to disallow the aliases when the aliased instructions are
always available.  The new behaviour matches existing LLVM behaviour.


diff --git a/gas/testsuite/gas/aarch64/alias-2.d b/gas/testsuite/gas/aarch64/alias-2.d
index 45ddcf5905a677ab807c9e8f7d93dd8b10bd77a1..610382b91d1a096027ef115451d7985b2ed40e61 100644
--- a/gas/testsuite/gas/aarch64/alias-2.d
+++ b/gas/testsuite/gas/aarch64/alias-2.d
@@ -1,5 +1,5 @@
 #objdump: -dr
-#as: -march=armv8.2-a
+#as: -march=armv8-a
 
 .*:     file format .*
 
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 95f7757e8ebaa5ca1958be212283aa17cacdcc5b..3df273c74f3af26195039a8ed23c4e6c3784b404 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3572,7 +3572,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV),
   CORE_INSN ("bfm", 0x33000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N),
   CORE_INSN ("bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
-  V8_2A_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV),
+  CORE_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV),
   CORE_INSN ("bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
   CORE_INSN ("ubfm", 0x53000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N),
   CORE_INSN ("ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
@@ -3645,7 +3645,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
   CORE_INSN ("rev",   0x5ac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEW, 0),
   CORE_INSN ("rev",   0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1),
-  V8_2A_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS),
+  CORE_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS),
   CORE_INSN ("clz",   0x5ac01000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
   CORE_INSN ("cls",   0x5ac01400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
   CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, 0),

[PATCH 11/11] aarch64: Remove unused code

[Andrew Carlotti]

Most of this code became redundant in my previous commits, but ARMV8_6A_SVE was
already dead when it was first added.


diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 3df273c74f3af26195039a8ed23c4e6c3784b404..0cf195d03216a38e1a9b5e06b80af064e2440b91 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2502,18 +2502,12 @@ static const aarch64_feature_set aarch64_feature_lor =
   AARCH64_FEATURE (LOR);
 static const aarch64_feature_set aarch64_feature_rdma =
   AARCH64_FEATURE (RDMA);
-static const aarch64_feature_set aarch64_feature_v8_2a =
-  AARCH64_FEATURE (V8_2A);
 static const aarch64_feature_set aarch64_feature_fp_f16 =
   AARCH64_FEATURES (2, F16, FP);
 static const aarch64_feature_set aarch64_feature_simd_f16 =
   AARCH64_FEATURES (2, F16, SIMD);
 static const aarch64_feature_set aarch64_feature_sve =
   AARCH64_FEATURE (SVE);
-static const aarch64_feature_set aarch64_feature_v8_3a =
-  AARCH64_FEATURE (V8_3A);
-static const aarch64_feature_set aarch64_feature_fp_v8_3a =
-  AARCH64_FEATURES (2, V8_3A, FP);
 static const aarch64_feature_set aarch64_feature_pac =
   AARCH64_FEATURE (PAC);
 static const aarch64_feature_set aarch64_feature_compnum =
@@ -2530,16 +2524,12 @@ static const aarch64_feature_set aarch64_feature_sha2 =
   AARCH64_FEATURES (2, V8, SHA2);
 static const aarch64_feature_set aarch64_feature_aes =
   AARCH64_FEATURES (2, V8, AES);
-static const aarch64_feature_set aarch64_feature_v8_4a =
-  AARCH64_FEATURE (V8_4A);
 static const aarch64_feature_set aarch64_feature_sm4 =
   AARCH64_FEATURES (3, SM4, SIMD, FP);
 static const aarch64_feature_set aarch64_feature_sha3 =
   AARCH64_FEATURES (4, SHA2, SHA3, SIMD, FP);
 static const aarch64_feature_set aarch64_feature_fp_16_v8_2a =
   AARCH64_FEATURES (3, F16_FML, F16, FP);
-static const aarch64_feature_set aarch64_feature_v8_5a =
-  AARCH64_FEATURE (V8_5A);
 static const aarch64_feature_set aarch64_feature_flagmanip =
   AARCH64_FEATURE (FLAGMANIP);
 static const aarch64_feature_set aarch64_feature_frintts =
@@ -2580,10 +2570,6 @@ static const aarch64_feature_set aarch64_feature_sme2_i16i64 =
   AARCH64_FEATURES (2, SME2, SME_I16I64);
 static const aarch64_feature_set aarch64_feature_sme2_f64f64 =
   AARCH64_FEATURES (2, SME2, SME_F64F64);
-static const aarch64_feature_set aarch64_feature_v8_6a =
-  AARCH64_FEATURE (V8_6A);
-static const aarch64_feature_set aarch64_feature_v8_7a =
-  AARCH64_FEATURE (V8_7A);
 static const aarch64_feature_set aarch64_feature_i8mm =
   AARCH64_FEATURE (I8MM);
 static const aarch64_feature_set aarch64_feature_i8mm_sve =
@@ -2633,10 +2619,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
 #define RDMA		&aarch64_feature_rdma
 #define FP_F16		&aarch64_feature_fp_f16
 #define SIMD_F16	&aarch64_feature_simd_f16
-#define ARMV8_2A	&aarch64_feature_v8_2a
 #define SVE		&aarch64_feature_sve
-#define ARMV8_3A	&aarch64_feature_v8_3a
-#define FP_V8_3A	&aarch64_feature_fp_v8_3a
 #define PAC		&aarch64_feature_pac
 #define COMPNUM		&aarch64_feature_compnum
 #define JSCVT		&aarch64_feature_jscvt
@@ -2644,12 +2627,10 @@ static const aarch64_feature_set aarch64_feature_d128_the =
 #define RCPC2		&aarch64_feature_rcpc2
 #define SHA2		&aarch64_feature_sha2
 #define AES		&aarch64_feature_aes
-#define ARMV8_4A	&aarch64_feature_v8_4a
 #define SHA3		&aarch64_feature_sha3
 #define SM4		&aarch64_feature_sm4
 #define FP_F16_V8_2A	&aarch64_feature_fp_16_v8_2a
 #define DOTPROD		&aarch64_feature_dotprod
-#define ARMV8_5A	&aarch64_feature_v8_5a
 #define FLAGMANIP	&aarch64_feature_flagmanip
 #define FRINTTS		&aarch64_feature_frintts
 #define SB		&aarch64_feature_sb
@@ -2668,8 +2649,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
 #define SME2		&aarch64_feature_sme2
 #define SME2_I16I64	&aarch64_feature_sme2_i16i64
 #define SME2_F64F64	&aarch64_feature_sme2_f64f64
-#define ARMV8_6A		&aarch64_feature_v8_6a
-#define ARMV8_6A_SVE		&aarch64_feature_v8_6a
 #define BFLOAT16_SVE	&aarch64_feature_bfloat16_sve
 #define BFLOAT16	&aarch64_feature_bfloat16
 #define I8MM_SVE      &aarch64_feature_i8mm_sve
@@ -2677,7 +2656,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
 #define F64MM_SVE     &aarch64_feature_f64mm_sve
 #define I8MM      &aarch64_feature_i8mm
 #define ARMV8R	  &aarch64_feature_v8r
-#define ARMV8_7A  &aarch64_feature_v8_7a
 #define LS64	  &aarch64_feature_ls64
 #define FLAGM	  &aarch64_feature_flagm
 #define XS	  &aarch64_feature_xs
@@ -2715,16 +2693,12 @@ static const aarch64_feature_set aarch64_feature_d128_the =
   { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS)		\
   { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, 0, NULL }
-#define V8_2A_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, OP, ARMV8_2A, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
     FLAGS | F_STRICT, 0, TIED, NULL }
 #define _SVE_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
     FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
-#define V8_3A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, 0, ARMV8_3A, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define PAC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, PAC, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
@@ -2739,8 +2713,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
   { NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, 0, NULL }
-#define V8_4A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, 0, ARMV8_4A, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -2749,8 +2721,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
   { NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2A, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, 0, NULL }
-#define V8_5A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, 0, ARMV8_5A, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define FLAGMANIP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, FLAGMANIP, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define FRINTTS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -2808,8 +2778,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
 #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
     FLAGS | F_STRICT, 0, TIED, NULL }
-#define V8_6A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, 0, ARMV8_6A, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define BFLOAT16_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
@@ -2829,8 +2797,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
   { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
 #define V8R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL }
-#define V8_7A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, 0, ARMV8_7A, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define XS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, XS, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define WFXT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \

Re: [PATCH 00/11] aarch64: New feature flags and flag fixes

[Nick Clifton]

Hi Andrew,

> This patch series adds new feature flags for instructions that are already
> present in Binutils, to allow the instructions to be enabled without specifying
> a higher architecture version.  With the exception of patch 11/11 (cleaning up
> dead code), each patch is independent of the others.
> 
> Aside from adding new feature flags (or otherwise eliminating architecture
> version dependencies), there are also three small bug fixes, in patches 1/11,
> 3/11 and 9/11.
> 
> I have run the tests affected by each commit after that commit, and I have also
> run the entire testsuite on the series as a whole, with no test failures.  Is
> this ok for master?  I don't have write access, so will need help to commit
> these.
> 
Patch series approved and applied.

Cheers
   Nick