From: Jan Beulich <jbeulich@suse.com>
To: "Cui, Lili" <lili.cui@intel.com>
Cc: "Lu, Hongjiu" <hongjiu.lu@intel.com>,
"ccoutant@gmail.com" <ccoutant@gmail.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: Re: [PATCH 4/8] Add tests for APX GPR32 with extend evex prefix
Date: Thu, 16 Nov 2023 10:17:16 +0100 [thread overview]
Message-ID: <3af119c3-4574-40e5-8799-0d88f19633a9@suse.com> (raw)
In-Reply-To: <SJ0PR11MB5600DF148480DF8D44AB8D7F9EB1A@SJ0PR11MB5600.namprd11.prod.outlook.com>
On 15.11.2023 15:56, Cui, Lili wrote:
>>> + phminposuw (%r23),%xmm4
>>> + pinsrb $100,%r23,%xmm4
>>> + pinsrb $100,(%r23),%xmm4
>>> + pinsrd $100, %r23d, %xmm4
>>> + pinsrd $100,(%r23),%xmm4
>>> + pinsrq $100, %r24, %xmm4
>>> + pinsrq $100,(%r24),%xmm4
>>> + pmaxsb (%r24),%xmm6
>>> + pmaxsd (%r24),%xmm6
>>> + pmaxud (%r24),%xmm6
>>> + pmaxuw (%r24),%xmm6
>>> + pminsb (%r24),%xmm6
>>> + pminsd (%r24),%xmm6
>>> + pminud (%r24),%xmm6
>>> + pminuw (%r24),%xmm6
>>> + pmovsxbw (%r24),%xmm4
>>> + pmovsxbd (%r24),%xmm4
>>> + pmovsxbq (%r24),%xmm4
>>> + pmovsxwd (%r24),%xmm4
>>> + pmovsxwq (%r24),%xmm4
>>> + pmovsxdq (%r24),%xmm4
>>> + pmovsxbw (%r24),%xmm4
>>> + pmovzxbd (%r24),%xmm4
>>> + pmovzxbq (%r24),%xmm4
>>> + pmovzxwd (%r24),%xmm4
>>> + pmovzxwq (%r24),%xmm4
>>> + pmovzxdq (%r24),%xmm4
>>> + pmuldq (%r24),%xmm4
>>> + pmulld (%r24),%xmm4
>>> + roundpd $100,(%r24),%xmm6
>>> + roundps $100,(%r24),%xmm6
>>> + roundsd $100,(%r24),%xmm6
>>> + roundss $100,(%r24),%xmm6
>>> + pcmpestri $100,(%r25),%xmm6
>>> + pcmpestrm $100,(%r25),%xmm6
>>> + pcmpgtq (%r25),%xmm4
>>> + pcmpistri $100,(%r25),%xmm6
>>> + pcmpistrm $100,(%r25),%xmm6
>>> +#AES
>>> + aesdec (%r26),%xmm6
>>> + aesdeclast (%r26),%xmm6
>>> + aesenc (%r26),%xmm6
>>> + aesenclast (%r26),%xmm6
>>> + aesimc (%r26),%xmm6
>>> + aeskeygenassist $100,(%r26),%xmm6
>>> + pclmulqdq $100,(%r26),%xmm6
>>> + pclmullqlqdq (%r26),%xmm6
>>> + pclmulhqlqdq (%r26),%xmm6
>>> + pclmullqhqdq (%r26),%xmm6
>>> + pclmulhqhqdq (%r26),%xmm6
>>> +#GFNI
>>> + gf2p8affineqb $100,(%r26),%xmm6
>>> + gf2p8affineinvqb $100,(%r26),%xmm6
>>> + gf2p8mulb (%r26),%xmm6
>>> +#VEX without evex
>>> + vblendpd $7,(%r27),%xmm6,%xmm2
>>> + vblendpd $7,(%r27),%ymm6,%ymm2
>>> + vblendps $7,(%r27),%xmm6,%xmm2
>>> + vblendps $7,(%r27),%ymm6,%ymm2
>>> + vblendvpd %xmm4,(%r27),%xmm2,%xmm7
>>> + vblendvpd %ymm4,(%r27),%ymm2,%ymm7
>>> + vblendvps %xmm4,(%r27),%xmm2,%xmm7
>>> + vblendvps %ymm4,(%r27),%ymm2,%ymm7
>>> + vdppd $7,(%r27),%xmm6,%xmm2
>>> + vdpps $7,(%r27),%xmm6,%xmm2
>>> + vdpps $7,(%r27),%ymm6,%ymm2
>>> + vhaddpd (%r27),%xmm6,%xmm5
>>> + vhaddpd (%r27),%ymm6,%ymm5
>>> + vhsubps (%r27),%xmm6,%xmm5
>>> + vhsubps (%r27),%ymm6,%ymm5
>>> + vlddqu (%r27),%xmm4
>>> + vlddqu (%r27),%ymm4
>>> + vldmxcsr (%r27)
>>
>> As mentioned before, for this, ...
>>
>>> + vmaskmovpd (%r27),%xmm4,%xmm6
>>> + vmaskmovpd %xmm4,%xmm6,(%r27)
>>> + vmaskmovps (%r27),%xmm4,%xmm6
>>> + vmaskmovps %xmm4,%xmm6,(%r27)
>>> + vmaskmovpd (%r27),%ymm4,%ymm6
>>> + vmaskmovpd %ymm4,%ymm6,(%r27)
>>> + vmaskmovps (%r27),%ymm4,%ymm6
>>> + vmaskmovps %ymm4,%ymm6,(%r27)
>>> + vmovmskpd %xmm4,%r27d
>>> + vmovmskpd %xmm8,%r27d
>>> + vmovmskps %xmm4,%r27d
>>> + vmovmskps %ymm8,%r27d
>>> + vpblendvb %xmm4,(%r27),%xmm2,%xmm7
>>> + vpblendvb %ymm4,(%r27),%ymm2,%ymm7
>>> + vpblendw $7,(%r27),%xmm6,%xmm2
>>> + vpblendw $7,(%r27),%ymm6,%ymm2
>>> + vpcmpestri $7,(%r27),%xmm6
>>> + vpcmpestrm $7,(%r27),%xmm6
>>> + vperm2f128 $7,(%r27),%ymm6,%ymm2
>>> + vphaddd (%r27),%xmm6,%xmm7
>>> + vphaddsw (%r27),%xmm6,%xmm7
>>> + vphaddw (%r27),%xmm6,%xmm7
>>> + vphsubd (%r27),%xmm6,%xmm7
>>> + vphsubsw (%r27),%xmm6,%xmm7
>>> + vphsubw (%r27),%xmm6,%xmm7
>>> + vphaddd (%r27),%ymm6,%ymm7
>>> + vphaddsw (%r27),%ymm6,%ymm7
>>> + vphaddw (%r27),%ymm6,%ymm7
>>> + vphsubd (%r27),%ymm6,%ymm7
>>> + vphsubsw (%r27),%ymm6,%ymm7
>>> + vphsubw (%r27),%ymm6,%ymm7
>>> + vphminposuw (%r27),%xmm6
>>> + vpmovmskb %xmm4,%r27
>>> + vpmovmskb %ymm4,%r27d
>>> + vpsignb (%r27),%xmm6,%xmm7
>>> + vpsignw (%r27),%xmm6,%xmm7
>>> + vpsignd (%r27),%xmm6,%xmm7
>>> + vpsignb (%r27),%xmm6,%xmm7
>>> + vpsignw (%r27),%xmm6,%xmm7
>>> + vpsignd (%r27),%xmm6,%xmm7
>>> + vptest (%r27),%xmm6
>>> + vptest (%r27),%ymm6
>>> + vrcpps (%r27),%xmm6
>>> + vrcpps (%r27),%ymm6
>>> + vrcpss (%r27),%xmm6,%xmm6
>>> + vrsqrtps (%r27),%xmm6
>>> + vrsqrtps (%r27),%ymm6
>>> + vrsqrtss (%r27),%xmm6,%xmm6
>>> + vstmxcsr (%r27)
>>
>> ... this, and ...
>>
>>> + vtestps (%r27),%xmm6
>>> + vtestps (%r27),%ymm6
>>> + vtestpd (%r27),%xmm6
>>> + vtestps (%r27),%ymm6
>>> + vtestpd (%r27),%ymm6
>>> + vpblendd $7,(%r27),%xmm6,%xmm2
>>> + vpblendd $7,(%r27),%ymm6,%ymm2
>>> + vperm2i128 $7,(%r27),%ymm6,%ymm2
>>> + vpmaskmovd (%r27),%xmm4,%xmm6
>>> + vpmaskmovd %xmm4,%xmm6,(%r27)
>>> + vpmaskmovq (%r27),%xmm4,%xmm6
>>> + vpmaskmovq %xmm4,%xmm6,(%r27)
>>> + vpmaskmovd (%r27),%ymm4,%ymm6
>>> + vpmaskmovd %ymm4,%ymm6,(%r27)
>>> + vpmaskmovq (%r27),%ymm4,%ymm6
>>> + vpmaskmovq %ymm4,%ymm6,(%r27)
>>> + vaesimc (%r27), %xmm3
>>> + vaeskeygenassist $7,(%r27),%xmm3
>>> + vroundpd $1,(%r24),%xmm6
>>> + vroundps $2,(%r24),%xmm6
>>> + vroundsd $3,(%r24),%xmm6,%xmm3
>>> + vroundss $4,(%r24),%xmm6,%xmm3
>>
>> ... and these four I wonder whether the documentation shouldn't at least
>> allow room for translating them, for there being functionally equivalent
>> encodings.
>
> Could you give an example with equivalent encodings? Thanks.
ldmxcsr (%r27)
stmxcsr (%r27)
vrndscalepd $1,(%r24),%xmm6
vrndscaleps $2,(%r24),%xmm6
vrndscalesd $3,(%r24),%xmm6,%xmm3
vrndscaless $4,(%r24),%xmm6,%xmm3
Of course for the former two the decision to not support EVEX-encoded
V{LD,ST}MXCSR needs to be firm, or else later on what these mnemonics
translate to (when using extended registers for addressing) would change.
Jan
next prev parent reply other threads:[~2023-11-16 9:17 UTC|newest]
Thread overview: 113+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-02 11:29 [PATCH v2 0/8] Support Intel APX EGPR Cui, Lili
2023-11-02 11:29 ` [PATCH 1/8] Support APX GPR32 with rex2 prefix Cui, Lili
2023-11-02 17:05 ` Jan Beulich
2023-11-03 6:20 ` Cui, Lili
2023-11-03 13:05 ` Jan Beulich
2023-11-03 14:19 ` Jan Beulich
2023-11-06 15:20 ` Cui, Lili
2023-11-06 16:08 ` Jan Beulich
2023-11-07 8:16 ` Cui, Lili
2023-11-07 10:43 ` Jan Beulich
2023-11-07 15:31 ` Cui, Lili
2023-11-07 15:43 ` Jan Beulich
2023-11-07 15:53 ` Cui, Lili
2023-11-06 15:02 ` Jan Beulich
2023-11-07 8:06 ` Cui, Lili
2023-11-07 10:20 ` Jan Beulich
2023-11-07 14:32 ` Cui, Lili
2023-11-07 15:08 ` Jan Beulich
2023-11-06 15:39 ` Jan Beulich
2023-11-09 8:02 ` Cui, Lili
2023-11-09 10:52 ` Jan Beulich
2023-11-09 13:27 ` Cui, Lili
2023-11-09 15:22 ` Jan Beulich
2023-11-10 7:11 ` Cui, Lili
2023-11-10 9:14 ` Jan Beulich
2023-11-10 9:21 ` Jan Beulich
2023-11-10 12:38 ` Cui, Lili
2023-12-14 10:13 ` Cui, Lili
2023-12-18 15:24 ` Jan Beulich
2023-12-18 16:23 ` H.J. Lu
2023-11-10 9:47 ` Cui, Lili
2023-11-10 9:57 ` Jan Beulich
2023-11-10 12:05 ` Cui, Lili
2023-11-10 12:35 ` Jan Beulich
2023-11-13 0:18 ` Cui, Lili
2023-11-02 11:29 ` [PATCH 2/8] Created an empty EVEX_MAP4_ sub-table for EVEX instructions Cui, Lili
2023-11-02 11:29 ` [PATCH 3/8] Support APX GPR32 with extend evex prefix Cui, Lili
2023-11-02 11:29 ` [PATCH 4/8] Add tests for " Cui, Lili
2023-11-08 9:11 ` Jan Beulich
2023-11-15 14:56 ` Cui, Lili
2023-11-16 9:17 ` Jan Beulich [this message]
2023-11-16 15:34 ` Cui, Lili
2023-11-16 16:50 ` Jan Beulich
2023-11-17 12:42 ` Cui, Lili
2023-11-17 14:38 ` Jan Beulich
2023-11-22 13:40 ` Cui, Lili
2023-11-02 11:29 ` [PATCH 5/8] Support APX NDD Cui, Lili
2023-11-08 10:39 ` Jan Beulich
2023-11-20 1:19 ` Cui, Lili
2023-11-08 11:13 ` Jan Beulich
2023-11-20 12:36 ` Cui, Lili
2023-11-20 16:33 ` Jan Beulich
2023-11-22 7:46 ` Cui, Lili
2023-11-22 8:47 ` Jan Beulich
2023-11-22 10:45 ` Cui, Lili
2023-11-23 10:57 ` Jan Beulich
2023-11-23 12:14 ` Cui, Lili
2023-11-24 6:56 ` [PATCH v3 0/9] Support Intel APX EGPR Cui, Lili
2023-12-07 8:17 ` Cui, Lili
2023-12-07 8:33 ` Cui, Lili
2023-11-09 9:37 ` [PATCH 5/8] Support APX NDD Jan Beulich
2023-11-20 1:33 ` Cui, Lili
2023-11-20 8:19 ` Jan Beulich
2023-11-20 12:54 ` Cui, Lili
2023-11-20 16:43 ` Jan Beulich
2023-11-02 11:29 ` [PATCH 6/8] Support APX Push2/Pop2 Cui, Lili
2023-11-08 11:44 ` Jan Beulich
2023-11-08 12:52 ` Jan Beulich
2023-11-22 5:48 ` Cui, Lili
2023-11-22 8:53 ` Jan Beulich
2023-11-22 12:26 ` Cui, Lili
2023-11-09 9:57 ` Jan Beulich
2023-11-02 11:29 ` [PATCH 7/8] Support APX NDD optimized encoding Cui, Lili
2023-11-09 10:36 ` Jan Beulich
2023-11-10 5:43 ` Hu, Lin1
2023-11-10 9:54 ` Jan Beulich
2023-11-14 2:28 ` Hu, Lin1
2023-11-14 10:50 ` Jan Beulich
2023-11-15 2:52 ` Hu, Lin1
2023-11-15 8:57 ` Jan Beulich
2023-11-15 2:59 ` [PATCH][v3] " Hu, Lin1
2023-11-15 9:34 ` Jan Beulich
2023-11-17 7:24 ` Hu, Lin1
2023-11-17 9:47 ` Jan Beulich
2023-11-20 3:28 ` Hu, Lin1
2023-11-20 8:34 ` Jan Beulich
2023-11-14 2:58 ` [PATCH 1/2] Reorder APX insns in i386.tbl Hu, Lin1
2023-11-14 11:20 ` Jan Beulich
2023-11-15 1:49 ` Hu, Lin1
2023-11-15 8:52 ` Jan Beulich
2023-11-17 3:27 ` Hu, Lin1
2023-11-02 11:29 ` [PATCH 8/8] Support APX JMPABS Cui, Lili
2023-11-09 12:59 ` Jan Beulich
2023-11-14 3:26 ` Hu, Lin1
2023-11-14 11:15 ` Jan Beulich
2023-11-24 5:40 ` Hu, Lin1
2023-11-24 7:21 ` Jan Beulich
2023-11-27 2:16 ` Hu, Lin1
2023-11-27 8:03 ` Jan Beulich
2023-11-27 8:46 ` Hu, Lin1
2023-11-27 8:54 ` Jan Beulich
2023-11-27 9:03 ` Hu, Lin1
2023-11-27 10:32 ` Jan Beulich
2023-12-04 7:33 ` Hu, Lin1
2023-11-02 13:22 ` [PATCH v2 0/8] Support Intel APX EGPR Jan Beulich
2023-11-03 16:42 ` Cui, Lili
2023-11-06 7:30 ` Jan Beulich
2023-11-06 14:20 ` Cui, Lili
2023-11-06 14:44 ` Jan Beulich
2023-11-06 16:03 ` Cui, Lili
2023-11-06 16:10 ` Jan Beulich
2023-11-07 1:53 ` Cui, Lili
2023-11-07 10:11 ` Jan Beulich
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