RE: [PATCH v2 0/8] Support Intel APX EGPR

["Cui, Lili" <lili.cui@intel.com>]

> Subject: Re: [PATCH v2 0/8] Support Intel APX EGPR
> 
> On 02.11.2023 12:29, Cui, Lili wrote:
> > This is V2 of all APX patch.
> > 1. Merged patch part II 1/6 into patch 1/8.
> > 2. Created a new patch for empty EVEX_MAP4_ sub-table.
> > 3. The NF patch needs to be suspended, Where NF should be placed is
> under discussion. Since the patch part II 2/6 depends on the NF patch, it is
> also suspended.
> > 4. There are no comments yet for APX linker patch.
> >
> >
> > Cui, Lili (4):
> >   Support APX GPR32 with rex2 prefix
> >   Created an empty EVEX_MAP4_ sub-table for EVEX instructions.
> >   Support APX GPR32 with extend evex prefix
> >   Add tests for APX GPR32 with extend evex prefix
> >
> > Hu, Lin1 (2):
> >   Support APX NDD optimized encoding.
> >   Support APX JMPABS
> >
> > Mo, Zewei (1):
> >   Support APX Push2/Pop2
> >
> > konglin1 (1):
> >   Support APX NDD
> 
> Mind me asking whether this work is now based on my "x86: split insn
> templates' CPU field"? You don't say so here, so my initial assumption would
> be that it isn't. That's also supported by me peeking at patch 3.
> Yet that patch was specifically created as a prereq for the APX work to base on
> top (and it may require further refinement, the need for which I could only
> know once you're actually using that patch as a prereq).
> 

Sorry for missing this patch, I rebased patch3 on it.  this patch works without my old code. I will sent out new patch3.

+//       else if (x.bitfield.cpuapx_f)
+//         {
+//           /* All cpu in x need to be enabled in cpu_arch_flags.  */
+//           if (cpu_flags_not_or_check (&x, &cpu_arch_flags))
+//             match |= CPU_FLAGS_ARCH_MATCH;
+//         }


AMX can works with the following changing. 
--------------------------------------------------------
opcodes/i386-opc.tbl:

#define APX_F_64 APX_F&x64
ldtilecfg, 0x49/0, AMX_TILE&x64&(AMX_TILE|APX_F), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }

gas/config/tc-i386.c:

   if (t->opcode_modifier.vex && t->opcode_modifier.evex)
   {
-      if ((maybe_cpu (t, CpuAVX) || maybe_cpu (t, CpuAVX2)
-          || maybe_cpu (t, CpuFMA))
-         && (maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512VL)))
+    if ((maybe_cpu (t, CpuAVX) || maybe_cpu (t, CpuAVX2)
+        || maybe_cpu (t, CpuFMA) ||  maybe_cpu (t, CpuAMX_TILE))
+       && (maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512VL)
+           || maybe_cpu (t, CpuAPX_F)))
        {
          if (need_evex_encoding ())
            {
@@ -3725,7 +3726,7 @@ install_template (const insn_template *t)
                i.tm.cpu.bitfield.cpuavx = 1;
              else
                {
-                 gas_assert (!i.tm.cpu.bitfield.isa);
+//               gas_assert (!i.tm.cpu.bitfield.isa);
                  i.tm.cpu.bitfield.isa = i.tm.cpu_any.bitfield.isa;
                }
            }
-----------------------------------------------------------------

But if we want to merge bextr's vex and evex formats, we need to support BMI&(BMI |( APX_F&x64))
....
bextr, 0xf7, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
bextr, 0xf7, BMI&APX_F_64, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_b
...

Thanks,
Lili.