RE: [PATCH][v3] Support APX NDD optimized encoding.

["Hu, Lin1" <lin1.hu@intel.com>]

> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Wednesday, November 15, 2023 5:35 PM
> To: Hu, Lin1 <lin1.hu@intel.com>
> Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org
> Subject: Re: [PATCH][v3] Support APX NDD optimized encoding.
> 
> On 15.11.2023 03:59, Hu, Lin1 wrote:
> > --- a/gas/config/tc-i386.c
> > +++ b/gas/config/tc-i386.c
> > @@ -7208,6 +7208,43 @@ check_EgprOperands (const insn_template *t)
> >    return 0;
> >  }
> >
> > +/* Optimize APX NDD insns to legacy insns.  */ static bool
> > +convert_NDD_to_REX2 (const insn_template *t) {
> > +  if (t->opcode_modifier.vexvvvv == VexVVVV_DST
> > +      && t->opcode_space == SPACE_EVEXMAP4
> > +      && !i.has_nf
> > +      && i.reg_operands >= 2)
> > +    {
> > +      unsigned int readonly_var = ~0;
> > +      unsigned int dest = i.operands - 1;
> > +      unsigned int src1 = i.operands - 2;
> > +      unsigned int src2 = (i.operands > 3) ? i.operands - 3 : 0;
> > +
> > +      if (i.types[src1].bitfield.class == Reg
> > +	  && i.op[src1].regs == i.op[dest].regs)
> > +	readonly_var = src2;
> > +      /* adcx, adox and imul can't support to swap the source operands.  */
> > +      else if (i.types[src2].bitfield.class == Reg
> > +	       && i.op[src2].regs == i.op[dest].regs
> > +	       && optimize > 1
> > +	       && t->opcode_modifier.commutative)
> 
> Comment and code still aren't in line: "support to swap the source
> operands"
> really is the D attribute in the opcode table, whereas
> t->opcode_modifier.commutative is related to the C attribute (and all
> t->three
> insns named really are commutative). It looks to me that the code is correct,
> so it would then be the comment that may need updating. But it may also
> be better to additionally check .d here (making the code robust against C
> being added to the truly commutative yet not eligible to be optimized insns).
> In which case the comment might say "adcx, adox, and imul, while
> commutative, don't support to swap the source operands".
>

I think we don't need to worry about it for now, because we've constrained the function with vexvvvvvvdest, and these instructions must be NDD instructions. And adcx, adox and imul don't have D attribute. If I add check .d here, I will need to exclude them. The code will back, which we had initially hoped to avoid by using C.

>
> > +	readonly_var = src1;
> > +      if (readonly_var != (unsigned int) ~0)
> > +	{
> > +	  if (readonly_var != src2)
> > +	    swap_2_operands (readonly_var, src2);
> > +
> > +	  --i.operands;
> > +	  --i.reg_operands;
> > +
> > +	  return true;
> > +	}
> > +    }
> > +  return false;
> > +}
> > +
> >  /* Helper function for the progress() macro in match_template().  */
> > static INLINE enum i386_error progress (enum i386_error new,
> >  					enum i386_error last,
> > @@ -7728,6 +7765,21 @@ match_template (char mnem_suffix)
> >  	  i.memshift = memshift;
> >  	}
> >
> > +      /* If we can optimize a NDD insn to non-NDD insn, like
> 
> The terminology here wants to match the function name below, i.e. (as
> indicated elsewhere for the name, in reply to your question) "legacy"
> instead of "non-NDD" (assuming the function name is changed as well, in
> line with that).
>

OK.

> 
> > +	 add %r16, %r8, %r8 -> add %r16, %r8,
> > +	 add  %r8, %r16, %r8 -> add %r16, %r8, then rematch template.
> > +	 Note that the semantics have not been changed.  */
> > +      if (optimize
> > +	  && !i.no_optimize
> > +	  && i.vec_encoding != vex_encoding_evex
> > +	  && t + 1 < current_templates->end
> > +	  && !t[1].opcode_modifier.evex
> 
> This is more fragile than it needs to be; it would imo be better to indeed go
> from opcode space of the supposed alternative encoding. Perhaps that's
> going to mean checking both.
>

Based on our previous discussion, I modified tc-i386.c as follows

+/* Check if the instruction use the REX registers.  */
+static bool
+check_RexOperands (const insn_template *t)
+{
+  for (unsigned int op = 0; op < i.operands; op++)
+    {
+      if (i.types[op].bitfield.class != Reg
+         /* Special case for (%dx) while doing input/output op */
+         || i.input_output_operand)
+       continue;
+
+      if (i.op[op].regs->reg_flags & (RegRex | RegRex64))
+       return true;
+    }
+
+  if ((i.index_reg && (i.index_reg->reg_flags & (RegRex | RegRex64)))
+      || (i.base_reg && (i.base_reg->reg_flags & (RegRex | RegRex64))))
+    return true;
+
+  /* Check pseudo prefix {rex} are valid.  */
+  if (i.rex_encoding)
+    return true;
+  return false;
+}
+
+/* Optimize APX NDD insns to legacy insns.  */
+static unsigned int
+convert_NDD_to_legacy (const insn_template *t)
+{
+  unsigned int readonly_var = ~0;
+
+  if (t->opcode_modifier.vexvvvv == VexVVVV_DST
+      && t->opcode_space == SPACE_EVEXMAP4
+      && !i.has_nf
+      && i.reg_operands >= 2)
+    {
+      unsigned int dest = i.operands - 1;
+      unsigned int src1 = i.operands - 2;
+      unsigned int src2 = (i.operands > 3) ? i.operands - 3 : 0;
+
+      if (i.types[src1].bitfield.class == Reg
+         && i.op[src1].regs == i.op[dest].regs)
+       readonly_var = src2;
+      /* adcx, adox, and imul, while commutative, don't support to swap
+        the source operands.  */
+      else if (i.types[src2].bitfield.class == Reg
+              && i.op[src2].regs == i.op[dest].regs
+              && optimize > 1
+              && t->opcode_modifier.commutative)
+       readonly_var = src1;
+    }
+  return readonly_var;
+}
+

@@ -7728,6 +7782,55 @@ match_template (char mnem_suffix)
          i.memshift = memshift;
        }

+      /* If we can optimize a NDD insn to legacy insn, like
+        add %r16, %r8, %r8 -> add %r16, %r8,
+        add  %r8, %r16, %r8 -> add %r16, %r8, then rematch template.
+        Note that the semantics have not been changed.  */
+      if (optimize
+         && !i.no_optimize
+         && i.vec_encoding != vex_encoding_evex
+         && t + 1 < current_templates->end
+         && !t[1].opcode_modifier.evex
+         && t[1].opcode_space <= SPACE_0F38)
+       {
+         unsigned int readonly_var = convert_NDD_to_legacy (t);
+         size_match = true;
+
+         if (readonly_var != (unsigned int) ~0)
+           {
+             for (j = 0; j < i.operands - 2; j++)
+               {
+                 check_register = j;
+                 if (t->opcode_modifier.d)
+                   check_register ^= 1;
+                 overlap0 = operand_type_and (i.types[check_register],
+                                              t[1].operand_types[check_register]);
+                 if (!operand_type_match (overlap0, i.types[check_register]))
+                   size_match = false;
+               }
+
+             if (size_match
+                 && (t[1].opcode_space <= SPACE_0F
+                     || (!check_EgprOperands (t + 1)	 // These conditions are exclude adcx/adox with inappropriate registers.
+                         && !check_RexOperands (t + 1)
+                         && !i.op[i.operands - 1].regs->reg_type.bitfield.qword)))
+               {
+                 unsigned int src1 = i.operands - 2;
+                 unsigned int src2 = (i.operands > 3) ? i.operands - 3 : 0;
+
+                 if (readonly_var != src2)
+                   swap_2_operands (readonly_var, src2);
+
+                 --i.operands;
+                 --i.reg_operands;
+
+                 specific_error = progress (internal_error);
+                 continue;
+               }
+
+           }
+       }
+
       /* We've found a match; break out of loop.  */
       break;

What's your opinion?

BRs,
Lin