From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Nelson Chu <nelson.chu@sifive.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set
Date: Fri, 25 Feb 2022 16:07:30 +0900 [thread overview]
Message-ID: <66686bc9-09c0-4b1b-9d06-c51270eb04c2@irq.a4lg.com> (raw)
In-Reply-To: <CAJYME4E1M+2LmXiOEqE9Wjijxt5y=EjjM58xAGS0Sh5MB6_zTA@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 3326 bytes --]
Hi Nelson,
I attached new rebased version of my CMO patches (for reference and
NOT an actual submission) so that you can test an example below.
| (Submission) (Attachment)
| PATCH 1/5 -> PATCH 1-2/2 (splitted and squashed)
| PATCH 4-5/5 -> PATCH 1/2 (squashed and order changed) p
| PATCH 2-3/5 -> PATCH 2/2 (squashed and order changed) m/z
This reorganization is mainly caused by following open issue:
<https://github.com/riscv/riscv-CMOs/issues/47>
I hope this is resolved soon so that I can submit the next version
without extra footnotes.
On 2022/02/25 11:50, Nelson Chu wrote:
> Hi Tsukasa,
>
> Reusing the q operand should be enough. Though we may add relocation
> when the offset is a symbol, I think this should be fine.
>
> Consider Christoph patch,
> https://sourceware.org/pipermail/binutils/2022-January/119262.html
>
> His patch is closer to the implementation I will do, just consider the
> compatibility of amo instructions should be perfect. However, you are
> adding more testcases than us. It would be always good to add more
> testcases, so except the f operand, your patches LGTM.
>
> Thanks
> Nelson
Unfortunately, simply reusing 'q' doesn't work.
For overflow checking, 'q' is fine.
On 2022/02/25 11:50, Nelson Chu wrote:>> case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
>> + case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
>
> I prefer to reuse the q operand here.
We may use simple fall-through here.
However, 32-byte alignment constraint requires a new operand type.
Let's see... assume that we change to use "q(s)" instead of "f(s)" (you
can just patch the patches I attached).
# BTW, I use minimal playground to test my GNU Binutils patches
# <https://github.com/a4lg/riscv-baremetal-playground>
# so that this example can be built and linked.
.globl _start
.section .entry, "ax", %progbits
_start:
.option arch,+zicbop
prefetch.i 0(t0)
# Remove Zicbop extension from final ELF
# to disassemble above instruction as `ori', not `prefetch.i'.
.option arch,-zicbop
ret
If we assemble above example (test.bare.S) and disassemble the result,
it should look like this:
0000000080000028 <_start>:
80000028: 0002e013 ori zero,t0,0
8000002c: 8082 ret
Looks great. But if we change 0(t0) to 1(t0), we DON'T get an error and
the result will look like...
0000000080000028 <_start>:
80000028: 0002e093 ori ra,t0,0
8000002c: 8082 ret
Oh no, a side effect (assignment to ra[x1]) without "illegal operands".
It happens because `match_opcode' for prefetch instructions (to test
instruction validity in `riscv_ip') is called before instruction bits
are modified. For store addresses, actual value insertion happens in
`md_apply_fix' function after "successfully assembled" in `riscv_ip'.
So, we need to test validity of the immediate constant (32-byte aligned)
somewhere. Even if we test it on fixup, it (at least) requires new
BFD relocation type (preventing reuse of case 'q' code path).
Of course, if we consider using relocations on prefetch instructions,
we could move, for instance, address insertion.
Still, we absolutely need something new to handle special 32-byte
alignment or we will risk generating corrupted programs.
Thanks,
Tsukasa
[-- Attachment #2: 0001-RISC-V-Prefetch-hint-instructions-and-operand-set.patch --]
[-- Type: text/plain, Size: 9157 bytes --]
From 2cf451c653352e6f5d1769f36a2a48f1d5820ae1 Mon Sep 17 00:00:00 2001
Message-Id: <2cf451c653352e6f5d1769f36a2a48f1d5820ae1.1645771895.git.research_trasio@irq.a4lg.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Tue, 11 Jan 2022 19:14:02 +0900
Subject: [PATCH 1/2] RISC-V: Prefetch hint instructions and operand set
This commit adds 'Zicbop' hint instructions and testcases.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zicbop'
standard 'Z' extension. (riscv_multi_subset_supports): Add
handling for new instruction class.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add handling for new operand
type 'f' (32-byte aligned pseudo S-type immediate for prefetch
hints).
(validate_riscv_insn): Likewise.
* testsuite/gas/riscv/zicbop-fail.d: New testcase for invalid
prefetch hint instructions.
* testsuite/gas/riscv/zicbop-fail.l: Likewise.
* testsuite/gas/riscv/zicbop-fail.s: Likewise.
* testsuite/gas/riscv/zicbop.d: New testcase for prefetch hint
instructions.
* testsuite/gas/riscv/zicbop.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
MASK_PREFETCH_W): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class INSN_CLASS_ZICBOP.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add handling for new operand
type.
* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
---
bfd/elfxx-riscv.c | 3 +++
gas/config/tc-riscv.c | 18 ++++++++++++++++++
gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zicbop.s | 4 ++++
include/opcode/riscv-opc.h | 7 +++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-dis.c | 4 ++++
opcodes/riscv-opc.c | 3 +++
11 files changed, 63 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicbop.d
create mode 100644 gas/testsuite/gas/riscv/zicbop.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index d74e7a584eb..83cd90d006a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1172,6 +1172,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
@@ -2319,6 +2320,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZICBOP:
+ return riscv_subset_supports (rps, "zicbop");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 322e0f070ba..966d08ced82 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1180,6 +1180,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
+ case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
case 'z': break; /* Zero immediate. */
case '[': break; /* Unused operand. */
@@ -3191,6 +3192,23 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
imm_expr->X_op = O_absent;
continue;
+ case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
+ if (riscv_handle_implicit_zero_offset (imm_expr, asarg))
+ continue;
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, false);
+ if (((unsigned) (imm_expr->X_add_number) & 0x1fU)
+ || imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2
+ || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2)
+ as_bad (_("improper prefetch offset (%ld)"),
+ (long) imm_expr->X_add_number);
+ ip->insn_opcode |=
+ ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) &
+ ~ 0x1fU);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
default:
unknown_riscv_ip_operand:
as_fatal (_("internal: unknown argument type `%s'"),
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.d b/gas/testsuite/gas/riscv/zicbop-fail.d
new file mode 100644
index 00000000000..d734c7d4d15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicbop
+#source: zicbop-fail.s
+#error_output: zicbop-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.l b/gas/testsuite/gas/riscv/zicbop-fail.l
new file mode 100644
index 00000000000..4b5d5fc84fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*: Error: improper prefetch offset \(2048\)
+.*: Error: improper prefetch offset \(-2080\)
+.*: Error: improper prefetch offset \(255\)
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.s b/gas/testsuite/gas/riscv/zicbop-fail.s
new file mode 100644
index 00000000000..0353c5ff80a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.s
@@ -0,0 +1,4 @@
+target:
+ prefetch.i 2048(x1)
+ prefetch.r -0x820(x16)
+ prefetch.w +0xff(x31)
diff --git a/gas/testsuite/gas/riscv/zicbop.d b/gas/testsuite/gas/riscv/zicbop.d
new file mode 100644
index 00000000000..056a8a501ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop.d
@@ -0,0 +1,12 @@
+#as: -march=rv64g_zicbop
+#source: zicbop.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0200e013[ ]+prefetch\.i[ ]+32\(ra\)
+[ ]+[0-9a-f]+:[ ]+80186013[ ]+prefetch\.r[ ]+-2048\(a6\)
+[ ]+[0-9a-f]+:[ ]+7e3fe013[ ]+prefetch\.w[ ]+2016\(t6\)
diff --git a/gas/testsuite/gas/riscv/zicbop.s b/gas/testsuite/gas/riscv/zicbop.s
new file mode 100644
index 00000000000..ffe2014be6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop.s
@@ -0,0 +1,4 @@
+target:
+ prefetch.i 0x20(x1)
+ prefetch.r -2048(x16)
+ prefetch.w +0x7e0(x31)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 01cd3a4e9dd..1572c84f0be 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2029,6 +2029,13 @@
#define MASK_HSV_W 0xfe007fff
#define MATCH_HSV_D 0x6e004073
#define MASK_HSV_D 0xfe007fff
+/* Zicbop hint instructions. */
+#define MATCH_PREFETCH_I 0x6013
+#define MASK_PREFETCH_I 0x1f07fff
+#define MATCH_PREFETCH_R 0x106013
+#define MASK_PREFETCH_R 0x1f07fff
+#define MATCH_PREFETCH_W 0x306013
+#define MASK_PREFETCH_W 0x1f07fff
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 048ab0a5d68..5462b5eceab 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -388,6 +388,7 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
+ INSN_CLASS_ZICBOP,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 34724d4aec5..57b798d8e14 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -424,6 +424,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
break;
+ case 'f':
+ print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
+ break;
+
case 'a':
info->target = EXTRACT_JTYPE_IMM (l) + pc;
(*info->print_address_func) (info->target, info);
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2da0f7cf0a4..bd200d736e5 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -388,6 +388,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
{"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS },
+{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
+{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
+{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
{"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
{"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
{"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
--
2.32.0
[-- Attachment #3: 0002-RISC-V-Cache-management-instructions.patch --]
[-- Type: text/plain, Size: 6954 bytes --]
From 596caba950482dd6a6dc0f564e9be9d56c81bb48 Mon Sep 17 00:00:00 2001
Message-Id: <596caba950482dd6a6dc0f564e9be9d56c81bb48.1645771895.git.research_trasio@irq.a4lg.com>
In-Reply-To: <2cf451c653352e6f5d1769f36a2a48f1d5820ae1.1645771895.git.research_trasio@irq.a4lg.com>
References: <2cf451c653352e6f5d1769f36a2a48f1d5820ae1.1645771895.git.research_trasio@irq.a4lg.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Tue, 11 Jan 2022 19:14:02 +0900
Subject: [PATCH 2/2] RISC-V: Cache management instructions
This commit adds 'Zicbom' / 'Zicboz' instructions and testcases.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zicbom' and
'Zicboz' standard 'Z' extensions. (riscv_multi_subset_supports):
Add handling for new instruction classes.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
gas/ChangeLog:
* testsuite/gas/riscv/zicbom.d: New cache-block management
instruction tests.
* testsuite/gas/riscv/zicbom.s: Likewise.
* testsuite/gas/riscv/zicboz.d: New cache-block zero instruction
tests.
* testsuite/gas/riscv/zicboz.s: Likewise.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add cache-block management
instructions.
---
bfd/elfxx-riscv.c | 6 ++++++
gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
gas/testsuite/gas/riscv/zicboz.d | 11 +++++++++++
gas/testsuite/gas/riscv/zicboz.s | 3 +++
include/opcode/riscv-opc.h | 9 +++++++++
include/opcode/riscv.h | 2 ++
opcodes/riscv-opc.c | 6 ++++++
8 files changed, 59 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbom.d
create mode 100644 gas/testsuite/gas/riscv/zicbom.s
create mode 100644 gas/testsuite/gas/riscv/zicboz.d
create mode 100644 gas/testsuite/gas/riscv/zicboz.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 83cd90d006a..b761b590dd0 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1172,7 +1172,9 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
@@ -2320,8 +2322,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZICBOM:
+ return riscv_subset_supports (rps, "zicbom");
case INSN_CLASS_ZICBOP:
return riscv_subset_supports (rps, "zicbop");
+ case INSN_CLASS_ZICBOZ:
+ return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbom.d
new file mode 100644
index 00000000000..3a194cf6edf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.d
@@ -0,0 +1,15 @@
+#as: -march=rv64g_zicbom
+#source: zicbom.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0010a00f[ ]+cbo\.clean[ ]+ra
+[ ]+[0-9a-f]+:[ ]+001f200f[ ]+cbo\.clean[ ]+t5
+[ ]+[0-9a-f]+:[ ]+0020a00f[ ]+cbo\.flush[ ]+ra
+[ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+t5
+[ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+ra
+[ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+t5
diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
new file mode 100644
index 00000000000..778a61e76f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean x1
+ cbo.clean x30
+ cbo.flush x1
+ cbo.flush x30
+ cbo.inval x1
+ cbo.inval x30
diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
new file mode 100644
index 00000000000..7686edbe677
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.d
@@ -0,0 +1,11 @@
+#as: -march=rv64g_zicboz
+#source: zicboz.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+ra
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+t5
diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
new file mode 100644
index 00000000000..ba75b787b00
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.s
@@ -0,0 +1,3 @@
+target:
+ cbo.zero x1
+ cbo.zero x30
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1572c84f0be..3eea33a5dae 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2036,6 +2036,15 @@
#define MASK_PREFETCH_R 0x1f07fff
#define MATCH_PREFETCH_W 0x306013
#define MASK_PREFETCH_W 0x1f07fff
+/* Zicbom/Zicboz instructions. */
+#define MATCH_CBO_CLEAN 0x10200f
+#define MASK_CBO_CLEAN 0xfff07fff
+#define MATCH_CBO_FLUSH 0x20200f
+#define MASK_CBO_FLUSH 0xfff07fff
+#define MATCH_CBO_INVAL 0x200f
+#define MASK_CBO_INVAL 0xfff07fff
+#define MATCH_CBO_ZERO 0x40200f
+#define MASK_CBO_ZERO 0xfff07fff
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 5462b5eceab..b769769b4ec 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -388,7 +388,9 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
+ INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
+ INSN_CLASS_ZICBOZ,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bd200d736e5..c472c6d3252 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -852,6 +852,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+/* Zicbom and Zicboz instructions. */
+{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
+{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
+{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
+{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
+
/* Zbb or zbkb instructions. */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
--
2.32.0
next prev parent reply other threads:[~2022-02-25 7:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
2022-02-09 2:29 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
2022-02-09 2:29 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
2022-02-09 2:29 ` [PATCH 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
2022-02-09 2:29 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
2022-02-25 2:50 ` Nelson Chu
2022-02-25 7:07 ` Tsukasa OI [this message]
2022-03-18 7:50 ` Nelson Chu
2022-02-09 2:29 ` [PATCH 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
2022-04-01 3:33 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Palmer Dabbelt
2022-04-01 4:04 ` Kito Cheng
2022-04-01 4:15 ` Palmer Dabbelt
-- strict thread matches above, loose matches on Subject: below --
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
2021-12-16 11:04 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
2021-12-17 15:15 ` Nelson Chu
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