From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH 2/5] RISC-V: Cache management instructions
Date: Wed, 9 Feb 2022 11:29:29 +0900 [thread overview]
Message-ID: <ea2ab0537f7c2b6b1194189b289efe43f752abcc.1644373764.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1644373764.git.research_trasio@irq.a4lg.com>
This commit adds 'Zicbom' / 'Zicboz' instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction classes.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add cache-block management
instructions.
---
bfd/elfxx-riscv.c | 4 ++++
include/opcode/riscv-opc.h | 9 +++++++++
include/opcode/riscv.h | 2 ++
opcodes/riscv-opc.c | 6 ++++++
4 files changed, 21 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 3761811d4fd..a7cd9320655 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2334,6 +2334,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZICBOM:
+ return riscv_subset_supports (rps, "zicbom");
+ case INSN_CLASS_ZICBOZ:
+ return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 0b8cc6c7ddb..b24e8a47c87 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2029,6 +2029,15 @@
#define MASK_HSV_W 0xfe007fff
#define MATCH_HSV_D 0x6e004073
#define MASK_HSV_D 0xfe007fff
+/* Zicbom/Zicboz instructions. */
+#define MATCH_CBO_CLEAN 0x10200f
+#define MASK_CBO_CLEAN 0xfff07fff
+#define MATCH_CBO_FLUSH 0x20200f
+#define MASK_CBO_FLUSH 0xfff07fff
+#define MATCH_CBO_INVAL 0x200f
+#define MASK_CBO_INVAL 0xfff07fff
+#define MATCH_CBO_ZERO 0x40200f
+#define MASK_CBO_ZERO 0xfff07fff
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 048ab0a5d68..1d74f0e521a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -388,6 +388,8 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
+ INSN_CLASS_ZICBOM,
+ INSN_CLASS_ZICBOZ,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2da0f7cf0a4..f092e975bd8 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+/* Zicbom and Zicboz instructions. */
+{"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
+{"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
+{"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
+{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
+
/* Zbb or zbkb instructions. */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
--
2.32.0
next prev parent reply other threads:[~2022-02-09 2:29 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
2022-02-09 2:29 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
2022-02-09 2:29 ` Tsukasa OI [this message]
2022-02-09 2:29 ` [PATCH 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
2022-02-09 2:29 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
2022-02-25 2:50 ` Nelson Chu
2022-02-25 7:07 ` Tsukasa OI
2022-03-18 7:50 ` Nelson Chu
2022-02-09 2:29 ` [PATCH 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
2022-04-01 3:33 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Palmer Dabbelt
2022-04-01 4:04 ` Kito Cheng
2022-04-01 4:15 ` Palmer Dabbelt
-- strict thread matches above, loose matches on Subject: below --
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
2021-12-16 11:04 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
2022-01-04 8:01 ` Jan Beulich
2022-01-04 22:15 ` Andrew Waterman
2022-01-05 3:17 ` Tsukasa OI
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