From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH 3/5] RISC-V: Cache management instruction testcases
Date: Wed, 9 Feb 2022 11:29:30 +0900 [thread overview]
Message-ID: <bb216ea6c16b9f454c1bc117588e348b70c610ec.1644373764.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1644373764.git.research_trasio@irq.a4lg.com>
This commit adds testcases for 'Zicbom' / 'Zicboz' instructions.
* testsuite/gas/riscv/zicbom.d: New cache-block management
instruction tests.
* testsuite/gas/riscv/zicbom.s: Likewise.
* testsuite/gas/riscv/zicbom-fail.d: New cache-block management
instruction failure tests.
* testsuite/gas/riscv/zicbom-fail.l: Likewise.
* testsuite/gas/riscv/zicbom-fail.s: Likewise.
* testsuite/gas/riscv/zicboz.d: New cache-block zero instruction
tests.
* testsuite/gas/riscv/zicboz.s: Likewise.
* testsuite/gas/riscv/zicboz-fail.d: New cache-block zero
instruction failure tests.
* testsuite/gas/riscv/zicboz-fail.l: Likewise.
* testsuite/gas/riscv/zicboz-fail.s: Likewise.
---
gas/testsuite/gas/riscv/zicbom-fail.d | 3 +++
gas/testsuite/gas/riscv/zicbom-fail.l | 7 +++++++
gas/testsuite/gas/riscv/zicbom-fail.s | 7 +++++++
gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
gas/testsuite/gas/riscv/zicboz-fail.d | 3 +++
gas/testsuite/gas/riscv/zicboz-fail.l | 3 +++
gas/testsuite/gas/riscv/zicboz-fail.s | 3 +++
gas/testsuite/gas/riscv/zicboz.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zicboz.s | 4 ++++
10 files changed, 64 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicbom.d
create mode 100644 gas/testsuite/gas/riscv/zicbom.s
create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicboz.d
create mode 100644 gas/testsuite/gas/riscv/zicboz.s
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.d b/gas/testsuite/gas/riscv/zicbom-fail.d
new file mode 100644
index 00000000000..a6a61dfd37e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicbom
+#source: zicbom-fail.s
+#error_output: zicbom-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.l b/gas/testsuite/gas/riscv/zicbom-fail.l
new file mode 100644
index 00000000000..8b8eab54301
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom-fail.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cbo.clean 1\(x1\)'
+.*: Error: illegal operands `cbo.clean x30'
+.*: Error: illegal operands `cbo.flush \(0\+1\)\(x1\)'
+.*: Error: illegal operands `cbo.flush x30'
+.*: Error: illegal operands `cbo.inval \(3\*2\)\(x1\)'
+.*: Error: illegal operands `cbo.inval x30'
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.s b/gas/testsuite/gas/riscv/zicbom-fail.s
new file mode 100644
index 00000000000..11133ff75d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom-fail.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean 1(x1)
+ cbo.clean x30
+ cbo.flush (0+1)(x1)
+ cbo.flush x30
+ cbo.inval (3*2)(x1)
+ cbo.inval x30
diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbom.d
new file mode 100644
index 00000000000..edd8a7079f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.d
@@ -0,0 +1,15 @@
+#as: -march=rv64g_zicbom
+#source: zicbom.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0010a00f[ ]+cbo\.clean[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+001f200f[ ]+cbo\.clean[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0020a00f[ ]+cbo\.flush[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+\(t5\)
diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
new file mode 100644
index 00000000000..463a6b3ebb4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean (x1)
+ cbo.clean 0(x30)
+ cbo.flush (x1)
+ cbo.flush (2-2)(x30)
+ cbo.inval (x1)
+ cbo.inval (3*4-12)(x30)
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.d b/gas/testsuite/gas/riscv/zicboz-fail.d
new file mode 100644
index 00000000000..74cfd2fc911
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicboz
+#source: zicboz-fail.s
+#error_output: zicboz-fail.l
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.l b/gas/testsuite/gas/riscv/zicboz-fail.l
new file mode 100644
index 00000000000..0a19d3323c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cbo.zero x1'
+.*: Error: illegal operands `cbo.zero 1\(x30\)'
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.s b/gas/testsuite/gas/riscv/zicboz-fail.s
new file mode 100644
index 00000000000..b524cb6e269
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz-fail.s
@@ -0,0 +1,3 @@
+target:
+ cbo.zero x1
+ cbo.zero 1(x30)
diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
new file mode 100644
index 00000000000..7e47ad72610
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.d
@@ -0,0 +1,12 @@
+#as: -march=rv64g_zicboz
+#source: zicboz.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
new file mode 100644
index 00000000000..ca5efb5ce24
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.s
@@ -0,0 +1,4 @@
+target:
+ cbo.zero 0(x1)
+ cbo.zero (x30)
+ cbo.zero (2-2)(x1)
--
2.32.0
next prev parent reply other threads:[~2022-02-09 2:29 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
2022-02-09 2:29 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
2022-02-09 2:29 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
2022-02-09 2:29 ` Tsukasa OI [this message]
2022-02-09 2:29 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
2022-02-25 2:50 ` Nelson Chu
2022-02-25 7:07 ` Tsukasa OI
2022-03-18 7:50 ` Nelson Chu
2022-02-09 2:29 ` [PATCH 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
2022-04-01 3:33 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Palmer Dabbelt
2022-04-01 4:04 ` Kito Cheng
2022-04-01 4:15 ` Palmer Dabbelt
-- strict thread matches above, loose matches on Subject: below --
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
2021-12-16 11:04 ` [PATCH 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
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