From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 03/11] RISC-V: Make mapping symbol checking consistent
Date: Tue, 15 Nov 2022 04:52:46 +0000 [thread overview]
Message-ID: <6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1668487922.git.research_trasio@irq.a4lg.com>
There were two places where the mapping symbols are checked but had
different conditions.
- riscv_get_map_state: "$d" or starts with "$x"
- riscv_elf_is_mapping_symbols: Starts with either "$x" or "$d"
Considering recent mapping symbol proposal, it's better to make symbol
checking consistent (whether the symbol _starts_ with "$[xd]").
It only checks prefix "$xrv" (mapping symbol with ISA string) only when the
prefix "$x" is matched.
opcodes/ChangeLog:
* riscv-dis.c (riscv_get_map_state): Change the condition for
consistency.
---
opcodes/riscv-dis.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index ea45a631a25..d3bd4ceec1e 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -832,16 +832,17 @@ riscv_get_map_state (int n,
return false;
name = bfd_asymbol_name(info->symtab[n]);
- if (strcmp (name, "$x") == 0)
- *state = MAP_INSN;
- else if (strcmp (name, "$d") == 0)
- *state = MAP_DATA;
- else if (strncmp (name, "$xrv", 4) == 0)
+ if (startswith (name, "$x"))
{
+ if (startswith (name + 2, "rv"))
+ {
+ riscv_release_subset_list (&riscv_subsets);
+ riscv_parse_subset (&riscv_rps_dis, name + 2);
+ }
*state = MAP_INSN;
- riscv_release_subset_list (&riscv_subsets);
- riscv_parse_subset (&riscv_rps_dis, name + 2);
}
+ else if (startswith (name, "$d"))
+ *state = MAP_DATA;
else
return false;
--
2.37.2
next prev parent reply other threads:[~2022-11-15 4:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-15 4:52 [PATCH 00/11] RISC-V: Requirements for disassembler optimizations batch 1 Tsukasa OI
2022-11-15 4:52 ` [PATCH 01/11] opcodes/riscv-dis.c: More tidying Tsukasa OI
2022-11-15 4:52 ` [PATCH 02/11] RISC-V: Add test for 'Zfinx' register switching Tsukasa OI
2022-11-15 4:52 ` Tsukasa OI [this message]
2022-11-15 4:52 ` [PATCH 04/11] RISC-V: Split riscv_get_map_state into two steps Tsukasa OI
2022-11-15 4:52 ` [PATCH 05/11] RISC-V: One time CSR hash table initialization Tsukasa OI
2022-11-15 4:52 ` [PATCH 06/11] RISC-V: Use static xlen on ADDIW sequence Tsukasa OI
2022-11-15 4:52 ` [PATCH 07/11] opcodes/riscv-dis.c: Add form feed for separation Tsukasa OI
2022-11-15 4:52 ` [PATCH 08/11] RISC-V: Split match/print steps on disassembler Tsukasa OI
2022-11-15 4:52 ` [PATCH 09/11] RISC-V: Reorganize disassembler state initialization Tsukasa OI
2022-11-15 4:52 ` [PATCH 10/11] RISC-V: Reorganize arch-related initialization and management Tsukasa OI
2022-11-15 4:52 ` [PATCH 11/11] RISC-V: Move disassembler private data initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 00/11] RISC-V: Requirements for disassembler optimizations batch 1 Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 01/11] opcodes/riscv-dis.c: More tidying Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 02/11] RISC-V: Add test for 'Zfinx' register switching Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 03/11] RISC-V: Make mapping symbol checking consistent Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 04/11] RISC-V: Split riscv_get_map_state into two steps Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 05/11] RISC-V: One time CSR hash table initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 06/11] RISC-V: Use static xlen on ADDIW sequence Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 07/11] opcodes/riscv-dis.c: Add form feed for separation Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 08/11] RISC-V: Split match/print steps on disassembler Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 09/11] RISC-V: Reorganize disassembler state initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 10/11] RISC-V: Reorganize arch-related initialization and management Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 11/11] RISC-V: Move disassembler private data initialization Tsukasa OI
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