From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v2 02/11] RISC-V: Add test for 'Zfinx' register switching
Date: Mon, 28 Nov 2022 04:43:37 +0000 [thread overview]
Message-ID: <761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1669610611.git.research_trasio@irq.a4lg.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Because the author is going to reorganize core RISC-V disassembler, we have
to make sure that nothing is broken when disassembling with mapping symbols
with ISA string.
This commit adds a testcase for 'F' and 'Zfinx' instructions to make sure
that "FPR" register names are correctly switched when necessary.
gas/ChangeLog:
* testsuite/gas/riscv/mapping.s: Add 'F' and 'Zfinx' testcase.
* testsuite/gas/riscv/mapping-dis.d: Likewise.
* testsuite/gas/riscv/mapping-symbols.d: Likewise.
---
gas/testsuite/gas/riscv/mapping-dis.d | 7 +++++++
gas/testsuite/gas/riscv/mapping-symbols.d | 4 ++++
gas/testsuite/gas/riscv/mapping.s | 10 ++++++++++
3 files changed, 21 insertions(+)
diff --git a/gas/testsuite/gas/riscv/mapping-dis.d b/gas/testsuite/gas/riscv/mapping-dis.d
index b1a26fbd151b..f0508499b726 100644
--- a/gas/testsuite/gas/riscv/mapping-dis.d
+++ b/gas/testsuite/gas/riscv/mapping-dis.d
@@ -91,3 +91,10 @@ Disassembly of section .text.relax.align:
[ ]+[0-9a-f]+:[ ]+00000013[ ]+nop
[ ]+[0-9a-f]+:[ ]+00200513[ ]+li[ ]+a0,2
[ ]+[0-9a-f]+:[ ]+00000013[ ]+nop
+
+Disassembly of section .text.dis.zfinx:
+
+0+000 <.text.dis.zfinx>:
+[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2
+[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2
diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d b/gas/testsuite/gas/riscv/mapping-symbols.d
index 40df34097369..b28e3306b1b4 100644
--- a/gas/testsuite/gas/riscv/mapping-symbols.d
+++ b/gas/testsuite/gas/riscv/mapping-symbols.d
@@ -42,6 +42,10 @@ SYMBOL TABLE:
0+00 l d .text.relax.align 0+00 .text.relax.align
0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0
0+08 l .text.relax.align 0+00 \$xrv32i2p1
+0+00 l d .text.dis.zfinx 0+00 .text.dis.zfinx
+0+00 l .text.dis.zfinx 0+00 \$xrv32i2p1_f2p2_zicsr2p0
+0+04 l .text.dis.zfinx 0+00 \$xrv32i2p1_zicsr2p0_zfinx1p0
+0+08 l .text.dis.zfinx 0+00 \$xrv32i2p1_f2p2_zicsr2p0
0+0a l .text.section.padding 0+00 \$x
0+03 l .text.odd.align.start.insn 0+00 \$d
0+04 l .text.odd.align.start.insn 0+00 \$x
diff --git a/gas/testsuite/gas/riscv/mapping.s b/gas/testsuite/gas/riscv/mapping.s
index 3014a69e7920..4fee2b420f0c 100644
--- a/gas/testsuite/gas/riscv/mapping.s
+++ b/gas/testsuite/gas/riscv/mapping.s
@@ -119,3 +119,13 @@ addi a0, zero, 1 # $x, won't added
.align 3 # $x, won't added
addi a0, zero, 2 # $xrv32i
.option pop
+
+.section .text.dis.zfinx, "ax"
+.option push
+.option arch, rv32if
+fadd.s fa0, fa1, fa2 # $xrv32if
+.option arch, rv32i_zfinx
+fadd.s a0, a1, a2 # $xrv32i_zfinx
+.option arch, rv32if
+fadd.s fa0, fa1, fa2 # $xrv32if
+.option pop
--
2.38.1
next prev parent reply other threads:[~2022-11-28 4:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-15 4:52 [PATCH 00/11] RISC-V: Requirements for disassembler optimizations batch 1 Tsukasa OI
2022-11-15 4:52 ` [PATCH 01/11] opcodes/riscv-dis.c: More tidying Tsukasa OI
2022-11-15 4:52 ` [PATCH 02/11] RISC-V: Add test for 'Zfinx' register switching Tsukasa OI
2022-11-15 4:52 ` [PATCH 03/11] RISC-V: Make mapping symbol checking consistent Tsukasa OI
2022-11-15 4:52 ` [PATCH 04/11] RISC-V: Split riscv_get_map_state into two steps Tsukasa OI
2022-11-15 4:52 ` [PATCH 05/11] RISC-V: One time CSR hash table initialization Tsukasa OI
2022-11-15 4:52 ` [PATCH 06/11] RISC-V: Use static xlen on ADDIW sequence Tsukasa OI
2022-11-15 4:52 ` [PATCH 07/11] opcodes/riscv-dis.c: Add form feed for separation Tsukasa OI
2022-11-15 4:52 ` [PATCH 08/11] RISC-V: Split match/print steps on disassembler Tsukasa OI
2022-11-15 4:52 ` [PATCH 09/11] RISC-V: Reorganize disassembler state initialization Tsukasa OI
2022-11-15 4:52 ` [PATCH 10/11] RISC-V: Reorganize arch-related initialization and management Tsukasa OI
2022-11-15 4:52 ` [PATCH 11/11] RISC-V: Move disassembler private data initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 00/11] RISC-V: Requirements for disassembler optimizations batch 1 Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 01/11] opcodes/riscv-dis.c: More tidying Tsukasa OI
2022-11-28 4:43 ` Tsukasa OI [this message]
2022-11-28 4:43 ` [PATCH v2 03/11] RISC-V: Make mapping symbol checking consistent Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 04/11] RISC-V: Split riscv_get_map_state into two steps Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 05/11] RISC-V: One time CSR hash table initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 06/11] RISC-V: Use static xlen on ADDIW sequence Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 07/11] opcodes/riscv-dis.c: Add form feed for separation Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 08/11] RISC-V: Split match/print steps on disassembler Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 09/11] RISC-V: Reorganize disassembler state initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 10/11] RISC-V: Reorganize arch-related initialization and management Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 11/11] RISC-V: Move disassembler private data initialization Tsukasa OI
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