From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 04/11] RISC-V: Split riscv_get_map_state into two steps
Date: Tue, 15 Nov 2022 04:52:47 +0000 [thread overview]
Message-ID: <b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1668487922.git.research_trasio@irq.a4lg.com>
Because mapping symbol optimization would remove riscv_get_map_state
function, this commit splits symbol name checking step into a separate
function riscv_get_map_state_by_name.
Let alone the optimization, splitting the code improves readability.
opcodes/ChangeLog:
* riscv-dis.c (riscv_get_map_state): Split symbol name checking
into a separate function. (riscv_get_map_state_by_name): New.
---
opcodes/riscv-dis.c | 41 +++++++++++++++++++++++++++--------------
1 file changed, 27 insertions(+), 14 deletions(-)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d3bd4ceec1e..3135db30ccd 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -816,6 +816,24 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
return insnlen;
}
+/* Return new mapping state if a given symbol name is of mapping symbols',
+ MAP_NONE otherwise. If arch is not NULL and name denotes a mapping symbol
+ with ISA string, *arch is updated to the ISA string. */
+
+static enum riscv_seg_mstate
+riscv_get_map_state_by_name (const char *name, const char** arch)
+{
+ if (startswith (name, "$x"))
+ {
+ if (arch && startswith (name + 2, "rv"))
+ *arch = name + 2;
+ return MAP_INSN;
+ }
+ else if (startswith (name, "$d"))
+ return MAP_DATA;
+ return MAP_NONE;
+}
+
/* Return true if we find the suitable mapping symbol,
and also update the STATE. Otherwise, return false. */
@@ -824,28 +842,23 @@ riscv_get_map_state (int n,
enum riscv_seg_mstate *state,
struct disassemble_info *info)
{
- const char *name;
+ const char *name, *arch = NULL;
/* If the symbol is in a different section, ignore it. */
if (info->section != NULL
&& info->section != info->symtab[n]->section)
return false;
- name = bfd_asymbol_name(info->symtab[n]);
- if (startswith (name, "$x"))
+ name = bfd_asymbol_name (info->symtab[n]);
+ enum riscv_seg_mstate newstate = riscv_get_map_state_by_name (name, &arch);
+ if (newstate == MAP_NONE)
+ return false;
+ *state = newstate;
+ if (arch)
{
- if (startswith (name + 2, "rv"))
- {
- riscv_release_subset_list (&riscv_subsets);
- riscv_parse_subset (&riscv_rps_dis, name + 2);
- }
- *state = MAP_INSN;
+ riscv_release_subset_list (&riscv_subsets);
+ riscv_parse_subset (&riscv_rps_dis, arch);
}
- else if (startswith (name, "$d"))
- *state = MAP_DATA;
- else
- return false;
-
return true;
}
--
2.37.2
next prev parent reply other threads:[~2022-11-15 4:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-15 4:52 [PATCH 00/11] RISC-V: Requirements for disassembler optimizations batch 1 Tsukasa OI
2022-11-15 4:52 ` [PATCH 01/11] opcodes/riscv-dis.c: More tidying Tsukasa OI
2022-11-15 4:52 ` [PATCH 02/11] RISC-V: Add test for 'Zfinx' register switching Tsukasa OI
2022-11-15 4:52 ` [PATCH 03/11] RISC-V: Make mapping symbol checking consistent Tsukasa OI
2022-11-15 4:52 ` Tsukasa OI [this message]
2022-11-15 4:52 ` [PATCH 05/11] RISC-V: One time CSR hash table initialization Tsukasa OI
2022-11-15 4:52 ` [PATCH 06/11] RISC-V: Use static xlen on ADDIW sequence Tsukasa OI
2022-11-15 4:52 ` [PATCH 07/11] opcodes/riscv-dis.c: Add form feed for separation Tsukasa OI
2022-11-15 4:52 ` [PATCH 08/11] RISC-V: Split match/print steps on disassembler Tsukasa OI
2022-11-15 4:52 ` [PATCH 09/11] RISC-V: Reorganize disassembler state initialization Tsukasa OI
2022-11-15 4:52 ` [PATCH 10/11] RISC-V: Reorganize arch-related initialization and management Tsukasa OI
2022-11-15 4:52 ` [PATCH 11/11] RISC-V: Move disassembler private data initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 00/11] RISC-V: Requirements for disassembler optimizations batch 1 Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 01/11] opcodes/riscv-dis.c: More tidying Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 02/11] RISC-V: Add test for 'Zfinx' register switching Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 03/11] RISC-V: Make mapping symbol checking consistent Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 04/11] RISC-V: Split riscv_get_map_state into two steps Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 05/11] RISC-V: One time CSR hash table initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 06/11] RISC-V: Use static xlen on ADDIW sequence Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 07/11] opcodes/riscv-dis.c: Add form feed for separation Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 08/11] RISC-V: Split match/print steps on disassembler Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 09/11] RISC-V: Reorganize disassembler state initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 10/11] RISC-V: Reorganize arch-related initialization and management Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 11/11] RISC-V: Move disassembler private data initialization Tsukasa OI
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