From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v2 07/11] opcodes/riscv-dis.c: Add form feed for separation
Date: Mon, 28 Nov 2022 04:43:42 +0000 [thread overview]
Message-ID: <8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1669610611.git.research_trasio@irq.a4lg.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
This is a general tidying commit.
opcodes/ChangeLog:
* riscv-dis.c: Add lines with form feed to separate functional
sections.
---
opcodes/riscv-dis.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 4c193624039e..f5dc1907c6ec 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -72,7 +72,7 @@ static const char * const *riscv_fpr_names;
/* If set, disassemble as most general instruction. */
static bool no_aliases = false;
-
+\f
/* Set default RISC-V disassembler options. */
@@ -174,6 +174,7 @@ parse_riscv_dis_options (const char *opts_in)
free (opts);
}
+\f
/* Print one argument from an array. */
--
2.38.1
next prev parent reply other threads:[~2022-11-28 4:45 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-15 4:52 [PATCH 00/11] RISC-V: Requirements for disassembler optimizations batch 1 Tsukasa OI
2022-11-15 4:52 ` [PATCH 01/11] opcodes/riscv-dis.c: More tidying Tsukasa OI
2022-11-15 4:52 ` [PATCH 02/11] RISC-V: Add test for 'Zfinx' register switching Tsukasa OI
2022-11-15 4:52 ` [PATCH 03/11] RISC-V: Make mapping symbol checking consistent Tsukasa OI
2022-11-15 4:52 ` [PATCH 04/11] RISC-V: Split riscv_get_map_state into two steps Tsukasa OI
2022-11-15 4:52 ` [PATCH 05/11] RISC-V: One time CSR hash table initialization Tsukasa OI
2022-11-15 4:52 ` [PATCH 06/11] RISC-V: Use static xlen on ADDIW sequence Tsukasa OI
2022-11-15 4:52 ` [PATCH 07/11] opcodes/riscv-dis.c: Add form feed for separation Tsukasa OI
2022-11-15 4:52 ` [PATCH 08/11] RISC-V: Split match/print steps on disassembler Tsukasa OI
2022-11-15 4:52 ` [PATCH 09/11] RISC-V: Reorganize disassembler state initialization Tsukasa OI
2022-11-15 4:52 ` [PATCH 10/11] RISC-V: Reorganize arch-related initialization and management Tsukasa OI
2022-11-15 4:52 ` [PATCH 11/11] RISC-V: Move disassembler private data initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 00/11] RISC-V: Requirements for disassembler optimizations batch 1 Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 01/11] opcodes/riscv-dis.c: More tidying Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 02/11] RISC-V: Add test for 'Zfinx' register switching Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 03/11] RISC-V: Make mapping symbol checking consistent Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 04/11] RISC-V: Split riscv_get_map_state into two steps Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 05/11] RISC-V: One time CSR hash table initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 06/11] RISC-V: Use static xlen on ADDIW sequence Tsukasa OI
2022-11-28 4:43 ` Tsukasa OI [this message]
2022-11-28 4:43 ` [PATCH v2 08/11] RISC-V: Split match/print steps on disassembler Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 09/11] RISC-V: Reorganize disassembler state initialization Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 10/11] RISC-V: Reorganize arch-related initialization and management Tsukasa OI
2022-11-28 4:43 ` [PATCH v2 11/11] RISC-V: Move disassembler private data initialization Tsukasa OI
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