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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	Nelson Chu <nelson@rivosinc.com>,
	Kito Cheng <kito.cheng@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 3/5] opcodes/riscv-dis.c: Use bool type whenever possible
Date: Sat,  8 Oct 2022 04:34:25 +0000	[thread overview]
Message-ID: <740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1665203660.git.research_trasio@irq.a4lg.com>

Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.

This commit replaces uses of int with bool whenever possible.

opcodes/ChangeLog:

	* riscv-dis.c (no_aliases) Change type to bool.
	(set_default_riscv_dis_options): Use boolean.
	(parse_riscv_dis_option_without_args): Likewise.
	(riscv_disassemble_insn): Use boolean keywords.
---
 opcodes/riscv-dis.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 088d0d91080..608670bed7f 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -71,7 +71,7 @@ static const char * const *riscv_gpr_names;
 static const char * const *riscv_fpr_names;
 
 /* If set, disassemble as most general instruction.  */
-static int no_aliases;
+static bool no_aliases = false;
 
 
 /* Set default RISC-V disassembler options.  */
@@ -81,7 +81,7 @@ set_default_riscv_dis_options (void)
 {
   riscv_gpr_names = riscv_gpr_names_abi;
   riscv_fpr_names = riscv_fpr_names_abi;
-  no_aliases = 0;
+  no_aliases = false;
 }
 
 /* Parse RISC-V disassembler option (without arguments).  */
@@ -90,7 +90,7 @@ static bool
 parse_riscv_dis_option_without_args (const char *option)
 {
   if (strcmp (option, "no-aliases") == 0)
-    no_aliases = 1;
+    no_aliases = true;
   else if (strcmp (option, "numeric") == 0)
     {
       riscv_gpr_names = riscv_gpr_names_numeric;
@@ -645,7 +645,7 @@ static int
 riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 {
   const struct riscv_opcode *op;
-  static bool init = 0;
+  static bool init = false;
   static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
   struct riscv_private_data *pd;
   int insnlen;
@@ -659,7 +659,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	if (!riscv_hash[OP_HASH_IDX (op->match)])
 	  riscv_hash[OP_HASH_IDX (op->match)] = op;
 
-      init = 1;
+      init = true;
     }
 
   if (info->private_data == NULL)
-- 
2.34.1


  parent reply	other threads:[~2022-10-08  4:35 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-08  4:34 [PATCH 0/5] RISC-V: Requirements for disassembler optimizations 1 (Tidying part) Tsukasa OI
2022-10-08  4:34 ` [PATCH 1/5] opcodes/riscv-dis.c: Tidying with comments/clarity Tsukasa OI
2022-10-08  4:34 ` [PATCH 2/5] opcodes/riscv-dis.c: Tidying with spacing Tsukasa OI
2022-10-08  4:34 ` Tsukasa OI [this message]
2022-10-08  4:34 ` [PATCH 4/5] opcodes/riscv-dis.c: Make XLEN variable static Tsukasa OI
2022-10-08  4:34 ` [PATCH 5/5] opcodes/riscv-dis.c: Remove last_map_state Tsukasa OI
2022-10-14  3:47 ` [PATCH 0/5] RISC-V: Requirements for disassembler optimizations 1 (Tidying part) Nelson Chu

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