[PATCH 0/5] RISC-V: Requirements for disassembler optimizations 1 (Tidying part)

[Tsukasa OI <research_trasio@irq.a4lg.com>]

Hello,

To improve the core disassembler (both for performance and feature), this
patchset now prepares for it.

This is the part 1 of (planned) 4 part patchsets.

1.  Tidying (you are here)
2.  Reorganization of the disassembler architecture
    (including some small optimizations)
3.  Optimization 1
4.  Optimization 2

Project:
<https://github.com/a4lg/binutils-gdb/wiki/proj_dis_perf_improvements_1>

Batch 1, Part 1 is the only hardly-functional part of the whole patchsets
and considered non-debatable.

-   Adds/fixes some comments
-   Fixes some formatting / typing
-   Removes/makes static some local variables

Again, this is mostly a tidying patchset.

Thanks,
Tsukasa




Tsukasa OI (5):
  opcodes/riscv-dis.c: Tidying with comments/clarity
  opcodes/riscv-dis.c: Tidying with spacing
  opcodes/riscv-dis.c: Use bool type whenever possible
  opcodes/riscv-dis.c: Make XLEN variable static
  opcodes/riscv-dis.c: Remove last_map_state

 opcodes/riscv-dis.c | 40 +++++++++++++++++++++++++++-------------
 1 file changed, 27 insertions(+), 13 deletions(-)


base-commit: 4cbfd0daabd68516651ee37a19d0e24ca4789ea3
-- 
2.34.1