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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	Nelson Chu <nelson@rivosinc.com>,
	Kito Cheng <kito.cheng@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 2/5] opcodes/riscv-dis.c: Tidying with spacing
Date: Sat,  8 Oct 2022 04:34:24 +0000	[thread overview]
Message-ID: <1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1665203660.git.research_trasio@irq.a4lg.com>

Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.

This commit takes care of improper spacing for code clarity.

opcodes/ChangeLog:

	* riscv-dis.c (riscv_disassemble_insn): Tidying with spacing.
---
 opcodes/riscv-dis.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 2d1faf26eb3..088d0d91080 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -715,7 +715,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	}
 
       /* If arch has the Zfinx extension, replace FPR with GPR.  */
-      if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
+      if (riscv_subset_supports (&riscv_rps_dis, "zfinx"))
 	riscv_fpr_names = riscv_gpr_names;
 
       for (; op->name; op++)
-- 
2.34.1


  parent reply	other threads:[~2022-10-08  4:34 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-08  4:34 [PATCH 0/5] RISC-V: Requirements for disassembler optimizations 1 (Tidying part) Tsukasa OI
2022-10-08  4:34 ` [PATCH 1/5] opcodes/riscv-dis.c: Tidying with comments/clarity Tsukasa OI
2022-10-08  4:34 ` Tsukasa OI [this message]
2022-10-08  4:34 ` [PATCH 3/5] opcodes/riscv-dis.c: Use bool type whenever possible Tsukasa OI
2022-10-08  4:34 ` [PATCH 4/5] opcodes/riscv-dis.c: Make XLEN variable static Tsukasa OI
2022-10-08  4:34 ` [PATCH 5/5] opcodes/riscv-dis.c: Remove last_map_state Tsukasa OI
2022-10-14  3:47 ` [PATCH 0/5] RISC-V: Requirements for disassembler optimizations 1 (Tidying part) Nelson Chu

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