[PATCH v2 0/2] gas: diagnostic improvements for macros

[PATCH v2 0/2] gas: diagnostic improvements for macros

[Jan Beulich]

Since there were no comments / objections to v1, all v2 now does is cover
the remaining Arm testsuite failures (plus, of course, some re-basing, in
particular over additions to RISC-V testcase touched here as well). I
intend to commit this after another full run of testing, just in case some
new uses of .macro have appeared recently, but which I didn't notice going
in.

1: Arm: avoid unhelpful uses of .macro in testsuite
2: gas: re-work line number tracking for macros and their expansions

Jan

[PATCH v2 1/2] Arm: avoid unhelpful uses of .macro in testsuite

[Jan Beulich]

Macros with just a single use site are a little pointless to have, and
even in further cases .irp is more suitable for the purpose. Expand such
inline, avoiding the need to touch the testcases when diagnostics are
changed for code resulting from macro expansion.

While there also make what was "iter_mla" in sp-usage-thumb2-relax cover
smlatt as well, rather than testing smlabt twice.
---
v2: Convert many more testcases.

--- a/gas/testsuite/gas/arm/mve-tailpredloop-bad.l
+++ b/gas/testsuite/gas/arm/mve-tailpredloop-bad.l
@@ -1,26 +1,26 @@
 [^:]*: Assembler messages:
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Error: r15 not allowed here -- `wlstp.8 lr,pc,.label'
-[^:]*:29: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:30: Error: r15 not allowed here -- `dlstp.16 lr,pc'
-[^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:33: Error: ARM register expected -- `letp .label_back'
-[^:]*:34: Error: branch out of range or not a multiple of 2
-[^:]*:35: Error: branch out of range or not a multiple of 2
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Error: r15 not allowed here -- `wlstp.8 lr,pc,.label'
+[^:]*:21: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:22: Error: r15 not allowed here -- `dlstp.16 lr,pc'
+[^:]*:23: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:25: Error: ARM register expected -- `letp .label_back'
+[^:]*:26: Error: branch out of range or not a multiple of 2
+[^:]*:27: Error: branch out of range or not a multiple of 2
--- a/gas/testsuite/gas/arm/mve-tailpredloop-bad.s
+++ b/gas/testsuite/gas/arm/mve-tailpredloop-bad.s
@@ -1,30 +1,22 @@
-.macro cond1
+.label_back:
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
 wlstp.8 lr, r0, .label
 .endr
-.endm
 
-.macro cond2
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
 dlstp.8 lr, r0
 .endr
-.endm
 
-.macro cond3
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
 letp lr, .label_back
 .endr
-.endm
 
-.label_back:
-.syntax unified
-.thumb
-cond1
-cond2
-cond3
 wlstp.8 lr, pc, .label
 wlstp.8 lr, sp, .label
 dlstp.16 lr, pc
--- a/gas/testsuite/gas/arm/mve-vabav-bad.l
+++ b/gas/testsuite/gas/arm/mve-vabav-bad.l
@@ -1,18 +1,18 @@
 [^:]*: Assembler messages:
-[^:]*:13: Error: bad type in SIMD instruction -- `vabav.s64 r0,q0,q1'
-[^:]*:14: Error: bad type in SIMD instruction -- `vabav.f16 r0,q0,q1'
-[^:]*:15: Error: bad type in SIMD instruction -- `vabav.f32 r0,q0,q1'
-[^:]*:16: Error: bad type in SIMD instruction -- `vabav.p8 r0,q0,q1'
-[^:]*:17: Error: bad type in SIMD instruction -- `vabav.p16 r0,q0,q1'
-[^:]*:18: Error: r13 not allowed here -- `vabav.s32 r13,q0,q1'
-[^:]*:19: Error: r15 not allowed here -- `vabav.s32 r15,q0,q1'
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Error: syntax error -- `vabaveq.s32 r0,q0,q1'
-[^:]*:23: Error: syntax error -- `vabaveq.s32 r0,q0,q1'
-[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vabavt.s32 r0,q0,q1'
-[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vabavt.s32 r0,q0,q1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vabav.s64 r0,q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vabav.f16 r0,q0,q1'
+[^:]*:6: Error: bad type in SIMD instruction -- `vabav.f32 r0,q0,q1'
+[^:]*:7: Error: bad type in SIMD instruction -- `vabav.p8 r0,q0,q1'
+[^:]*:8: Error: bad type in SIMD instruction -- `vabav.p16 r0,q0,q1'
+[^:]*:9: Error: r13 not allowed here -- `vabav.s32 r13,q0,q1'
+[^:]*:10: Error: r15 not allowed here -- `vabav.s32 r15,q0,q1'
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Error: syntax error -- `vabaveq.s32 r0,q0,q1'
+[^:]*:19: Error: syntax error -- `vabaveq.s32 r0,q0,q1'
+[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vabavt.s32 r0,q0,q1'
+[^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vabavt.s32 r0,q0,q1'
--- a/gas/testsuite/gas/arm/mve-vabav-bad.s
+++ b/gas/testsuite/gas/arm/mve-vabav-bad.s
@@ -1,12 +1,3 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s32 r0, q0, q1
-.endr
-.endm
-
-
-
 .syntax unified
 .text
 .thumb
@@ -17,7 +8,12 @@ vabav.p8 r0, q0, q1
 vabav.p16 r0, q0, q1
 vabav.s32 r13, q0, q1
 vabav.s32 r15, q0, q1
-cond vabav
+
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vabav.s32 r0, q0, q1
+.endr
+
 vpst
 vabaveq.s32 r0, q0, q1
 vabaveq.s32 r0, q0, q1
--- a/gas/testsuite/gas/arm/mve-vadc-bad.l
+++ b/gas/testsuite/gas/arm/mve-vadc-bad.l
@@ -1,16 +1,16 @@
 [^:]*: Assembler messages:
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:13: Error: bad type in SIMD instruction -- `vadc.i8 q0,q1,q2'
 [^:]*:14: Error: bad type in SIMD instruction -- `vadc.i16 q0,q1,q2'
 [^:]*:15: Error: bad type in SIMD instruction -- `vadc.i64 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vadc-bad.s
+++ b/gas/testsuite/gas/arm/mve-vadc-bad.s
@@ -1,15 +1,15 @@
-.macro cond
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
 .irp mnem, vadc.i32, vadci.i32
+
 it \cond
 \mnem q0, q1, q2
+
 .endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond
 vadc.i8 q0, q1, q2
 vadc.i16 q0, q1, q2
 vadc.i64 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vaddlv-bad.l
+++ b/gas/testsuite/gas/arm/mve-vaddlv-bad.l
@@ -1,16 +1,16 @@
 [^:]*: Assembler messages:
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:13: Error: bad type in SIMD instruction -- `vaddlv.i32 r0,r1,q0'
 [^:]*:14: Error: bad type in SIMD instruction -- `vaddlv.f32 r0,r1,q0'
 [^:]*:15: Error: bad type in SIMD instruction -- `vaddlv.s8 r0,r1,q0'
--- a/gas/testsuite/gas/arm/mve-vaddlv-bad.s
+++ b/gas/testsuite/gas/arm/mve-vaddlv-bad.s
@@ -1,15 +1,15 @@
-.macro cond
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
 .irp mnem, vaddlv.s32, vaddlva.u32
+
 it \cond
 \mnem r0, r1, q0
+
 .endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond
 vaddlv.i32 r0, r1, q0
 vaddlv.f32 r0, r1, q0
 vaddlv.s8 r0, r1, q0
--- a/gas/testsuite/gas/arm/mve-vaddv-bad.l
+++ b/gas/testsuite/gas/arm/mve-vaddv-bad.l
@@ -1,16 +1,16 @@
 [^:]*: Assembler messages:
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:13: Error: bad type in SIMD instruction -- `vaddv.i32 r0,q0'
 [^:]*:14: Error: bad type in SIMD instruction -- `vaddv.f32 r0,q0'
 [^:]*:15: Error: bad type in SIMD instruction -- `vaddv.s64 r0,q0'
--- a/gas/testsuite/gas/arm/mve-vaddv-bad.s
+++ b/gas/testsuite/gas/arm/mve-vaddv-bad.s
@@ -1,15 +1,15 @@
-.macro cond
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
 .irp mnem, vaddv.s32, vaddva.u32
+
 it \cond
 \mnem r0, q0
+
 .endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond
 vaddv.i32 r0, q0
 vaddv.f32 r0, q0
 vaddv.s64 r0, q0
--- a/gas/testsuite/gas/arm/mve-vand-bad.l
+++ b/gas/testsuite/gas/arm/mve-vand-bad.l
@@ -1,27 +1,27 @@
 [^:]*: Assembler messages:
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Error: syntax error -- `vandeq q0,q1,q2'
-[^:]*:20: Error: syntax error -- `vandeq q0,q1,q2'
-[^:]*:22: Error: syntax error -- `vandeq q0,q1,q2'
-[^:]*:24: Error: instruction missing MVE vector predication code -- `vand q0,q1,q2'
-[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vandt q0,q1,q2'
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Error: syntax error -- `vandeq.i16 q0,#255'
-[^:]*:29: Error: syntax error -- `vandeq.i16 q0,#255'
-[^:]*:31: Error: syntax error -- `vandeq.i16 q0,#255'
-[^:]*:33: Error: instruction missing MVE vector predication code -- `vand.i16 q0,#255'
-[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vandt.i16 q0,#255'
-[^:]*:35: Error: bad type in SIMD instruction -- `vand.i8 q0,#255'
-[^:]*:36: Error: bad type in SIMD instruction -- `vand.i64 q0,#255'
-[^:]*:37: Error: immediate value out of range -- `vand.i16 q0,#0'
-[^:]*:38: Error: immediate value out of range -- `vand.i32 q0,#0'
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Error: syntax error -- `vandeq q0,q1,q2'
+[^:]*:11: Error: syntax error -- `vandeq q0,q1,q2'
+[^:]*:13: Error: syntax error -- `vandeq q0,q1,q2'
+[^:]*:15: Error: instruction missing MVE vector predication code -- `vand q0,q1,q2'
+[^:]*:16: Error: vector predicated instruction should be in VPT/VPST block -- `vandt q0,q1,q2'
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Error: syntax error -- `vandeq.i16 q0,#255'
+[^:]*:25: Error: syntax error -- `vandeq.i16 q0,#255'
+[^:]*:27: Error: syntax error -- `vandeq.i16 q0,#255'
+[^:]*:29: Error: instruction missing MVE vector predication code -- `vand.i16 q0,#255'
+[^:]*:30: Error: vector predicated instruction should be in VPT/VPST block -- `vandt.i16 q0,#255'
+[^:]*:31: Error: bad type in SIMD instruction -- `vand.i8 q0,#255'
+[^:]*:32: Error: bad type in SIMD instruction -- `vand.i64 q0,#255'
+[^:]*:33: Error: immediate value out of range -- `vand.i16 q0,#0'
+[^:]*:34: Error: immediate value out of range -- `vand.i32 q0,#0'
--- a/gas/testsuite/gas/arm/mve-vand-bad.s
+++ b/gas/testsuite/gas/arm/mve-vand-bad.s
@@ -1,20 +1,11 @@
-.macro cond1
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vand q0, q1, q2
-.endr
-.endm
+.syntax unified
+.thumb
 
-.macro cond2
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
-vand.i16 q0, #255
+vand q0, q1, q2
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond1
 it eq
 vandeq q0, q1, q2
 vandeq q0, q1, q2
@@ -23,7 +14,12 @@ vandeq q0, q1, q2
 vpst
 vand q0, q1, q2
 vandt q0, q1, q2
-cond2
+
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vand.i16 q0, #255
+.endr
+
 it eq
 vandeq.i16 q0, #255
 vandeq.i16 q0, #255
--- a/gas/testsuite/gas/arm/mve-vbic-bad.l
+++ b/gas/testsuite/gas/arm/mve-vbic-bad.l
@@ -1,28 +1,28 @@
 [^:]*: Assembler messages:
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Error: syntax error -- `vbiceq q0,q1,q2'
-[^:]*:20: Error: syntax error -- `vbiceq q0,q1,q2'
-[^:]*:22: Error: syntax error -- `vbiceq q0,q1,q2'
-[^:]*:24: Error: instruction missing MVE vector predication code -- `vbic q0,q1,q2'
-[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vbict q0,q1,q2'
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Error: syntax error -- `vbiceq.i16 q0,#255'
-[^:]*:29: Error: syntax error -- `vbiceq.i16 q0,#255'
-[^:]*:31: Error: syntax error -- `vbiceq.i16 q0,#255'
-[^:]*:33: Error: instruction missing MVE vector predication code -- `vbic.i16 q0,#255'
-[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vbict.i16 q0,#255'
-[^:]*:35: Error: bad type in SIMD instruction -- `vbic.i8 q0,#255'
-[^:]*:36: Error: bad type in SIMD instruction -- `vbic.i64 q0,#255'
-[^:]*:37: Error: immediate value out of range -- `vbic.i16 q0,#257'
-[^:]*:38: Error: immediate value out of range -- `vbic.i32 q0,#257'
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Error: syntax error -- `vbiceq q0,q1,q2'
+[^:]*:11: Error: syntax error -- `vbiceq q0,q1,q2'
+[^:]*:13: Error: syntax error -- `vbiceq q0,q1,q2'
+[^:]*:15: Error: instruction missing MVE vector predication code -- `vbic q0,q1,q2'
+[^:]*:16: Error: vector predicated instruction should be in VPT/VPST block -- `vbict q0,q1,q2'
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Error: syntax error -- `vbiceq.i16 q0,#255'
+[^:]*:25: Error: syntax error -- `vbiceq.i16 q0,#255'
+[^:]*:27: Error: syntax error -- `vbiceq.i16 q0,#255'
+[^:]*:29: Error: instruction missing MVE vector predication code -- `vbic.i16 q0,#255'
+[^:]*:30: Error: vector predicated instruction should be in VPT/VPST block -- `vbict.i16 q0,#255'
+[^:]*:31: Error: bad type in SIMD instruction -- `vbic.i8 q0,#255'
+[^:]*:32: Error: bad type in SIMD instruction -- `vbic.i64 q0,#255'
+[^:]*:33: Error: immediate value out of range -- `vbic.i16 q0,#257'
+[^:]*:34: Error: immediate value out of range -- `vbic.i32 q0,#257'
 
--- a/gas/testsuite/gas/arm/mve-vbic-bad.s
+++ b/gas/testsuite/gas/arm/mve-vbic-bad.s
@@ -1,20 +1,11 @@
-.macro cond1
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vbic q0, q1, q2
-.endr
-.endm
+.syntax unified
+.thumb
 
-.macro cond2
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
-vbic.i16 q0, #255
+vbic q0, q1, q2
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond1
 it eq
 vbiceq q0, q1, q2
 vbiceq q0, q1, q2
@@ -23,7 +14,12 @@ vbiceq q0, q1, q2
 vpst
 vbic q0, q1, q2
 vbict q0, q1, q2
-cond2
+
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vbic.i16 q0, #255
+.endr
+
 it eq
 vbiceq.i16 q0, #255
 vbiceq.i16 q0, #255
--- a/gas/testsuite/gas/arm/mve-vbrsr-bad.l
+++ b/gas/testsuite/gas/arm/mve-vbrsr-bad.l
@@ -1,10 +1,10 @@
 [^:]*: Assembler messages:
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:11: Error: bad type in SIMD instruction -- `vbrsr.64 q0,q1,r2'
 [^:]*:12: Error: ARM register expected -- `vbrsr.32 q0,q1,q2'
 [^:]*:14: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
--- a/gas/testsuite/gas/arm/mve-vbrsr-bad.s
+++ b/gas/testsuite/gas/arm/mve-vbrsr-bad.s
@@ -1,13 +1,13 @@
-.macro cond
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 vbrsr.16 q0, q1, r2
+
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond
 vbrsr.64 q0, q1, r2
 vbrsr.32 q0, q1, q2
 it eq
--- a/gas/testsuite/gas/arm/mve-vcadd-bad-1.l
+++ b/gas/testsuite/gas/arm/mve-vcadd-bad-1.l
@@ -1,15 +1,15 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: selected FPU does not support instruction -- `vcadd.f16 q0,q1,q2,#90'
-[^:]*:11: Error: bad type in SIMD instruction -- `vcadd.64 q0,q1,q2,#90'
-[^:]*:12: Error: immediate out of range -- `vcadd.i32 q0,q1,q2,#180'
-[^:]*:13: Error: immediate out of range -- `vcadd.i32 q0,q1,q2,#0'
-[^:]*:14: Warning: 32-bit element size and same first and third operand makes instruction UNPREDICTABLE
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: selected FPU does not support instruction -- `vcadd.f16 q0,q1,q2,#90'
+[^:]*:4: Error: bad type in SIMD instruction -- `vcadd.64 q0,q1,q2,#90'
+[^:]*:5: Error: immediate out of range -- `vcadd.i32 q0,q1,q2,#180'
+[^:]*:6: Error: immediate out of range -- `vcadd.i32 q0,q1,q2,#0'
+[^:]*:7: Warning: 32-bit element size and same first and third operand makes instruction UNPREDICTABLE
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90'
 [^:]*:18: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90'
 [^:]*:20: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90'
--- a/gas/testsuite/gas/arm/mve-vcadd-bad-1.s
+++ b/gas/testsuite/gas/arm/mve-vcadd-bad-1.s
@@ -1,10 +1,3 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vcadd.i16 q0, q1, q2, #90
-.endr
-.endm
-
 .syntax unified
 .thumb
 vcadd.f16 q0, q1, q2, #90
@@ -12,7 +5,14 @@ vcadd.64 q0, q1, q2, #90
 vcadd.i32 q0, q1, q2, #180
 vcadd.i32 q0, q1, q2, #0
 vcadd.i32 q0, q1, q0, #90
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vcadd.i16 q0, q1, q2, #90
+
+.endr
+
 it eq
 vcaddeq.i16 q0, q1, q2, #90
 vcaddeq.i16 q0, q1, q2, #90
--- a/gas/testsuite/gas/arm/mve-vcadd-bad-2.l
+++ b/gas/testsuite/gas/arm/mve-vcadd-bad-2.l
@@ -1,14 +1,14 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vcadd.f64 q0,q1,q2,#90'
-[^:]*:11: Error: immediate out of range -- `vcadd.f32 q0,q1,q2,#180'
-[^:]*:12: Error: immediate out of range -- `vcadd.f32 q0,q1,q2,#0'
-[^:]*:13: Warning: 32-bit element size and same first and third operand makes instruction UNPREDICTABLE
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vcadd.f64 q0,q1,q2,#90'
+[^:]*:4: Error: immediate out of range -- `vcadd.f32 q0,q1,q2,#180'
+[^:]*:5: Error: immediate out of range -- `vcadd.f32 q0,q1,q2,#0'
+[^:]*:6: Warning: 32-bit element size and same first and third operand makes instruction UNPREDICTABLE
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:16: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90'
 [^:]*:17: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90'
 [^:]*:19: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90'
--- a/gas/testsuite/gas/arm/mve-vcadd-bad-2.s
+++ b/gas/testsuite/gas/arm/mve-vcadd-bad-2.s
@@ -1,17 +1,17 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vcadd.f32 q0, q1, q2, #90
-.endr
-.endm
-
 .syntax unified
 .thumb
 vcadd.f64 q0, q1, q2, #90
 vcadd.f32 q0, q1, q2, #180
 vcadd.f32 q0, q1, q2, #0
 vcadd.f32 q0, q1, q0, #90
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vcadd.f32 q0, q1, q2, #90
+
+.endr
+
 it eq
 vcaddeq.f16 q0, q1, q2, #90
 vcaddeq.f16 q0, q1, q2, #90
--- a/gas/testsuite/gas/arm/mve-vcls-bad.l
+++ b/gas/testsuite/gas/arm/mve-vcls-bad.l
@@ -1,15 +1,15 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vcls.f32 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vcls.u32 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vcls.32 q0,q1'
-[^:]*:13: Error: bad type in SIMD instruction -- `vcls.i32 q0,q1'
-[^:]*:14: Error: bad type in SIMD instruction -- `vcls.s64 q0,q1'
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vcls.f32 q0,q1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vcls.u32 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vcls.32 q0,q1'
+[^:]*:6: Error: bad type in SIMD instruction -- `vcls.i32 q0,q1'
+[^:]*:7: Error: bad type in SIMD instruction -- `vcls.s64 q0,q1'
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vclseq.s16 q0,q1'
 [^:]*:18: Error: syntax error -- `vclseq.s16 q0,q1'
 [^:]*:20: Error: syntax error -- `vclseq.s16 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vcls-bad.s
+++ b/gas/testsuite/gas/arm/mve-vcls-bad.s
@@ -1,10 +1,3 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vcls.s32 q0, q1
-.endr
-.endm
-
 .syntax unified
 .thumb
 vcls.f32 q0, q1
@@ -12,7 +5,14 @@ vcls.u32 q0, q1
 vcls.32 q0, q1
 vcls.i32 q0, q1
 vcls.s64 q0, q1
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vcls.s32 q0, q1
+
+.endr
+
 it eq
 vclseq.s16 q0, q1
 vclseq.s16 q0, q1
--- a/gas/testsuite/gas/arm/mve-vclz-bad.l
+++ b/gas/testsuite/gas/arm/mve-vclz-bad.l
@@ -1,12 +1,12 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vclz.f32 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vclz.i64 q0,q1'
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vclz.f32 q0,q1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vclz.i64 q0,q1'
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:14: Error: syntax error -- `vclzeq.i16 q0,q1'
 [^:]*:15: Error: syntax error -- `vclzeq.i16 q0,q1'
 [^:]*:17: Error: syntax error -- `vclzeq.i16 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vclz-bad.s
+++ b/gas/testsuite/gas/arm/mve-vclz-bad.s
@@ -1,15 +1,15 @@
-.macro cond
+.syntax unified
+.thumb
+vclz.f32 q0, q1
+vclz.i64 q0, q1
+
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 vclz.i32 q0, q1
+
 .endr
-.endm
 
-.syntax unified
-.thumb
-vclz.f32 q0, q1
-vclz.i64 q0, q1
-cond
 it eq
 vclzeq.i16 q0, q1
 vclzeq.i16 q0, q1
--- a/gas/testsuite/gas/arm/mve-vcmla-bad-2.l
+++ b/gas/testsuite/gas/arm/mve-vcmla-bad-2.l
@@ -1,15 +1,15 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: immediate out of range -- `vcmla.f16 q0,q1,q2,#20'
-[^:]*:11: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:13: Error: bad type in SIMD instruction -- `vcmla.f64 q0,q1,q2,#0'
-[^:]*:14: Error: bad type in SIMD instruction -- `vcmla.i16 q0,q1,q2,#0'
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: immediate out of range -- `vcmla.f16 q0,q1,q2,#20'
+[^:]*:4: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:5: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:6: Error: bad type in SIMD instruction -- `vcmla.f64 q0,q1,q2,#0'
+[^:]*:7: Error: bad type in SIMD instruction -- `vcmla.i16 q0,q1,q2,#0'
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
 [^:]*:18: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
 [^:]*:20: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
--- a/gas/testsuite/gas/arm/mve-vcmla-bad-2.s
+++ b/gas/testsuite/gas/arm/mve-vcmla-bad-2.s
@@ -1,10 +1,3 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vcmla.f32 q0, q1, q2, #0
-.endr
-.endm
-
 .syntax unified
 .thumb
 vcmla.f16 q0, q1, q2, #20
@@ -12,7 +5,14 @@ vcmla.f32 q0, q0, q1, #0
 vcmla.f32 q0, q1, q0, #0
 vcmla.f64 q0, q1, q2, #0
 vcmla.i16 q0, q1, q2, #0
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vcmla.f32 q0, q1, q2, #0
+
+.endr
+
 it eq
 vcmlaeq.f16 q0, q1, q2, #0
 vcmlaeq.f16 q0, q1, q2, #0
--- a/gas/testsuite/gas/arm/mve-vcmp-bad-1.l
+++ b/gas/testsuite/gas/arm/mve-vcmp-bad-1.l
@@ -1,31 +1,31 @@
 [^:]*: Assembler messages:
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Error: selected FPU does not support instruction -- `vcmp.f32 eq,q0,q1'
-[^:]*:25: Error: selected FPU does not support instruction -- `vcmp.f32 eq,q0,r1'
-[^:]*:26: Error: bad type in SIMD instruction -- `vcmp.i64 eq,q0,q1'
-[^:]*:27: Error: invalid condition -- `vcmp.s32 eq,q0,q1'
-[^:]*:28: Error: invalid condition -- `vcmp.s16 cs,q0,q1'
-[^:]*:29: Error: invalid condition -- `vcmp.u8 le,q0,q1'
-[^:]*:30: Error: condition required -- `vcmp.s16 q0,q1'
-[^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:33: Error: syntax error -- `vcmpeq.i32 eq,q0,q1'
-[^:]*:34: Error: syntax error -- `vcmpeq.i32 eq,q0,q1'
-[^:]*:36: Error: syntax error -- `vcmpeq.i32 eq,q0,q1'
-[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vcmpt.i32 eq,q0,q1'
-[^:]*:39: Error: instruction missing MVE vector predication code -- `vcmp.i32 eq,q0,q1'
-[^:]*:41: Error: syntax error -- `vcmpeq.i32 eq,q0,r1'
-[^:]*:42: Error: syntax error -- `vcmpeq.i32 eq,q0,r1'
-[^:]*:44: Error: syntax error -- `vcmpeq.i32 eq,q0,r1'
-[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vcmpt.i32 eq,q0,r1'
-[^:]*:47: Error: instruction missing MVE vector predication code -- `vcmp.i32 eq,q0,r1'
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Error: selected FPU does not support instruction -- `vcmp.f32 eq,q0,q1'
+[^:]*:19: Error: selected FPU does not support instruction -- `vcmp.f32 eq,q0,r1'
+[^:]*:20: Error: bad type in SIMD instruction -- `vcmp.i64 eq,q0,q1'
+[^:]*:21: Error: invalid condition -- `vcmp.s32 eq,q0,q1'
+[^:]*:22: Error: invalid condition -- `vcmp.s16 cs,q0,q1'
+[^:]*:23: Error: invalid condition -- `vcmp.u8 le,q0,q1'
+[^:]*:24: Error: condition required -- `vcmp.s16 q0,q1'
+[^:]*:25: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:27: Error: syntax error -- `vcmpeq.i32 eq,q0,q1'
+[^:]*:28: Error: syntax error -- `vcmpeq.i32 eq,q0,q1'
+[^:]*:30: Error: syntax error -- `vcmpeq.i32 eq,q0,q1'
+[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vcmpt.i32 eq,q0,q1'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vcmp.i32 eq,q0,q1'
+[^:]*:35: Error: syntax error -- `vcmpeq.i32 eq,q0,r1'
+[^:]*:36: Error: syntax error -- `vcmpeq.i32 eq,q0,r1'
+[^:]*:38: Error: syntax error -- `vcmpeq.i32 eq,q0,r1'
+[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vcmpt.i32 eq,q0,r1'
+[^:]*:41: Error: instruction missing MVE vector predication code -- `vcmp.i32 eq,q0,r1'
--- a/gas/testsuite/gas/arm/mve-vcmp-bad-1.s
+++ b/gas/testsuite/gas/arm/mve-vcmp-bad-1.s
@@ -1,26 +1,20 @@
-.macro cond1
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
 .irp size, .
 it \cond
 vcmp.s32 gt, q0, q1
 .endr
 .endr
-.endm
 
-.macro cond2
 .irp cond, eq, ne, gt, ge, lt, le
 .irp size, .
 it \cond
 vcmp.i16 eq, q0, r1
 .endr
 .endr
-.endm
-
-.syntax unified
-.thumb
 
-cond1
-cond2
 vcmp.f32 eq, q0, q1
 vcmp.f32 eq, q0, r1
 vcmp.i64 eq, q0, q1
--- a/gas/testsuite/gas/arm/mve-vcmp-bad-2.l
+++ b/gas/testsuite/gas/arm/mve-vcmp-bad-2.l
@@ -1,25 +1,25 @@
 [^:]*: Assembler messages:
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Error: bad type in SIMD instruction -- `vcmp.f64 eq,q0,q1'
-[^:]*:25: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:27: Error: syntax error -- `vcmpeq.f32 eq,q0,q1'
-[^:]*:28: Error: syntax error -- `vcmpeq.f32 eq,q0,q1'
-[^:]*:30: Error: syntax error -- `vcmpeq.f32 eq,q0,q1'
-[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vcmpt.f32 eq,q0,q1'
-[^:]*:33: Error: instruction missing MVE vector predication code -- `vcmp.f32 eq,q0,q1'
-[^:]*:35: Error: syntax error -- `vcmpeq.f32 eq,q0,r1'
-[^:]*:36: Error: syntax error -- `vcmpeq.f32 eq,q0,r1'
-[^:]*:38: Error: syntax error -- `vcmpeq.f32 eq,q0,r1'
-[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vcmpt.f32 eq,q0,r1'
-[^:]*:41: Error: instruction missing MVE vector predication code -- `vcmp.f32 eq,q0,r1'
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Error: bad type in SIMD instruction -- `vcmp.f64 eq,q0,q1'
+[^:]*:19: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:21: Error: syntax error -- `vcmpeq.f32 eq,q0,q1'
+[^:]*:22: Error: syntax error -- `vcmpeq.f32 eq,q0,q1'
+[^:]*:24: Error: syntax error -- `vcmpeq.f32 eq,q0,q1'
+[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vcmpt.f32 eq,q0,q1'
+[^:]*:27: Error: instruction missing MVE vector predication code -- `vcmp.f32 eq,q0,q1'
+[^:]*:29: Error: syntax error -- `vcmpeq.f32 eq,q0,r1'
+[^:]*:30: Error: syntax error -- `vcmpeq.f32 eq,q0,r1'
+[^:]*:32: Error: syntax error -- `vcmpeq.f32 eq,q0,r1'
+[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vcmpt.f32 eq,q0,r1'
+[^:]*:35: Error: instruction missing MVE vector predication code -- `vcmp.f32 eq,q0,r1'
--- a/gas/testsuite/gas/arm/mve-vcmp-bad-2.s
+++ b/gas/testsuite/gas/arm/mve-vcmp-bad-2.s
@@ -1,26 +1,20 @@
-.macro cond1
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
 .irp size, .
 it \cond
 vcmp.f32 gt, q0, q1
 .endr
 .endr
-.endm
 
-.macro cond2
 .irp cond, eq, ne, gt, ge, lt, le
 .irp size, .
 it \cond
 vcmp.f16 eq, q0, r1
 .endr
 .endr
-.endm
-
-.syntax unified
-.thumb
 
-cond1
-cond2
 vcmp.f64 eq, q0, q1
 vcmp.f32 eq, q0, sp
 it eq
--- a/gas/testsuite/gas/arm/mve-vcmul-bad-2.l
+++ b/gas/testsuite/gas/arm/mve-vcmul-bad-2.l
@@ -1,15 +1,15 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vcmul.i16 q0,q1,q2,#0'
-[^:]*:11: Error: bad type in SIMD instruction -- `vcmul.f64 q0,q1,q2,#0'
-[^:]*:12: Error: immediate out of range -- `vcmul.f32 q0,q1,q2,#20'
-[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:14: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vcmul.i16 q0,q1,q2,#0'
+[^:]*:4: Error: bad type in SIMD instruction -- `vcmul.f64 q0,q1,q2,#0'
+[^:]*:5: Error: immediate out of range -- `vcmul.f32 q0,q1,q2,#20'
+[^:]*:6: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:7: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0'
 [^:]*:18: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0'
 [^:]*:20: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0'
--- a/gas/testsuite/gas/arm/mve-vcmul-bad-2.s
+++ b/gas/testsuite/gas/arm/mve-vcmul-bad-2.s
@@ -1,10 +1,3 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vcmul.f32 q0, q1, q2, #0
-.endr
-.endm
-
 .syntax unified
 .thumb
 vcmul.i16 q0, q1, q2, #0
@@ -12,7 +5,14 @@ vcmul.f64 q0, q1, q2, #0
 vcmul.f32 q0, q1, q2, #20
 vcmul.f32 q0, q1, q0, #0
 vcmul.f32 q0, q0, q1, #0
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vcmul.f32 q0, q1, q2, #0
+
+.endr
+
 it eq
 vcmuleq.f32 q0, q1, q2, #0
 vcmuleq.f32 q0, q1, q2, #0
--- a/gas/testsuite/gas/arm/mve-vcvt-bad-1.l
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-1.l
@@ -1,68 +1,68 @@
 [^:]*: Assembler messages:
-[^:]*:12: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#0'
-[^:]*:13: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#0'
-[^:]*:14: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#0'
-[^:]*:15: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#0'
-[^:]*:16: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#17'
-[^:]*:17: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#17'
-[^:]*:18: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#17'
-[^:]*:19: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#17'
-[^:]*:20: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#0'
-[^:]*:21: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#0'
-[^:]*:22: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#0'
-[^:]*:23: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#0'
-[^:]*:24: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#33'
-[^:]*:25: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#33'
-[^:]*:26: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#33'
-[^:]*:27: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#33'
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#0'
+[^:]*:4: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#0'
+[^:]*:5: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#0'
+[^:]*:6: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#0'
+[^:]*:7: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#17'
+[^:]*:8: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#17'
+[^:]*:9: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#17'
+[^:]*:10: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#17'
+[^:]*:11: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#0'
+[^:]*:12: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#0'
+[^:]*:13: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#0'
+[^:]*:14: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#0'
+[^:]*:15: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#33'
+[^:]*:16: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#33'
+[^:]*:17: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#33'
+[^:]*:18: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#33'
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:29: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1,#1'
 [^:]*:30: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1,#1'
 [^:]*:31: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1,#1'
--- a/gas/testsuite/gas/arm/mve-vcvt-bad-1.s
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-1.s
@@ -1,12 +1,3 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-.irp size, .f16.s16, .s16.f16, .f16.u16, .u16.f16, .f32.s32, .s32.f32, .f32.u32, .u32.f32
-it \cond
-vcvt\size q0, q1, #1
-.endr
-.endr
-.endm
-
 .syntax unified
 .thumb
 vcvt.f16.s16 q0, q1, #0
@@ -25,7 +16,16 @@ vcvt.f32.s32 q0, q1, #33
 vcvt.s32.f32 q0, q1, #33
 vcvt.f32.u32 q0, q1, #33
 vcvt.u32.f32 q0, q1, #33
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+.irp size, .f16.s16, .s16.f16, .f16.u16, .u16.f16, .f32.s32, .s32.f32, .f32.u32, .u32.f32
+
+it \cond
+vcvt\size q0, q1, #1
+
+.endr
+.endr
+
 vcvt.f64.u64 q0, q1, #1
 vcvt.u64.f64 q0, q1, #1
 vcvt.f64.s64 q0, q1, #1
--- a/gas/testsuite/gas/arm/mve-vcvt-bad-2.l
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-2.l
@@ -1,52 +1,52 @@
 [^:]*: Assembler messages:
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:13: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1'
 [^:]*:14: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1'
 [^:]*:15: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vcvt-bad-2.s
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-2.s
@@ -1,15 +1,15 @@
-.macro cond
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
 .irp size, .f16.s16, .s16.f16, .f16.u16, .u16.f16, .f32.s32, .s32.f32, .f32.u32, .u32.f32
+
 it \cond
 vcvt\size q0, q1
+
 .endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond
 vcvt.u64.f64 q0, q1
 vcvt.f64.u64 q0, q1
 vcvt.s64.f64 q0, q1
--- a/gas/testsuite/gas/arm/mve-vcvt-bad-3.l
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-3.l
@@ -1,28 +1,28 @@
 [^:]*: Assembler messages:
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:15: Error: bad type in SIMD instruction -- `vcvt.f64.f16 q0,q1'
 [^:]*:16: Error: bad type in SIMD instruction -- `vcvt.f64.f32 q0,q1'
 [^:]*:17: Error: bad type in SIMD instruction -- `vcvt.f16.f64 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vcvt-bad-3.s
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-3.s
@@ -1,17 +1,17 @@
-.macro cond
+.syntax unified
+.thumb
+
 .irp top, t, b
 .irp cond, eq, ne, gt, ge, lt, le
 .irp size, .f16.f32, .f32.f16
+
 it \cond
 vcvt\top\size q0, q1
+
 .endr
 .endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond
 vcvt.f64.f16 q0, q1
 vcvt.f64.f32 q0, q1
 vcvt.f16.f64 q0, q1
--- a/gas/testsuite/gas/arm/mve-vcvt-bad-4.l
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-4.l
@@ -1,100 +1,100 @@
 [^:]*: Assembler messages:
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:15: Error: bad type in SIMD instruction -- `vcvta.s64.f64 q0,q1'
 [^:]*:16: Error: bad type in SIMD instruction -- `vcvta.u64.f64 q0,q1'
 [^:]*:17: Error: bad type in SIMD instruction -- `vcvta.f64.s64 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vcvt-bad-4.s
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-4.s
@@ -1,17 +1,17 @@
-.macro cond
+.syntax unified
+.thumb
+
 .irp round, a, n, p, m
 .irp cond, eq, ne, gt, ge, lt, le
 .irp size, .s16.f16, .u16.f16, .s32.f32, .u32.f32
+
 it \cond
 vcvt\round\size q0, q1
+
 .endr
 .endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond
 vcvta.s64.f64 q0, q1
 vcvta.u64.f64 q0, q1
 vcvta.f64.s64 q0, q1
--- a/gas/testsuite/gas/arm/mve-vcvt-bad.l
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad.l
@@ -1,41 +1,41 @@
 [^:]*: Assembler messages:
-[^:]*:11: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#0'
-[^:]*:12: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#17'
-[^:]*:13: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#0'
-[^:]*:14: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#17'
-[^:]*:15: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#0'
-[^:]*:16: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#17'
-[^:]*:17: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#0'
-[^:]*:18: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#17'
-[^:]*:19: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#0'
-[^:]*:20: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#33'
-[^:]*:21: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#0'
-[^:]*:22: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#33'
-[^:]*:23: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#0'
-[^:]*:24: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#33'
-[^:]*:25: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#0'
-[^:]*:26: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#33'
-[^:]*:27: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1,#1'
-[^:]*:28: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1,#1'
-[^:]*:29: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1,#1'
-[^:]*:30: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1,#1'
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#0'
+[^:]*:5: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#17'
+[^:]*:6: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#0'
+[^:]*:7: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#17'
+[^:]*:8: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#0'
+[^:]*:9: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#17'
+[^:]*:10: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#0'
+[^:]*:11: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#17'
+[^:]*:12: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#0'
+[^:]*:13: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#33'
+[^:]*:14: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#0'
+[^:]*:15: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#33'
+[^:]*:16: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#0'
+[^:]*:17: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#33'
+[^:]*:18: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#0'
+[^:]*:19: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#33'
+[^:]*:20: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1,#1'
+[^:]*:21: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1,#1'
+[^:]*:22: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1,#1'
+[^:]*:23: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1,#1'
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:33: Error: syntax error -- `vcvteq.f16.s16 q0,q1,#1'
 [^:]*:34: Error: syntax error -- `vcvteq.f16.s16 q0,q1,#1'
 [^:]*:36: Error: syntax error -- `vcvteq.f16.s16 q0,q1,#1'
 [^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtt.f16.s16 q0,q1,#1'
 [^:]*:39: Error: instruction missing MVE vector predication code -- `vcvt.f16.s16 q0,q1,#1'
-[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:45: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:45: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:45: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:45: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:45: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:45: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:49: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1'
 [^:]*:50: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1'
 [^:]*:51: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1'
@@ -45,12 +45,12 @@
 [^:]*:57: Error: syntax error -- `vcvteq.u32.f32 q0,q1'
 [^:]*:58: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtt.u32.f32 q0,q1'
 [^:]*:60: Error: instruction missing MVE vector predication code -- `vcvt.u32.f32 q0,q1'
-[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:70: Error: bad type in SIMD instruction -- `vcvtb.f16.f64 q0,q1'
 [^:]*:71: Error: bad type in SIMD instruction -- `vcvtb.f64.f16 q0,q1'
 [^:]*:72: Error: bad type in SIMD instruction -- `vcvtb.f32.f64 q0,q1'
@@ -60,18 +60,18 @@
 [^:]*:78: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
 [^:]*:79: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtbt.f16.f32 q0,q1'
 [^:]*:81: Error: instruction missing MVE vector predication code -- `vcvtb.f16.f32 q0,q1'
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:83: Error: bad type in SIMD instruction -- `vcvtt.f16.f64 q0,q1'
-[^:]*:84: Error: bad type in SIMD instruction -- `vcvtt.f64.f16 q0,q1'
-[^:]*:85: Error: bad type in SIMD instruction -- `vcvtt.f32.f64 q0,q1'
-[^:]*:86: Error: bad type in SIMD instruction -- `vcvtt.f64.f32 q0,q1'
-[^:]*:88: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
-[^:]*:89: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
-[^:]*:91: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
-[^:]*:92: Error: vector predicated instruction should be in VPT/VPST block -- `vcvttt.f16.f32 q0,q1'
-[^:]*:94: Error: instruction missing MVE vector predication code -- `vcvtt.f16.f32 q0,q1'
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:67: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:70: Error: bad type in SIMD instruction -- `vcvtt.f16.f64 q0,q1'
+[^:]*:71: Error: bad type in SIMD instruction -- `vcvtt.f64.f16 q0,q1'
+[^:]*:72: Error: bad type in SIMD instruction -- `vcvtt.f32.f64 q0,q1'
+[^:]*:73: Error: bad type in SIMD instruction -- `vcvtt.f64.f32 q0,q1'
+[^:]*:75: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:76: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:78: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:79: Error: vector predicated instruction should be in VPT/VPST block -- `vcvttt.f16.f32 q0,q1'
+[^:]*:81: Error: instruction missing MVE vector predication code -- `vcvtt.f16.f32 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vcvt-bad.s
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad.s
@@ -1,10 +1,3 @@
-.macro cond1
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vcvt\().f16.s16 q0, q1, #1
-.endr
-.endm
-
 .syntax unified
 .thumb
 
@@ -28,7 +21,14 @@ vcvt.f64.s64 q0, q1, #1
 vcvt.f64.u64 q0, q1, #1
 vcvt.s64.f64 q0, q1, #1
 vcvt.u64.f64 q0, q1, #1
-cond1
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vcvt\().f16.s16 q0, q1, #1
+
+.endr
+
 it eq
 vcvteq.f16.s16 q0, q1, #1
 vcvteq.f16.s16 q0, q1, #1
@@ -38,14 +38,14 @@ vcvtt.f16.s16 q0, q1, #1
 vpst
 vcvt.f16.s16 q0, q1, #1
 
-.macro cond2
+
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 vcvt\().f16.s16 q0, q1
+
 .endr
-.endm
 
-cond2
 vcvt.f64.s64 q0, q1
 vcvt.f64.u64 q0, q1
 vcvt.s64.f64 q0, q1
@@ -59,36 +59,25 @@ vcvtt.u32.f32 q0, q1
 vpst
 vcvt.u32.f32 q0, q1
 
-.macro cond3 mnem
+
+.irp bt, b, t
+
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
-\mnem\().f16.f32 q0, q1
+vcvt\bt\().f16.f32 q0, q1
 .endr
-.endm
 
-cond3 vcvtb
-vcvtb.f16.f64 q0, q1
-vcvtb.f64.f16 q0, q1
-vcvtb.f32.f64 q0, q1
-vcvtb.f64.f32 q0, q1
+vcvt\bt\().f16.f64 q0, q1
+vcvt\bt\().f64.f16 q0, q1
+vcvt\bt\().f32.f64 q0, q1
+vcvt\bt\().f64.f32 q0, q1
 it eq
-vcvtbeq.f16.f32 q0, q1
-vcvtbeq.f16.f32 q0, q1
+vcvt\bt\()eq.f16.f32 q0, q1
+vcvt\bt\()eq.f16.f32 q0, q1
 vpst
-vcvtbeq.f16.f32 q0, q1
-vcvtbt.f16.f32 q0, q1
+vcvt\bt\()eq.f16.f32 q0, q1
+vcvt\bt\()t.f16.f32 q0, q1
 vpst
-vcvtb.f16.f32 q0, q1
-cond3 vcvtt
-vcvtt.f16.f64 q0, q1
-vcvtt.f64.f16 q0, q1
-vcvtt.f32.f64 q0, q1
-vcvtt.f64.f32 q0, q1
-it eq
-vcvtteq.f16.f32 q0, q1
-vcvtteq.f16.f32 q0, q1
-vpst
-vcvtteq.f16.f32 q0, q1
-vcvttt.f16.f32 q0, q1
-vpst
-vcvtt.f16.f32 q0, q1
+vcvt\bt\().f16.f32 q0, q1
+
+.endr
--- a/gas/testsuite/gas/arm/mve-vddup-bad.l
+++ b/gas/testsuite/gas/arm/mve-vddup-bad.l
@@ -1,26 +1,26 @@
 [^:]*: Assembler messages:
-[^:]*:16: Error: bad type in SIMD instruction -- `vddup.s16 q0,r0,#1'
-[^:]*:17: Error: bad type in SIMD instruction -- `vddup.u64 q0,r0,#1'
-[^:]*:18: Error: immediate must be either 1, 2, 4 or 8 -- `vddup.u32 q0,r0,#3'
-[^:]*:19: Error: immediate must be either 1, 2, 4 or 8 -- `vddup.u32 q0,r0,#0'
-[^:]*:20: Error: bad type in SIMD instruction -- `vdwdup.s16 q0,r0,r1,#1'
-[^:]*:21: Error: bad type in SIMD instruction -- `vdwdup.u64 q0,r0,r1,#1'
-[^:]*:22: Error: immediate must be either 1, 2, 4 or 8 -- `vdwdup.u32 q0,r0,r1,#3'
-[^:]*:23: Error: immediate must be either 1, 2, 4 or 8 -- `vdwdup.u32 q0,r0,r1,#0'
-[^:]*:24: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:25: Error: r15 not allowed here -- `vdwdup.u32 q0,r0,pc,#1'
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vddup.s16 q0,r0,#1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vddup.u64 q0,r0,#1'
+[^:]*:5: Error: immediate must be either 1, 2, 4 or 8 -- `vddup.u32 q0,r0,#3'
+[^:]*:6: Error: immediate must be either 1, 2, 4 or 8 -- `vddup.u32 q0,r0,#0'
+[^:]*:7: Error: bad type in SIMD instruction -- `vdwdup.s16 q0,r0,r1,#1'
+[^:]*:8: Error: bad type in SIMD instruction -- `vdwdup.u64 q0,r0,r1,#1'
+[^:]*:9: Error: immediate must be either 1, 2, 4 or 8 -- `vdwdup.u32 q0,r0,r1,#3'
+[^:]*:10: Error: immediate must be either 1, 2, 4 or 8 -- `vdwdup.u32 q0,r0,r1,#0'
+[^:]*:11: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:12: Error: r15 not allowed here -- `vdwdup.u32 q0,r0,pc,#1'
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:29: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
 [^:]*:30: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
 [^:]*:32: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
--- a/gas/testsuite/gas/arm/mve-vddup-bad.s
+++ b/gas/testsuite/gas/arm/mve-vddup-bad.s
@@ -1,16 +1,3 @@
-.macro cond1
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vddup.u32 q0, r2, #1
-.endr
-.endm
-
-.macro cond2
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vdwdup.u32 q0, r2, r1, #1
-.endr
-.endm
 .syntax unified
 .thumb
 vddup.s16 q0, r0, #1
@@ -23,8 +10,21 @@ vdwdup.u32 q0, r0, r1, #3
 vdwdup.u32 q0, r0, r1, #0
 vdwdup.u32 q0, r0, sp, #1
 vdwdup.u32 q0, r0, pc, #1
-cond1
-cond2
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vddup.u32 q0, r2, #1
+
+.endr
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vdwdup.u32 q0, r2, r1, #1
+
+.endr
+
 it eq
 vddupeq.u32 q0, r0, #1
 vddupeq.u32 q0, r0, #1
--- a/gas/testsuite/gas/arm/mve-vdup-bad.l
+++ b/gas/testsuite/gas/arm/mve-vdup-bad.l
@@ -1,14 +1,14 @@
 [^:]*: Assembler messages:
-[^:]*:11: Error: bad type in SIMD instruction -- `vdup.64 q0,r1'
-[^:]*:12: Error: selected FPU does not support instruction -- `vdup.32 q0,d0\[1\]'
-[^:]*:13: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vdup.64 q0,r1'
+[^:]*:5: Error: selected FPU does not support instruction -- `vdup.32 q0,d0\[1\]'
+[^:]*:6: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:7: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vdupeq.32 q0,r2'
 [^:]*:18: Error: syntax error -- `vdupeq.32 q0,r2'
 [^:]*:20: Error: syntax error -- `vdupeq.32 q0,r2'
--- a/gas/testsuite/gas/arm/mve-vdup-bad.s
+++ b/gas/testsuite/gas/arm/mve-vdup-bad.s
@@ -1,10 +1,3 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vdup.32 q0, r2
-.endr
-.endm
-
 .syntax unified
 .thumb
 vdup.f16 q0, r1
@@ -12,7 +5,14 @@ vdup.64 q0, r1
 vdup.32 q0, d0[1]
 vdup.32 q0, sp
 vdup.32 q0, pc
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vdup.32 q0, r2
+
+.endr
+
 it eq
 vdupeq.32 q0, r2
 vdupeq.32 q0, r2
--- a/gas/testsuite/gas/arm/mve-veor-bad.l
+++ b/gas/testsuite/gas/arm/mve-veor-bad.l
@@ -1,10 +1,10 @@
 [^:]*: Assembler messages:
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:12: Error: syntax error -- `veoreq q0,q1,q2'
 [^:]*:13: Error: syntax error -- `veoreq q0,q1,q2'
 [^:]*:15: Error: syntax error -- `veoreq q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-veor-bad.s
+++ b/gas/testsuite/gas/arm/mve-veor-bad.s
@@ -1,13 +1,13 @@
-.macro cond
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 veor q0, q1, q2
+
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond
 it eq
 veoreq q0, q1, q2
 veoreq q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vfma-vfms-bad.l
+++ b/gas/testsuite/gas/arm/mve-vfma-vfms-bad.l
@@ -1,35 +1,35 @@
 [^:]*: Assembler messages:
-[^:]*:24: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:25: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:26: Error: bad type in SIMD instruction -- `vfma.f64 q0,q1,q2'
-[^:]*:27: Error: bad type in SIMD instruction -- `vfma.32 q0,q1,q2'
-[^:]*:28: Error: bad type in SIMD instruction -- `vfms.f64 q0,q1,q2'
-[^:]*:29: Error: bad type in SIMD instruction -- `vfms.32 q0,q1,q2'
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:35: Error: syntax error -- `vfmaeq.f16 q0,q1,q2'
-[^:]*:36: Error: syntax error -- `vfmaeq.f16 q0,q1,q2'
-[^:]*:38: Error: syntax error -- `vfmaeq.f16 q0,q1,q2'
-[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vfmat.f16 q0,q1,q2'
-[^:]*:41: Error: instruction missing MVE vector predication code -- `vfma.f16 q0,q1,q2'
-[^:]*:43: Error: syntax error -- `vfmseq.f16 q0,q1,q2'
-[^:]*:44: Error: syntax error -- `vfmseq.f16 q0,q1,q2'
-[^:]*:46: Error: syntax error -- `vfmseq.f16 q0,q1,q2'
-[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vfmst.f16 q0,q1,q2'
-[^:]*:49: Error: instruction missing MVE vector predication code -- `vfms.f16 q0,q1,q2'
+[^:]*:3: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:4: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:5: Error: bad type in SIMD instruction -- `vfma.f64 q0,q1,q2'
+[^:]*:6: Error: bad type in SIMD instruction -- `vfma.32 q0,q1,q2'
+[^:]*:7: Error: bad type in SIMD instruction -- `vfms.f64 q0,q1,q2'
+[^:]*:8: Error: bad type in SIMD instruction -- `vfms.32 q0,q1,q2'
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Error: syntax error -- `vfmaeq.f16 q0,q1,q2'
+[^:]*:28: Error: syntax error -- `vfmaeq.f16 q0,q1,q2'
+[^:]*:30: Error: syntax error -- `vfmaeq.f16 q0,q1,q2'
+[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vfmat.f16 q0,q1,q2'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vfma.f16 q0,q1,q2'
+[^:]*:35: Error: syntax error -- `vfmseq.f16 q0,q1,q2'
+[^:]*:36: Error: syntax error -- `vfmseq.f16 q0,q1,q2'
+[^:]*:38: Error: syntax error -- `vfmseq.f16 q0,q1,q2'
+[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vfmst.f16 q0,q1,q2'
+[^:]*:41: Error: instruction missing MVE vector predication code -- `vfms.f16 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vfma-vfms-bad.s
+++ b/gas/testsuite/gas/arm/mve-vfma-vfms-bad.s
@@ -1,36 +1,28 @@
-.macro cond1
+.syntax unified
+.thumb
+vfma.f32 q0, q1, sp
+vfma.f32 q0, q1, pc
+vfma.f64 q0, q1, q2
+vfma.32 q0, q1, q2
+vfms.f64 q0, q1, q2
+vfms.32 q0, q1, q2
+vfma.f64 d0, d1, d2
+
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
 vfma.f32 q0, q1, q2
 .endr
-.endm
 
-.macro cond2
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
 vfma.f32 q0, q1, r2
 .endr
-.endm
 
-.macro cond3
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
 vfms.f32 q0, q1, q2
 .endr
-.endm
 
-.syntax unified
-.thumb
-vfma.f32 q0, q1, sp
-vfma.f32 q0, q1, pc
-vfma.f64 q0, q1, q2
-vfma.32 q0, q1, q2
-vfms.f64 q0, q1, q2
-vfms.32 q0, q1, q2
-vfma.f64 d0, d1, d2
-cond1
-cond2
-cond3
 it eq
 vfmaeq.f16 q0, q1, q2
 vfmaeq.f16 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vfmas-bad.l
+++ b/gas/testsuite/gas/arm/mve-vfmas-bad.l
@@ -1,14 +1,14 @@
 [^:]*: Assembler messages:
-[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:11: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:12: Error: bad type in SIMD instruction -- `vfmas.i32 q0,q1,r2'
-[^:]*:13: Error: bad type in SIMD instruction -- `vfmas.f64 q0,q1,r2'
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:4: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:5: Error: bad type in SIMD instruction -- `vfmas.i32 q0,q1,r2'
+[^:]*:6: Error: bad type in SIMD instruction -- `vfmas.f64 q0,q1,r2'
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:16: Error: syntax error -- `vfmaseq.f32 q0,q1,r2'
 [^:]*:17: Error: syntax error -- `vfmaseq.f32 q0,q1,r2'
 [^:]*:19: Error: syntax error -- `vfmaseq.f32 q0,q1,r2'
--- a/gas/testsuite/gas/arm/mve-vfmas-bad.s
+++ b/gas/testsuite/gas/arm/mve-vfmas-bad.s
@@ -1,17 +1,17 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vfmas.f32 q0, q1, r2
-.endr
-.endm
-
 .syntax unified
 .thumb
 vfmas.f32 q0, q1, sp
 vfmas.f32 q0, q1, pc
 vfmas.i32 q0, q1, r2
 vfmas.f64 q0, q1, r2
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vfmas.f32 q0, q1, r2
+
+.endr
+
 it eq
 vfmaseq.f32 q0, q1, r2
 vfmaseq.f32 q0, q1, r2
--- a/gas/testsuite/gas/arm/mve-vhcadd-bad.l
+++ b/gas/testsuite/gas/arm/mve-vhcadd-bad.l
@@ -1,15 +1,15 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vhcadd.u8 q0,q1,q2,#90'
-[^:]*:11: Error: bad type in SIMD instruction -- `vhcadd.i8 q0,q1,q2,#90'
-[^:]*:12: Error: bad type in SIMD instruction -- `vhcadd.s64 q0,q1,q2,#90'
-[^:]*:13: Error: immediate out of range -- `vhcadd.s8 q0,q1,q2,#0'
-[^:]*:14: Error: immediate out of range -- `vhcadd.s8 q0,q1,q2,#180'
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vhcadd.u8 q0,q1,q2,#90'
+[^:]*:4: Error: bad type in SIMD instruction -- `vhcadd.i8 q0,q1,q2,#90'
+[^:]*:5: Error: bad type in SIMD instruction -- `vhcadd.s64 q0,q1,q2,#90'
+[^:]*:6: Error: immediate out of range -- `vhcadd.s8 q0,q1,q2,#0'
+[^:]*:7: Error: immediate out of range -- `vhcadd.s8 q0,q1,q2,#180'
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vhcaddeq.s8 q0,q1,q2,#90'
 [^:]*:18: Error: syntax error -- `vhcaddeq.s8 q0,q1,q2,#90'
 [^:]*:20: Error: syntax error -- `vhcaddeq.s8 q0,q1,q2,#90'
--- a/gas/testsuite/gas/arm/mve-vhcadd-bad.s
+++ b/gas/testsuite/gas/arm/mve-vhcadd-bad.s
@@ -1,10 +1,3 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vhcadd.s8 q0, q1, q2, #90
-.endr
-.endm
-
 .syntax unified
 .thumb
 vhcadd.u8 q0, q1, q2, #90
@@ -12,7 +5,14 @@ vhcadd.i8 q0, q1, q2, #90
 vhcadd.s64 q0, q1, q2, #90
 vhcadd.s8 q0, q1, q2, #0
 vhcadd.s8 q0, q1, q2, #180
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vhcadd.s8 q0, q1, q2, #90
+
+.endr
+
 it eq
 vhcaddeq.s8 q0, q1, q2, #90
 vhcaddeq.s8 q0, q1, q2, #90
--- a/gas/testsuite/gas/arm/mve-vidup-bad.l
+++ b/gas/testsuite/gas/arm/mve-vidup-bad.l
@@ -1,26 +1,26 @@
 [^:]*: Assembler messages:
-[^:]*:16: Error: bad type in SIMD instruction -- `vidup.s16 q0,r0,#1'
-[^:]*:17: Error: bad type in SIMD instruction -- `vidup.u64 q0,r0,#1'
-[^:]*:18: Error: immediate must be either 1, 2, 4 or 8 -- `vidup.u32 q0,r0,#3'
-[^:]*:19: Error: immediate must be either 1, 2, 4 or 8 -- `vidup.u32 q0,r0,#0'
-[^:]*:20: Error: bad type in SIMD instruction -- `viwdup.s16 q0,r0,r1,#1'
-[^:]*:21: Error: bad type in SIMD instruction -- `viwdup.u64 q0,r0,r1,#1'
-[^:]*:22: Error: immediate must be either 1, 2, 4 or 8 -- `viwdup.u32 q0,r0,r1,#3'
-[^:]*:23: Error: immediate must be either 1, 2, 4 or 8 -- `viwdup.u32 q0,r0,r1,#0'
-[^:]*:24: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:25: Error: r15 not allowed here -- `viwdup.u32 q0,r0,pc,#1'
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vidup.s16 q0,r0,#1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vidup.u64 q0,r0,#1'
+[^:]*:5: Error: immediate must be either 1, 2, 4 or 8 -- `vidup.u32 q0,r0,#3'
+[^:]*:6: Error: immediate must be either 1, 2, 4 or 8 -- `vidup.u32 q0,r0,#0'
+[^:]*:7: Error: bad type in SIMD instruction -- `viwdup.s16 q0,r0,r1,#1'
+[^:]*:8: Error: bad type in SIMD instruction -- `viwdup.u64 q0,r0,r1,#1'
+[^:]*:9: Error: immediate must be either 1, 2, 4 or 8 -- `viwdup.u32 q0,r0,r1,#3'
+[^:]*:10: Error: immediate must be either 1, 2, 4 or 8 -- `viwdup.u32 q0,r0,r1,#0'
+[^:]*:11: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:12: Error: r15 not allowed here -- `viwdup.u32 q0,r0,pc,#1'
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:29: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
 [^:]*:30: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
 [^:]*:32: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
--- a/gas/testsuite/gas/arm/mve-vidup-bad.s
+++ b/gas/testsuite/gas/arm/mve-vidup-bad.s
@@ -1,16 +1,3 @@
-.macro cond1
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vidup.u32 q0, r2, #1
-.endr
-.endm
-
-.macro cond2
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-viwdup.u32 q0, r2, r1, #1
-.endr
-.endm
 .syntax unified
 .thumb
 vidup.s16 q0, r0, #1
@@ -23,8 +10,21 @@ viwdup.u32 q0, r0, r1, #3
 viwdup.u32 q0, r0, r1, #0
 viwdup.u32 q0, r0, sp, #1
 viwdup.u32 q0, r0, pc, #1
-cond1
-cond2
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vidup.u32 q0, r2, #1
+
+.endr
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+viwdup.u32 q0, r2, r1, #1
+
+.endr
+
 it eq
 vidupeq.u32 q0, r0, #1
 vidupeq.u32 q0, r0, #1
--- a/gas/testsuite/gas/arm/mve-vmax-vmin-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.l
@@ -1,20 +1,20 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vmax.s64 q0,q1,q2'
-[^:]*:11: Error: selected FPU does not support instruction -- `vmax.f16 q0,q1,q2'
-[^:]*:12: Error: bad type in SIMD instruction -- `vmax.u64 q0,q1,q2'
-[^:]*:13: Error: selected FPU does not support instruction -- `vmax.f32 q0,q1,q2'
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vmax.s64 q0,q1,q2'
+[^:]*:5: Error: selected FPU does not support instruction -- `vmax.f16 q0,q1,q2'
+[^:]*:6: Error: bad type in SIMD instruction -- `vmax.u64 q0,q1,q2'
+[^:]*:7: Error: selected FPU does not support instruction -- `vmax.f32 q0,q1,q2'
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
 [^:]*:18: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
 [^:]*:20: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmax-vmin-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.s
@@ -1,18 +1,18 @@
-.macro cond, op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s8 q0, q1, q2
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vmax.s64 q0, q1, q2
 vmax.f16 q0, q1, q2
 vmax.u64 q0, q1, q2
 vmax.f32 q0, q1, q2
-cond vmax
-cond vmin
+
+.irp op, vmax, vmin
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s8 q0, q1, q2
+.endr
+.endr
+
 it eq
 vmaxeq.s16 q0, q1, q2
 vmaxeq.s16 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.l
@@ -1,22 +1,22 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vmaxa.u8 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vmaxa.s64 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vmaxa.f16 q0,q1'
-[^:]*:13: Error: bad type in SIMD instruction -- `vmina.u8 q0,q1'
-[^:]*:14: Error: bad type in SIMD instruction -- `vmina.s64 q0,q1'
-[^:]*:15: Error: bad type in SIMD instruction -- `vmina.f16 q0,q1'
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vmaxa.u8 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vmaxa.s64 q0,q1'
+[^:]*:6: Error: bad type in SIMD instruction -- `vmaxa.f16 q0,q1'
+[^:]*:7: Error: bad type in SIMD instruction -- `vmina.u8 q0,q1'
+[^:]*:8: Error: bad type in SIMD instruction -- `vmina.s64 q0,q1'
+[^:]*:9: Error: bad type in SIMD instruction -- `vmina.f16 q0,q1'
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:19: Error: syntax error -- `vmaxaeq.s8 q0,q1'
 [^:]*:20: Error: syntax error -- `vmaxaeq.s8 q0,q1'
 [^:]*:22: Error: syntax error -- `vmaxaeq.s8 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.s
@@ -1,20 +1,20 @@
-.macro cond, op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s8 q0, q1
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vmaxa.u8 q0, q1
 vmaxa.s64 q0, q1
 vmaxa.f16 q0, q1
 vmina.u8 q0, q1
 vmina.s64 q0, q1
 vmina.f16 q0, q1
-cond vmaxa
-cond vmina
+
+.irp op, vmaxa, vmina
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s8 q0, q1
+.endr
+.endr
+
 it eq
 vmaxaeq.s8 q0, q1
 vmaxaeq.s8 q0, q1
--- a/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l
@@ -1,20 +1,20 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnm.f64 q0,q1,q2'
-[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnm.i16 q0,q1,q2'
-[^:]*:12: Error: bad type in SIMD instruction -- `vminnm.f64 q0,q1,q2'
-[^:]*:13: Error: bad type in SIMD instruction -- `vminnm.i16 q0,q1,q2'
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vmaxnm.f64 q0,q1,q2'
+[^:]*:5: Error: bad type in SIMD instruction -- `vmaxnm.i16 q0,q1,q2'
+[^:]*:6: Error: bad type in SIMD instruction -- `vminnm.f64 q0,q1,q2'
+[^:]*:7: Error: bad type in SIMD instruction -- `vminnm.i16 q0,q1,q2'
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2'
 [^:]*:18: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2'
 [^:]*:20: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s
@@ -1,18 +1,18 @@
-.macro cond, op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().f16 q0, q1, q2
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vmaxnm.f64 q0, q1, q2
 vmaxnm.i16 q0, q1, q2
 vminnm.f64 q0, q1, q2
 vminnm.i16 q0, q1, q2
-cond vmaxnm
-cond vminnm
+
+.irp op, vmaxnm, vminnm
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().f16 q0, q1, q2
+.endr
+.endr
+
 it eq
 vmaxnmeq.f32 q0, q1, q2
 vmaxnmeq.f32 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l
@@ -1,20 +1,20 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnma.f64 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnma.i16 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vminnma.f64 q0,q1'
-[^:]*:13: Error: bad type in SIMD instruction -- `vminnma.i16 q0,q1'
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vmaxnma.f64 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vmaxnma.i16 q0,q1'
+[^:]*:6: Error: bad type in SIMD instruction -- `vminnma.f64 q0,q1'
+[^:]*:7: Error: bad type in SIMD instruction -- `vminnma.i16 q0,q1'
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vmaxnmaeq.f32 q0,q1'
 [^:]*:18: Error: syntax error -- `vmaxnmaeq.f32 q0,q1'
 [^:]*:20: Error: syntax error -- `vmaxnmaeq.f32 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s
@@ -1,18 +1,18 @@
-.macro cond, op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().f16 q0, q1
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vmaxnma.f64 q0, q1
 vmaxnma.i16 q0, q1
 vminnma.f64 q0, q1
 vminnma.i16 q0, q1
-cond vmaxnma
-cond vminnma
+
+.irp op, vmaxnma, vminnma
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().f16 q0, q1
+.endr
+.endr
+
 it eq
 vmaxnmaeq.f32 q0, q1
 vmaxnmaeq.f32 q0, q1
--- a/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l
@@ -1,40 +1,40 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnmv.f64 r0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnmv.i16 r0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vminnmv.f64 r0,q1'
-[^:]*:13: Error: bad type in SIMD instruction -- `vminnmv.i16 r0,q1'
-[^:]*:14: Error: bad type in SIMD instruction -- `vmaxnmav.f64 r0,q1'
-[^:]*:15: Error: bad type in SIMD instruction -- `vmaxnmav.i16 r0,q1'
-[^:]*:16: Error: bad type in SIMD instruction -- `vminnmav.f64 r0,q1'
-[^:]*:17: Error: bad type in SIMD instruction -- `vminnmav.i16 r0,q1'
-[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vmaxnmv.f64 r0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vmaxnmv.i16 r0,q1'
+[^:]*:6: Error: bad type in SIMD instruction -- `vminnmv.f64 r0,q1'
+[^:]*:7: Error: bad type in SIMD instruction -- `vminnmv.i16 r0,q1'
+[^:]*:8: Error: bad type in SIMD instruction -- `vmaxnmav.f64 r0,q1'
+[^:]*:9: Error: bad type in SIMD instruction -- `vmaxnmav.i16 r0,q1'
+[^:]*:10: Error: bad type in SIMD instruction -- `vminnmav.f64 r0,q1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vminnmav.i16 r0,q1'
+[^:]*:12: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:13: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:14: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:15: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:27: Error: syntax error -- `vmaxnmveq.f32 r0,q1'
 [^:]*:28: Error: syntax error -- `vmaxnmveq.f32 r0,q1'
 [^:]*:30: Error: syntax error -- `vmaxnmveq.f32 r0,q1'
--- a/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s
@@ -1,12 +1,6 @@
-.macro cond, op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().f16 r0, q1
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vmaxnmv.f64 r0, q1
 vmaxnmv.i16 r0, q1
 vminnmv.f64 r0, q1
@@ -19,10 +13,16 @@ vmaxnmv.f16 sp, q1
 vmaxnmav.f32 pc, q1
 vminnmav.f16 sp, q1
 vminnmv.f32 pc, q1
-cond vmaxnmv
-cond vminnmv
-cond vmaxnmav
-cond vminnmav
+
+.irp op, vmaxnmv, vminnmv, vmaxnmav, vminnmav
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+\op\().f16 r0, q1
+
+.endr
+.endr
+
 it eq
 vmaxnmveq.f32 r0, q1
 vmaxnmveq.f32 r0, q1
--- a/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.l
@@ -1,40 +1,40 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vmaxv.u64 r0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vmaxv.f16 r0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vminv.s64 r0,q1'
-[^:]*:13: Error: bad type in SIMD instruction -- `vminv.f32 r0,q1'
-[^:]*:14: Error: bad type in SIMD instruction -- `vmaxav.u16 r0,q1'
-[^:]*:15: Error: bad type in SIMD instruction -- `vmaxav.f32 r0,q1'
-[^:]*:16: Error: bad type in SIMD instruction -- `vminav.u32 r0,q1'
-[^:]*:17: Error: bad type in SIMD instruction -- `vminav.f16 r0,q1'
-[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:20: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:21: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vmaxv.u64 r0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vmaxv.f16 r0,q1'
+[^:]*:6: Error: bad type in SIMD instruction -- `vminv.s64 r0,q1'
+[^:]*:7: Error: bad type in SIMD instruction -- `vminv.f32 r0,q1'
+[^:]*:8: Error: bad type in SIMD instruction -- `vmaxav.u16 r0,q1'
+[^:]*:9: Error: bad type in SIMD instruction -- `vmaxav.f32 r0,q1'
+[^:]*:10: Error: bad type in SIMD instruction -- `vminav.u32 r0,q1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vminav.f16 r0,q1'
+[^:]*:12: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:13: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:15: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:27: Error: syntax error -- `vmaxveq.s32 r0,q1'
 [^:]*:28: Error: syntax error -- `vmaxveq.s32 r0,q1'
 [^:]*:30: Error: syntax error -- `vmaxveq.s32 r0,q1'
--- a/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.s
@@ -1,12 +1,6 @@
-.macro cond, op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s16 r0, q1
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vmaxv.u64 r0, q1
 vmaxv.f16 r0, q1
 vminv.s64 r0, q1
@@ -19,10 +13,16 @@ vmaxv.s32 sp, q1
 vmaxav.s32 pc, q1
 vminv.s32 pc, q1
 vminav.s32 sp, q1
-cond vmaxv
-cond vmaxav
-cond vminv
-cond vminav
+
+.irp op, vmaxv, vmaxav, vminv, vminav
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+\op\().s16 r0, q1
+
+.endr
+.endr
+
 it eq
 vmaxveq.s32 r0, q1
 vmaxveq.s32 r0, q1
--- a/gas/testsuite/gas/arm/mve-vmladav-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmladav-bad.l
@@ -1,28 +1,28 @@
 [^:]*: Assembler messages:
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:14: Error: bad type in SIMD instruction -- `vmladav.s64 r0,q1,q2'
 [^:]*:15: Error: bad type in SIMD instruction -- `vmladav.f32 r0,q1,q2'
 [^:]*:16: Error: bad type in SIMD instruction -- `vmladava.s64 r0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmladav-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmladav-bad.s
@@ -1,16 +1,16 @@
-.macro cond, op
+.syntax unified
+.thumb
+
+.irp op, vmladav, vmladava, vmladavx, vmladavax
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 \op\().s16 r0, q1, q2
+
+.endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond vmladav
-cond vmladava
-cond vmladavx
-cond vmladavax
+
 vmladav.s64 r0, q1, q2
 vmladav.f32 r0, q1, q2
 vmladava.s64 r0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmlaldav-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmlaldav-bad.l
@@ -1,29 +1,29 @@
 [^:]*: Assembler messages:
-[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:15: Error: bad type in SIMD instruction -- `vmlaldav.s64 r0,r1,q1,q2'
 [^:]*:16: Error: bad type in SIMD instruction -- `vmlaldav.f32 r0,r1,q1,q2'
 [^:]*:17: Error: bad type in SIMD instruction -- `vmlaldav.s8 r0,r1,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmlaldav-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmlaldav-bad.s
@@ -1,17 +1,17 @@
-.macro cond, op
+.syntax unified
+.thumb
+
+vmlaldav.s16 r0, sp, q1, q2
+
+.irp op, vmlaldav, vmlaldava, vmlaldavx, vmlaldavax
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 \op\().s16 r0, r1, q1, q2
+
+.endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-vmlaldav.s16 r0, sp, q1, q2
-cond vmlaldav
-cond vmlaldava
-cond vmlaldavx
-cond vmlaldavax
 vmlaldav.s64 r0, r1, q1, q2
 vmlaldav.f32 r0, r1, q1, q2
 vmlaldav.s8 r0, r1, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmlalv-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmlalv-bad.l
@@ -1,16 +1,16 @@
 [^:]*: Assembler messages:
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:12: Error: bad type in SIMD instruction -- `vmlalv.s64 r0,r1,q1,q2'
 [^:]*:13: Error: bad type in SIMD instruction -- `vmlalv.f32 r0,r1,q1,q2'
 [^:]*:14: Error: bad type in SIMD instruction -- `vmlalv.s8 r0,r1,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmlalv-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmlalv-bad.s
@@ -1,14 +1,14 @@
-.macro cond, op
+.syntax unified
+.thumb
+.irp op, vmlalv, vmlalva
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 \op\().s16 r0, r1, q1, q2
+
+.endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond vmlalv
-cond vmlalva
 vmlalv.s64 r0, r1, q1, q2
 vmlalv.f32 r0, r1, q1, q2
 vmlalv.s8 r0, r1, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmlav-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmlav-bad.l
@@ -1,16 +1,16 @@
 [^:]*: Assembler messages:
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:12: Error: bad type in SIMD instruction -- `vmlav.s64 r0,q1,q2'
 [^:]*:13: Error: bad type in SIMD instruction -- `vmlav.f32 r0,q1,q2'
 [^:]*:14: Error: bad type in SIMD instruction -- `vmlava.s64 r0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmlav-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmlav-bad.s
@@ -1,14 +1,14 @@
-.macro cond, op
+.syntax unified
+.thumb
+.irp op, vmlav, vmlava
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 \op\().s16 r0, q1, q2
+
+.endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond vmlav
-cond vmlava
 vmlav.s64 r0, q1, q2
 vmlav.f32 r0, q1, q2
 vmlava.s64 r0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmlsdav-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmlsdav-bad.l
@@ -1,30 +1,30 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: Odd register not allowed here -- `vmlsdav.s16 r1,q1,q2'
-[^:]*:11: Error: bad type in SIMD instruction -- `vmlsdav.u16 r0,q1,q2'
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: Odd register not allowed here -- `vmlsdav.s16 r1,q1,q2'
+[^:]*:5: Error: bad type in SIMD instruction -- `vmlsdav.u16 r0,q1,q2'
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2'
 [^:]*:18: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2'
 [^:]*:20: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmlsdav-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmlsdav-bad.s
@@ -1,18 +1,18 @@
-.macro cond, op
+.syntax unified
+.thumb
+
+vmlsdav.s16 r1, q1, q2
+vmlsdav.u16 r0, q1, q2
+
+.irp op, vmlsdav, vmlsdava, vmlsdavx, vmlsdavax
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 \op\().s16 r0, q1, q2
+
+.endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-vmlsdav.s16 r1, q1, q2
-vmlsdav.u16 r0, q1, q2
-cond vmlsdav
-cond vmlsdava
-cond vmlsdavx
-cond vmlsdavax
 it eq
 vmlsdaveq.s16 r0, q1, q2
 vmlsdaveq.s16 r0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmlsldav-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmlsldav-bad.l
@@ -1,30 +1,30 @@
 [^:]*: Assembler messages:
-[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:11: Error: bad type in SIMD instruction -- `vmlsldav.u16 r0,r1,q1,q2'
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:5: Error: bad type in SIMD instruction -- `vmlsldav.u16 r0,r1,q1,q2'
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:16: Error: bad type in SIMD instruction -- `vmlsldav.s64 r0,r1,q1,q2'
 [^:]*:17: Error: bad type in SIMD instruction -- `vmlsldav.f32 r0,r1,q1,q2'
 [^:]*:18: Error: bad type in SIMD instruction -- `vmlsldav.s8 r0,r1,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmlsldav-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmlsldav-bad.s
@@ -1,18 +1,18 @@
-.macro cond, op
+.syntax unified
+.thumb
+
+vmlsldav.s16 r0, sp, q1, q2
+vmlsldav.u16 r0, r1, q1, q2
+
+.irp op, vmlsldav, vmlsldava, vmlsldavx, vmlsldavax
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 \op\().s16 r0, r1, q1, q2
+
+.endr
 .endr
-.endm
 
-.syntax unified
-.thumb
-vmlsldav.s16 r0, sp, q1, q2
-vmlsldav.u16 r0, r1, q1, q2
-cond vmlsldav
-cond vmlsldava
-cond vmlsldavx
-cond vmlsldavax
 vmlsldav.s64 r0, r1, q1, q2
 vmlsldav.f32 r0, r1, q1, q2
 vmlsldav.s8 r0, r1, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmla-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmla-bad.l
@@ -1,15 +1,15 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vmla.f16 q0,q1,r2'
-[^:]*:11: Error: bad type in SIMD instruction -- `vmla.s64 q0,q1,r2'
-[^:]*:12: Error: selected FPU does not support instruction -- `vmla.s32 q0,q1,q2'
-[^:]*:13: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vmla.f16 q0,q1,r2'
+[^:]*:4: Error: bad type in SIMD instruction -- `vmla.s64 q0,q1,r2'
+[^:]*:5: Error: selected FPU does not support instruction -- `vmla.s32 q0,q1,q2'
+[^:]*:6: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:7: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vmlaeq.u16 q0,q1,r2'
 [^:]*:18: Error: syntax error -- `vmlaeq.u16 q0,q1,r2'
 [^:]*:20: Error: syntax error -- `vmlaeq.u16 q0,q1,r2'
--- a/gas/testsuite/gas/arm/mve-vmla-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmla-bad.s
@@ -1,10 +1,3 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vmla.s16 q0, q1, r2
-.endr
-.endm
-
 .syntax unified
 .thumb
 vmla.f16 q0, q1, r2
@@ -12,7 +5,14 @@ vmla.s64 q0, q1, r2
 vmla.s32 q0, q1, q2
 vmla.s32 q0, q1, sp
 vmla.s32 q0, q1, pc
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vmla.s16 q0, q1, r2
+
+.endr
+
 it eq
 vmlaeq.u16 q0, q1, r2
 vmlaeq.u16 q0, q1, r2
--- a/gas/testsuite/gas/arm/mve-vmlas-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmlas-bad.l
@@ -1,14 +1,14 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vmlas.s64 q0,q1,r2'
-[^:]*:11: Error: bad type in SIMD instruction -- `vmlas.f32 q0,q1,r2'
-[^:]*:12: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:13: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vmlas.s64 q0,q1,r2'
+[^:]*:4: Error: bad type in SIMD instruction -- `vmlas.f32 q0,q1,r2'
+[^:]*:5: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:6: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:16: Error: syntax error -- `vmlaseq.s16 q0,q1,r2'
 [^:]*:17: Error: syntax error -- `vmlaseq.s16 q0,q1,r2'
 [^:]*:19: Error: syntax error -- `vmlaseq.s16 q0,q1,r2'
--- a/gas/testsuite/gas/arm/mve-vmlas-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmlas-bad.s
@@ -1,17 +1,17 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vmlas.s16 q0, q1, r2
-.endr
-.endm
-
 .syntax unified
 .thumb
 vmlas.s64 q0, q1, r2
 vmlas.f32 q0, q1, r2
 vmlas.u32 q0, q1, sp
 vmlas.u32 q0, q1, pc
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vmlas.s16 q0, q1, r2
+
+.endr
+
 it eq
 vmlaseq.s16 q0, q1, r2
 vmlaseq.s16 q0, q1, r2
--- a/gas/testsuite/gas/arm/mve-vmul-bad-1.l
+++ b/gas/testsuite/gas/arm/mve-vmul-bad-1.l
@@ -1,24 +1,24 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: selected FPU does not support instruction -- `vmul.f16 q0,q1,q2'
-[^:]*:11: Error: selected FPU does not support instruction -- `vmul.f16 q0,q1,r2'
-[^:]*:12: Error: selected FPU does not support instruction -- `vmul.f32 q0,q1,q2'
-[^:]*:13: Error: selected FPU does not support instruction -- `vmul.f32 q0,q1,r2'
-[^:]*:14: Error: bad type in SIMD instruction -- `vmul.i64 q0,q1,q2'
-[^:]*:15: Error: bad type in SIMD instruction -- `vmul.i64 q0,q1,r2'
-[^:]*:16: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:17: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: selected FPU does not support instruction -- `vmul.f16 q0,q1,q2'
+[^:]*:4: Error: selected FPU does not support instruction -- `vmul.f16 q0,q1,r2'
+[^:]*:5: Error: selected FPU does not support instruction -- `vmul.f32 q0,q1,q2'
+[^:]*:6: Error: selected FPU does not support instruction -- `vmul.f32 q0,q1,r2'
+[^:]*:7: Error: bad type in SIMD instruction -- `vmul.i64 q0,q1,q2'
+[^:]*:8: Error: bad type in SIMD instruction -- `vmul.i64 q0,q1,r2'
+[^:]*:9: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:21: Error: syntax error -- `vmuleq.i32 q0,q1,q2'
 [^:]*:22: Error: syntax error -- `vmuleq.i32 q0,q1,q2'
 [^:]*:24: Error: syntax error -- `vmuleq.i32 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmul-bad-1.s
+++ b/gas/testsuite/gas/arm/mve-vmul-bad-1.s
@@ -1,10 +1,3 @@
-.macro cond lastreg
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vmul.i16 q0, q1, \lastreg
-.endr
-.endm
-
 .syntax unified
 .thumb
 vmul.f16 q0, q1, q2
@@ -15,8 +8,15 @@ vmul.i64 q0, q1, q2
 vmul.i64 q0, q1, r2
 vmul.i8 q0, q1, pc
 vmul.i8 q0, q1, sp
-cond q2
-cond r2
+
+.irp lastreg, q2, r2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vmul.i16 q0, q1, \lastreg
+.endr
+.endr
+
+
 it eq
 vmuleq.i32 q0, q1, q2
 vmuleq.i32 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmulh-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmulh-bad.l
@@ -1,22 +1,22 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vmulh.f16 q0,q1,q2'
-[^:]*:11: Error: bad type in SIMD instruction -- `vmulh.i32 q0,q1,q2'
-[^:]*:12: Error: bad type in SIMD instruction -- `vmulh.s64 q0,q1,q2'
-[^:]*:13: Error: bad type in SIMD instruction -- `vrmulh.f16 q0,q1,q2'
-[^:]*:14: Error: bad type in SIMD instruction -- `vrmulh.i32 q0,q1,q2'
-[^:]*:15: Error: bad type in SIMD instruction -- `vrmulh.s64 q0,q1,q2'
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vmulh.f16 q0,q1,q2'
+[^:]*:4: Error: bad type in SIMD instruction -- `vmulh.i32 q0,q1,q2'
+[^:]*:5: Error: bad type in SIMD instruction -- `vmulh.s64 q0,q1,q2'
+[^:]*:6: Error: bad type in SIMD instruction -- `vrmulh.f16 q0,q1,q2'
+[^:]*:7: Error: bad type in SIMD instruction -- `vrmulh.i32 q0,q1,q2'
+[^:]*:8: Error: bad type in SIMD instruction -- `vrmulh.s64 q0,q1,q2'
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:19: Error: syntax error -- `vmulheq.s16 q0,q1,q2'
 [^:]*:20: Error: syntax error -- `vmulheq.s16 q0,q1,q2'
 [^:]*:22: Error: syntax error -- `vmulheq.s16 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmulh-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmulh-bad.s
@@ -1,10 +1,3 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().u16 q0, q1, q2
-.endr
-.endm
-
 .syntax unified
 .thumb
 vmulh.f16 q0, q1, q2
@@ -13,8 +6,15 @@ vmulh.s64 q0, q1, q2
 vrmulh.f16 q0, q1, q2
 vrmulh.i32 q0, q1, q2
 vrmulh.s64 q0, q1, q2
-cond vmulh
-cond vrmulh
+
+.irp op, vmulh, vrmulh
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().u16 q0, q1, q2
+.endr
+.endr
+
+
 it eq
 vmulheq.s16 q0, q1, q2
 vmulheq.s16 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmullbt-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmullbt-bad.l
@@ -1,33 +1,33 @@
 [^:]*: Assembler messages:
-[^:]*:13: Error: bad type in SIMD instruction -- `vmullb.s64 q0,q1,q2'
-[^:]*:14: Error: bad type in SIMD instruction -- `vmullb.f16 q0,q1,q2'
-[^:]*:15: Error: bad type in SIMD instruction -- `vmullb.f32 q0,q1,q2'
-[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Error: bad type in SIMD instruction -- `vmullt.s64 q0,q1,q2'
-[^:]*:20: Error: bad type in SIMD instruction -- `vmullt.f16 q0,q1,q2'
-[^:]*:21: Error: bad type in SIMD instruction -- `vmullt.f32 q0,q1,q2'
-[^:]*:22: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:23: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Error: syntax error -- `vmullbeq.s32 q0,q1,q2'
-[^:]*:27: Error: syntax error -- `vmullbeq.s32 q0,q1,q2'
-[^:]*:29: Error: syntax error -- `vmullbeq.s32 q0,q1,q2'
-[^:]*:31: Error: instruction missing MVE vector predication code -- `vmullb.s32 q0,q1,q2'
-[^:]*:32: Error: vector predicated instruction should be in VPT/VPST block -- `vmullbt.s32 q0,q1,q2'
-[^:]*:34: Error: syntax error -- `vmullteq.s32 q0,q1,q2'
-[^:]*:35: Error: syntax error -- `vmullteq.s32 q0,q1,q2'
-[^:]*:37: Error: syntax error -- `vmullteq.s32 q0,q1,q2'
-[^:]*:39: Error: instruction missing MVE vector predication code -- `vmullt.s32 q0,q1,q2'
-[^:]*:40: Error: vector predicated instruction should be in VPT/VPST block -- `vmulltt.s32 q0,q1,q2'
+[^:]*:6: Error: bad type in SIMD instruction -- `vmullb.s64 q0,q1,q2'
+[^:]*:7: Error: bad type in SIMD instruction -- `vmullb.f16 q0,q1,q2'
+[^:]*:8: Error: bad type in SIMD instruction -- `vmullb.f32 q0,q1,q2'
+[^:]*:9: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:10: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:6: Error: bad type in SIMD instruction -- `vmullt.s64 q0,q1,q2'
+[^:]*:7: Error: bad type in SIMD instruction -- `vmullt.f16 q0,q1,q2'
+[^:]*:8: Error: bad type in SIMD instruction -- `vmullt.f32 q0,q1,q2'
+[^:]*:9: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:10: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Error: syntax error -- `vmullbeq.s32 q0,q1,q2'
+[^:]*:19: Error: syntax error -- `vmullbeq.s32 q0,q1,q2'
+[^:]*:21: Error: syntax error -- `vmullbeq.s32 q0,q1,q2'
+[^:]*:23: Error: instruction missing MVE vector predication code -- `vmullb.s32 q0,q1,q2'
+[^:]*:24: Error: vector predicated instruction should be in VPT/VPST block -- `vmullbt.s32 q0,q1,q2'
+[^:]*:26: Error: syntax error -- `vmullteq.s32 q0,q1,q2'
+[^:]*:27: Error: syntax error -- `vmullteq.s32 q0,q1,q2'
+[^:]*:29: Error: syntax error -- `vmullteq.s32 q0,q1,q2'
+[^:]*:31: Error: instruction missing MVE vector predication code -- `vmullt.s32 q0,q1,q2'
+[^:]*:32: Error: vector predicated instruction should be in VPT/VPST block -- `vmulltt.s32 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vmullbt-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmullbt-bad.s
@@ -1,27 +1,19 @@
-.macro cond op
+.syntax unified
+.text
+.thumb
+
+.irp bt, b, t
+vmull\bt\().s64 q0, q1, q2
+vmull\bt\().f16 q0, q1, q2
+vmull\bt\().f32 q0, q1, q2
+vmull\bt\().s32 q1, q1, q2
+vmull\bt\().s32 q2, q1, q2
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
-\op\().s32 q0, q1, q2
+vmull\bt\().s32 q0, q1, q2
+.endr
 .endr
-.endm
-
-
 
-.syntax unified
-.text
-.thumb
-vmullb.s64 q0, q1, q2
-vmullb.f16 q0, q1, q2
-vmullb.f32 q0, q1, q2
-vmullb.s32  q1, q1, q2
-vmullb.s32  q2, q1, q2
-cond vmullb
-vmullt.s64 q0, q1, q2
-vmullt.f16 q0, q1, q2
-vmullt.f32 q0, q1, q2
-vmullt.u32  q1, q1, q2
-vmullt.u32  q2, q1, q2
-cond vmullt
 it eq
 vmullbeq.s32 q0, q1, q2
 vmullbeq.s32 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vmvn-bad.l
+++ b/gas/testsuite/gas/arm/mve-vmvn-bad.l
@@ -1,18 +1,18 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: invalid instruction shape -- `vmvn.i16 d0,d1'
-[^:]*:11: Error: immediate out of range -- `vmvn.i32 q0,#0x1ef'
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: invalid instruction shape -- `vmvn.i16 d0,d1'
+[^:]*:4: Error: immediate out of range -- `vmvn.i32 q0,#0x1ef'
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:9: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:15: Error: syntax error -- `vmvneq q0,q1'
 [^:]*:16: Error: syntax error -- `vmvneq q0,q1'
 [^:]*:18: Error: syntax error -- `vmvneq q0,q1'
--- a/gas/testsuite/gas/arm/mve-vmvn-bad.s
+++ b/gas/testsuite/gas/arm/mve-vmvn-bad.s
@@ -1,16 +1,16 @@
-.macro cond lastop
+.syntax unified
+.thumb
+vmvn.i16 d0, d1
+vmvn.i32 q0, #0x1ef
+
+.irp lastop, q1, #1
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
 vmvn.i16 q0, \lastop
 .endr
-.endm
+.endr
+
 
-.syntax unified
-.thumb
-vmvn.i16 d0, d1
-vmvn.i32 q0, #0x1ef
-cond q1
-cond #0
 it eq
 vmvneq q0, q1
 vmvneq q0, q1
--- a/gas/testsuite/gas/arm/mve-vorn-bad.l
+++ b/gas/testsuite/gas/arm/mve-vorn-bad.l
@@ -1,21 +1,21 @@
 [^:]*: Assembler messages:
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Error: syntax error -- `vorneq q0,q1,q2'
-[^:]*:20: Error: syntax error -- `vorneq q0,q1,q2'
-[^:]*:22: Error: syntax error -- `vorneq q0,q1,q2'
-[^:]*:24: Error: instruction missing MVE vector predication code -- `vorn q0,q1,q2'
-[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vornt q0,q1,q2'
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Error: syntax error -- `vorneq q0,q1,q2'
+[^:]*:13: Error: syntax error -- `vorneq q0,q1,q2'
+[^:]*:15: Error: syntax error -- `vorneq q0,q1,q2'
+[^:]*:17: Error: instruction missing MVE vector predication code -- `vorn q0,q1,q2'
+[^:]*:18: Error: vector predicated instruction should be in VPT/VPST block -- `vornt q0,q1,q2'
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:28: Error: syntax error -- `vorneq.i16 q0,#255'
 [^:]*:29: Error: syntax error -- `vorneq.i16 q0,#255'
 [^:]*:31: Error: syntax error -- `vorneq.i16 q0,#255'
--- a/gas/testsuite/gas/arm/mve-vorn-bad.s
+++ b/gas/testsuite/gas/arm/mve-vorn-bad.s
@@ -1,20 +1,13 @@
-.macro cond1
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 vorn q0, q1, q2
-.endr
-.endm
 
-.macro cond2
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vorn.i16 q0, #255
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond1
 it eq
 vorneq q0, q1, q2
 vorneq q0, q1, q2
@@ -23,7 +16,14 @@ vorneq q0, q1, q2
 vpst
 vorn q0, q1, q2
 vornt q0, q1, q2
-cond2
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vorn.i16 q0, #255
+
+.endr
+
 it eq
 vorneq.i16 q0, #255
 vorneq.i16 q0, #255
--- a/gas/testsuite/gas/arm/mve-vorr-bad.l
+++ b/gas/testsuite/gas/arm/mve-vorr-bad.l
@@ -1,21 +1,21 @@
 [^:]*: Assembler messages:
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Error: syntax error -- `vorreq q0,q1,q2'
-[^:]*:20: Error: syntax error -- `vorreq q0,q1,q2'
-[^:]*:22: Error: syntax error -- `vorreq q0,q1,q2'
-[^:]*:24: Error: instruction missing MVE vector predication code -- `vorr q0,q1,q2'
-[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vorrt q0,q1,q2'
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Error: syntax error -- `vorreq q0,q1,q2'
+[^:]*:13: Error: syntax error -- `vorreq q0,q1,q2'
+[^:]*:15: Error: syntax error -- `vorreq q0,q1,q2'
+[^:]*:17: Error: instruction missing MVE vector predication code -- `vorr q0,q1,q2'
+[^:]*:18: Error: vector predicated instruction should be in VPT/VPST block -- `vorrt q0,q1,q2'
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:28: Error: syntax error -- `vorreq.i16 q0,#255'
 [^:]*:29: Error: syntax error -- `vorreq.i16 q0,#255'
 [^:]*:31: Error: syntax error -- `vorreq.i16 q0,#255'
--- a/gas/testsuite/gas/arm/mve-vorr-bad.s
+++ b/gas/testsuite/gas/arm/mve-vorr-bad.s
@@ -1,20 +1,13 @@
-.macro cond1
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 vorr q0, q1, q2
-.endr
-.endm
 
-.macro cond2
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vorr.i16 q0, #255
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond1
 it eq
 vorreq q0, q1, q2
 vorreq q0, q1, q2
@@ -23,7 +16,14 @@ vorreq q0, q1, q2
 vpst
 vorr q0, q1, q2
 vorrt q0, q1, q2
-cond2
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vorr.i16 q0, #255
+
+.endr
+
 it eq
 vorreq.i16 q0, #255
 vorreq.i16 q0, #255
--- a/gas/testsuite/gas/arm/mve-vpnot-bad.l
+++ b/gas/testsuite/gas/arm/mve-vpnot-bad.l
@@ -1,10 +1,10 @@
 [^:]*: Assembler messages:
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:12: Error: syntax error -- `vpnoteq'
 [^:]*:13: Error: syntax error -- `vpnoteq'
 [^:]*:15: Error: syntax error -- `vpnoteq'
--- a/gas/testsuite/gas/arm/mve-vpnot-bad.s
+++ b/gas/testsuite/gas/arm/mve-vpnot-bad.s
@@ -1,13 +1,13 @@
-.macro cond
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 vpnot
+
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond
 it eq
 vpnoteq
 vpnoteq
--- a/gas/testsuite/gas/arm/mve-vpsel-bad.l
+++ b/gas/testsuite/gas/arm/mve-vpsel-bad.l
@@ -1,10 +1,10 @@
 [^:]*: Assembler messages:
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:7: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:12: Error: syntax error -- `vpseleq.i16 q0,q1,q2'
 [^:]*:13: Error: syntax error -- `vpseleq.i16 q0,q1,q2'
 [^:]*:15: Error: syntax error -- `vpseleq.i16 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vpsel-bad.s
+++ b/gas/testsuite/gas/arm/mve-vpsel-bad.s
@@ -1,13 +1,13 @@
-.macro cond
+.syntax unified
+.thumb
+
 .irp cond, eq, ne, gt, ge, lt, le
+
 it \cond
 vpsel.i16 q0, q1, q2
+
 .endr
-.endm
 
-.syntax unified
-.thumb
-cond
 it eq
 vpseleq.i16 q0, q1, q2
 vpseleq.i16 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vpt-bad-1.l
+++ b/gas/testsuite/gas/arm/mve-vpt-bad-1.l
@@ -1,16 +1,16 @@
 [^:]*: Assembler messages:
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:15: Warning: instruction is UNPREDICTABLE with SP operand
 [^:]*:17: Error: bad type in SIMD instruction -- `vpt.i64 eq,q0,q1'
 [^:]*:18: Error: selected FPU does not support instruction -- `vpt.f16 eq,q0,q1'
--- a/gas/testsuite/gas/arm/mve-vpt-bad-1.s
+++ b/gas/testsuite/gas/arm/mve-vpt-bad-1.s
@@ -1,4 +1,7 @@
-.macro cond1, lastreg
+.syntax unified
+.thumb
+
+.irp lastreg, q1, r1
 .irp cond, eq, ne, gt, ge, lt, le
 .irp size, .
 it \cond
@@ -6,12 +9,9 @@ vpt.i8 eq, q0, \lastreg
 vaddt.i32 q0, q1, q2
 .endr
 .endr
-.endm
+.endr
+
 
-.syntax unified
-.thumb
-cond1 q1
-cond1 r1
 vpt.i8 eq, q0, sp
 vaddt.i32 q0, q1, q2
 vpt.i64 eq, q0, q1
--- a/gas/testsuite/gas/arm/mve-vpt-bad-2.l
+++ b/gas/testsuite/gas/arm/mve-vpt-bad-2.l
@@ -1,16 +1,16 @@
 [^:]*: Assembler messages:
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:8: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:15: Warning: instruction is UNPREDICTABLE with SP operand
 [^:]*:17: Error: bad type in SIMD instruction -- `vpt.f64 eq,q0,q1'
 [^:]*:19: Error: syntax error -- `vpteq.f32 eq,q0,q1'
--- a/gas/testsuite/gas/arm/mve-vpt-bad-2.s
+++ b/gas/testsuite/gas/arm/mve-vpt-bad-2.s
@@ -1,4 +1,7 @@
-.macro cond1, lastreg
+.syntax unified
+.thumb
+
+.irp lastreg, q1, r1
 .irp cond, eq, ne, gt, ge, lt, le
 .irp size, .
 it \cond
@@ -6,12 +9,9 @@ vpt.f16 eq, q0, \lastreg
 vaddt.i32 q0, q1, q2
 .endr
 .endr
-.endm
+.endr
+
 
-.syntax unified
-.thumb
-cond1 q1
-cond1 r1
 vpt.f16 eq, q0, sp
 vaddt.i32 q0, q1, q2
 vpt.f64 eq, q0, q1
--- a/gas/testsuite/gas/arm/mve-vqabsneg-bad.l
+++ b/gas/testsuite/gas/arm/mve-vqabsneg-bad.l
@@ -1,20 +1,20 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vqabs.u8 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vqneg.u16 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vqabs.s64 q0,q1'
-[^:]*:13: Error: bad instruction `vqnegs.s64 q0,q1'
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vqabs.u8 q0,q1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vqneg.u16 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vqabs.s64 q0,q1'
+[^:]*:6: Error: bad instruction `vqnegs.s64 q0,q1'
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:17: Error: syntax error -- `vqabseq.s32 q0,q1'
 [^:]*:18: Error: syntax error -- `vqabseq.s32 q0,q1'
 [^:]*:19: Error: syntax error -- `vqabseq.s32 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vqabsneg-bad.s
+++ b/gas/testsuite/gas/arm/mve-vqabsneg-bad.s
@@ -1,18 +1,18 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s16 q0, q1
-.endr
-.endm
-
 .syntax unified
 .thumb
 vqabs.u8 q0, q1
 vqneg.u16 q0, q1
 vqabs.s64 q0, q1
 vqnegs.s64 q0, q1
-cond vqabs
-cond vqneg
+
+.irp op, vqabs, vqneg
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s16 q0, q1
+.endr
+.endr
+
+
 it eq
 vqabseq.s32 q0, q1
 vqabseq.s32 q0, q1
--- a/gas/testsuite/gas/arm/mve-vqdmladh-bad.l
+++ b/gas/testsuite/gas/arm/mve-vqdmladh-bad.l
@@ -1,36 +1,36 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vqdmladh.u32 q0,q1,q2'
-[^:]*:11: Error: bad type in SIMD instruction -- `vqdmladh.s64 q0,q1,q2'
-[^:]*:12: Error: bad type in SIMD instruction -- `vqdmladhx.u32 q0,q1,q2'
-[^:]*:13: Error: bad type in SIMD instruction -- `vqdmladhx.s64 q0,q1,q2'
-[^:]*:14: Error: bad type in SIMD instruction -- `vqrdmladh.u32 q0,q1,q2'
-[^:]*:15: Error: bad type in SIMD instruction -- `vqrdmladh.s64 q0,q1,q2'
-[^:]*:16: Error: bad type in SIMD instruction -- `vqrdmladhx.u32 q0,q1,q2'
-[^:]*:17: Error: bad type in SIMD instruction -- `vqrdmladhx.s64 q0,q1,q2'
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vqdmladh.u32 q0,q1,q2'
+[^:]*:4: Error: bad type in SIMD instruction -- `vqdmladh.s64 q0,q1,q2'
+[^:]*:5: Error: bad type in SIMD instruction -- `vqdmladhx.u32 q0,q1,q2'
+[^:]*:6: Error: bad type in SIMD instruction -- `vqdmladhx.s64 q0,q1,q2'
+[^:]*:7: Error: bad type in SIMD instruction -- `vqrdmladh.u32 q0,q1,q2'
+[^:]*:8: Error: bad type in SIMD instruction -- `vqrdmladh.s64 q0,q1,q2'
+[^:]*:9: Error: bad type in SIMD instruction -- `vqrdmladhx.u32 q0,q1,q2'
+[^:]*:10: Error: bad type in SIMD instruction -- `vqrdmladhx.s64 q0,q1,q2'
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:23: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
 [^:]*:24: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
 [^:]*:26: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vqdmladh-bad.s
+++ b/gas/testsuite/gas/arm/mve-vqdmladh-bad.s
@@ -1,10 +1,3 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s16 q0, q1, q2
-.endr
-.endm
-
 .syntax unified
 .thumb
 vqdmladh.u32 q0, q1, q2
@@ -15,10 +8,17 @@ vqrdmladh.u32 q0, q1, q2
 vqrdmladh.s64 q0, q1, q2
 vqrdmladhx.u32 q0, q1, q2
 vqrdmladhx.s64 q0, q1, q2
-cond vqdmladh
-cond vqdmladhx
-cond vqrdmladh
-cond vqrdmladhx
+
+.irp op, vqdmladh, vqdmladhx, vqrdmladh, vqrdmladhx
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+\op\().s16 q0, q1, q2
+
+.endr
+.endr
+
+
 it eq
 vqdmladheq.s32 q0, q1, q2
 vqdmladheq.s32 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
@@ -1,36 +1,36 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vqdmlsdh.u32 q0,q1,q2'
-[^:]*:11: Error: bad type in SIMD instruction -- `vqdmlsdh.s64 q0,q1,q2'
-[^:]*:12: Error: bad type in SIMD instruction -- `vqdmlsdhx.u32 q0,q1,q2'
-[^:]*:13: Error: bad type in SIMD instruction -- `vqdmlsdhx.s64 q0,q1,q2'
-[^:]*:14: Error: bad type in SIMD instruction -- `vqrdmlsdh.u32 q0,q1,q2'
-[^:]*:15: Error: bad type in SIMD instruction -- `vqrdmlsdh.s64 q0,q1,q2'
-[^:]*:16: Error: bad type in SIMD instruction -- `vqrdmlsdhx.u32 q0,q1,q2'
-[^:]*:17: Error: bad type in SIMD instruction -- `vqrdmlsdhx.s64 q0,q1,q2'
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vqdmlsdh.u32 q0,q1,q2'
+[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlsdh.s64 q0,q1,q2'
+[^:]*:5: Error: bad type in SIMD instruction -- `vqdmlsdhx.u32 q0,q1,q2'
+[^:]*:6: Error: bad type in SIMD instruction -- `vqdmlsdhx.s64 q0,q1,q2'
+[^:]*:7: Error: bad type in SIMD instruction -- `vqrdmlsdh.u32 q0,q1,q2'
+[^:]*:8: Error: bad type in SIMD instruction -- `vqrdmlsdh.s64 q0,q1,q2'
+[^:]*:9: Error: bad type in SIMD instruction -- `vqrdmlsdhx.u32 q0,q1,q2'
+[^:]*:10: Error: bad type in SIMD instruction -- `vqrdmlsdhx.s64 q0,q1,q2'
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:23: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
 [^:]*:24: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
 [^:]*:26: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
@@ -1,10 +1,3 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s16 q0, q1, q2
-.endr
-.endm
-
 .syntax unified
 .thumb
 vqdmlsdh.u32 q0, q1, q2
@@ -15,10 +8,17 @@ vqrdmlsdh.u32 q0, q1, q2
 vqrdmlsdh.s64 q0, q1, q2
 vqrdmlsdhx.u32 q0, q1, q2
 vqrdmlsdhx.s64 q0, q1, q2
-cond vqdmlsdh
-cond vqdmlsdhx
-cond vqrdmlsdh
-cond vqrdmlsdhx
+
+.irp op, vqdmlsdh, vqdmlsdhx, vqrdmlsdh, vqrdmlsdhx
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+\op\().s16 q0, q1, q2
+
+.endr
+.endr
+
+
 it eq
 vqdmlsdheq.s32 q0, q1, q2
 vqdmlsdheq.s32 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vqmovn-bad.l
+++ b/gas/testsuite/gas/arm/mve-vqmovn-bad.l
@@ -1,44 +1,44 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vqmovnt.s8 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vqmovnt.s64 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vqmovnt.i16 q0,q1'
-[^:]*:13: Error: bad type in SIMD instruction -- `vqmovnb.u8 q0,q1'
-[^:]*:14: Error: bad type in SIMD instruction -- `vqmovnb.u64 q0,q1'
-[^:]*:15: Error: bad type in SIMD instruction -- `vqmovnb.i16 q0,q1'
-[^:]*:16: Error: bad type in SIMD instruction -- `vqmovunt.s8 q0,q1'
-[^:]*:17: Error: bad type in SIMD instruction -- `vqmovunt.s64 q0,q1'
-[^:]*:18: Error: bad type in SIMD instruction -- `vqmovunt.i16 q0,q1'
-[^:]*:19: Error: bad type in SIMD instruction -- `vqmovunb.s8 q0,q1'
-[^:]*:20: Error: bad type in SIMD instruction -- `vqmovunb.s64 q0,q1'
-[^:]*:21: Error: bad type in SIMD instruction -- `vqmovunb.i16 q0,q1'
-[^:]*:22: Error: bad type in SIMD instruction -- `vqmovunt.u16 q0,q1'
-[^:]*:23: Error: bad type in SIMD instruction -- `vqmovunt.u32 q0,q1'
-[^:]*:24: Error: bad type in SIMD instruction -- `vqmovunb.u16 q0,q1'
-[^:]*:25: Error: bad type in SIMD instruction -- `vqmovunb.u32 q0,q1'
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vqmovnt.s8 q0,q1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vqmovnt.s64 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vqmovnt.i16 q0,q1'
+[^:]*:6: Error: bad type in SIMD instruction -- `vqmovnb.u8 q0,q1'
+[^:]*:7: Error: bad type in SIMD instruction -- `vqmovnb.u64 q0,q1'
+[^:]*:8: Error: bad type in SIMD instruction -- `vqmovnb.i16 q0,q1'
+[^:]*:9: Error: bad type in SIMD instruction -- `vqmovunt.s8 q0,q1'
+[^:]*:10: Error: bad type in SIMD instruction -- `vqmovunt.s64 q0,q1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqmovunt.i16 q0,q1'
+[^:]*:12: Error: bad type in SIMD instruction -- `vqmovunb.s8 q0,q1'
+[^:]*:13: Error: bad type in SIMD instruction -- `vqmovunb.s64 q0,q1'
+[^:]*:14: Error: bad type in SIMD instruction -- `vqmovunb.i16 q0,q1'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqmovunt.u16 q0,q1'
+[^:]*:16: Error: bad type in SIMD instruction -- `vqmovunt.u32 q0,q1'
+[^:]*:17: Error: bad type in SIMD instruction -- `vqmovunb.u16 q0,q1'
+[^:]*:18: Error: bad type in SIMD instruction -- `vqmovunb.u32 q0,q1'
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:31: Error: syntax error -- `vqmovnteq.s16 q0,q1'
 [^:]*:32: Error: syntax error -- `vqmovnteq.s16 q0,q1'
 [^:]*:34: Error: syntax error -- `vqmovnteq.s16 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vqmovn-bad.s
+++ b/gas/testsuite/gas/arm/mve-vqmovn-bad.s
@@ -1,10 +1,3 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s16 q0, q1
-.endr
-.endm
-
 .syntax unified
 .thumb
 vqmovnt.s8 q0, q1
@@ -23,10 +16,17 @@ vqmovunt.u16 q0, q1
 vqmovunt.u32 q0, q1
 vqmovunb.u16 q0, q1
 vqmovunb.u32 q0, q1
-cond vqmovnt
-cond vqmovnb
-cond vqmovunt
-cond vqmovunb
+
+.irp op, vqmovnt, vqmovnb, vqmovunt, vqmovunb
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+\op\().s16 q0, q1
+
+.endr
+.endr
+
+
 it eq
 vqmovnteq.s16 q0, q1
 vqmovnteq.s16 q0, q1
--- a/gas/testsuite/gas/arm/mve-vqrshl-bad.l
+++ b/gas/testsuite/gas/arm/mve-vqrshl-bad.l
@@ -1,25 +1,25 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,q1,q2'
-[^:]*:11: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,q1,q2'
-[^:]*:12: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,q1,q2'
-[^:]*:13: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,r2'
-[^:]*:14: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,r2'
-[^:]*:15: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,r2'
-[^:]*:16: Error: invalid instruction shape -- `vqrshl.s32 q0,q1,r2'
-[^:]*:17: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,q1,q2'
+[^:]*:4: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,q1,q2'
+[^:]*:5: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,q1,q2'
+[^:]*:6: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,r2'
+[^:]*:7: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,r2'
+[^:]*:8: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,r2'
+[^:]*:9: Error: invalid instruction shape -- `vqrshl.s32 q0,q1,r2'
+[^:]*:10: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:11: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:22: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
 [^:]*:23: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
 [^:]*:25: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vqrshl-bad.s
+++ b/gas/testsuite/gas/arm/mve-vqrshl-bad.s
@@ -1,10 +1,3 @@
-.macro cond lastreg
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vqrshl.s16 q0, q0, \lastreg
-.endr
-.endm
-
 .syntax unified
 .thumb
 vqrshl.s64 q0, q1, q2
@@ -16,8 +9,15 @@ vqrshl.i32 q0, r2
 vqrshl.s32 q0, q1, r2
 vqrshl.s32 q0, pc
 vqrshl.s32 q0, sp
-cond q2
-cond r2
+
+.irp lastreg, q2, r2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vqrshl.s16 q0, q0, \lastreg
+.endr
+.endr
+
+
 it eq
 vqrshleq.s32 q0, q1, q2
 vqrshleq.s32 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vqrshrn-bad.l
+++ b/gas/testsuite/gas/arm/mve-vqrshrn-bad.l
@@ -1,54 +1,54 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vqrshrnt.s8 q0,q1,#1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vqrshrnt.s64 q0,q1,#1'
-[^:]*:12: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnt.s16 q0,q1,#0'
-[^:]*:13: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnt.s16 q0,q1,#9'
-[^:]*:14: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnt.s32 q0,q1,#0'
-[^:]*:15: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnt.s32 q0,q1,#17'
-[^:]*:16: Error: bad type in SIMD instruction -- `vqrshrnb.s8 q0,q1,#1'
-[^:]*:17: Error: bad type in SIMD instruction -- `vqrshrnb.s64 q0,q1,#1'
-[^:]*:18: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnb.s16 q0,q1,#0'
-[^:]*:19: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnb.s16 q0,q1,#9'
-[^:]*:20: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnb.s32 q0,q1,#0'
-[^:]*:21: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnb.s32 q0,q1,#17'
-[^:]*:22: Error: bad type in SIMD instruction -- `vqrshrunt.s8 q0,q1,#1'
-[^:]*:23: Error: bad type in SIMD instruction -- `vqrshrunt.s64 q0,q1,#1'
-[^:]*:24: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunt.s16 q0,q1,#0'
-[^:]*:25: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunt.s16 q0,q1,#9'
-[^:]*:26: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunt.s32 q0,q1,#0'
-[^:]*:27: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunt.s32 q0,q1,#17'
-[^:]*:28: Error: bad type in SIMD instruction -- `vqrshrunt.u16 q0,q1,#1'
-[^:]*:29: Error: bad type in SIMD instruction -- `vqrshrunb.s8 q0,q1,#1'
-[^:]*:30: Error: bad type in SIMD instruction -- `vqrshrunb.s64 q0,q1,#1'
-[^:]*:31: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunb.s16 q0,q1,#0'
-[^:]*:32: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunb.s16 q0,q1,#9'
-[^:]*:33: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunb.s32 q0,q1,#0'
-[^:]*:34: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunb.s32 q0,q1,#17'
-[^:]*:35: Error: bad type in SIMD instruction -- `vqrshrunb.u16 q0,q1,#1'
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vqrshrnt.s8 q0,q1,#1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vqrshrnt.s64 q0,q1,#1'
+[^:]*:6: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnt.s16 q0,q1,#0'
+[^:]*:7: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnt.s16 q0,q1,#9'
+[^:]*:8: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnt.s32 q0,q1,#0'
+[^:]*:9: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnt.s32 q0,q1,#17'
+[^:]*:10: Error: bad type in SIMD instruction -- `vqrshrnb.s8 q0,q1,#1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqrshrnb.s64 q0,q1,#1'
+[^:]*:12: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnb.s16 q0,q1,#0'
+[^:]*:13: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnb.s16 q0,q1,#9'
+[^:]*:14: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnb.s32 q0,q1,#0'
+[^:]*:15: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnb.s32 q0,q1,#17'
+[^:]*:16: Error: bad type in SIMD instruction -- `vqrshrunt.s8 q0,q1,#1'
+[^:]*:17: Error: bad type in SIMD instruction -- `vqrshrunt.s64 q0,q1,#1'
+[^:]*:18: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunt.s16 q0,q1,#0'
+[^:]*:19: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunt.s16 q0,q1,#9'
+[^:]*:20: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunt.s32 q0,q1,#0'
+[^:]*:21: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunt.s32 q0,q1,#17'
+[^:]*:22: Error: bad type in SIMD instruction -- `vqrshrunt.u16 q0,q1,#1'
+[^:]*:23: Error: bad type in SIMD instruction -- `vqrshrunb.s8 q0,q1,#1'
+[^:]*:24: Error: bad type in SIMD instruction -- `vqrshrunb.s64 q0,q1,#1'
+[^:]*:25: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunb.s16 q0,q1,#0'
+[^:]*:26: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunb.s16 q0,q1,#9'
+[^:]*:27: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunb.s32 q0,q1,#0'
+[^:]*:28: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunb.s32 q0,q1,#17'
+[^:]*:29: Error: bad type in SIMD instruction -- `vqrshrunb.u16 q0,q1,#1'
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:41: Error: syntax error -- `vqrshrnteq.s16 q0,q1,#1'
 [^:]*:42: Error: syntax error -- `vqrshrnteq.s16 q0,q1,#1'
 [^:]*:44: Error: syntax error -- `vqrshrnteq.s16 q0,q1,#1'
--- a/gas/testsuite/gas/arm/mve-vqrshrn-bad.s
+++ b/gas/testsuite/gas/arm/mve-vqrshrn-bad.s
@@ -1,12 +1,6 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s16 q0, q0, #1
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vqrshrnt.s8 q0, q1, #1
 vqrshrnt.s64 q0, q1, #1
 vqrshrnt.s16 q0, q1, #0
@@ -33,10 +27,16 @@ vqrshrunb.s16 q0, q1, #9
 vqrshrunb.s32 q0, q1, #0
 vqrshrunb.s32 q0, q1, #17
 vqrshrunb.u16 q0, q1, #1
-cond vqrshrnt
-cond vqrshrnb
-cond vqrshrunt
-cond vqrshrunb
+
+.irp op, vqrshrnt, vqrshrnb, vqrshrunt, vqrshrunb
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+\op\().s16 q0, q0, #1
+
+.endr
+.endr
+
 it eq
 vqrshrnteq.s16 q0, q1, #1
 vqrshrnteq.s16 q0, q1, #1
--- a/gas/testsuite/gas/arm/mve-vrev-bad.l
+++ b/gas/testsuite/gas/arm/mve-vrev-bad.l
@@ -1,26 +1,26 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: elements must be smaller than reversal region -- `vrev16.16 q0,q1'
-[^:]*:11: Error: elements must be smaller than reversal region -- `vrev32.32 q0,q1'
-[^:]*:12: Error: elements must be smaller than reversal region -- `vrev64.64 q0,q1'
-[^:]*:13: Warning: 64-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: elements must be smaller than reversal region -- `vrev16.16 q0,q1'
+[^:]*:4: Error: elements must be smaller than reversal region -- `vrev32.32 q0,q1'
+[^:]*:5: Error: elements must be smaller than reversal region -- `vrev64.64 q0,q1'
+[^:]*:6: Warning: 64-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:18: Error: syntax error -- `vrev16eq.8 q0,q1'
 [^:]*:19: Error: syntax error -- `vrev16eq.8 q0,q1'
 [^:]*:21: Error: syntax error -- `vrev16eq.8 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vrev-bad.s
+++ b/gas/testsuite/gas/arm/mve-vrev-bad.s
@@ -1,19 +1,19 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().8 q0, q1
-.endr
-.endm
-
 .syntax unified
 .thumb
 vrev16.16 q0, q1
 vrev32.32 q0, q1
 vrev64.64 q0, q1
 vrev64.8  q0, q0
-cond vrev16
-cond vrev32
-cond vrev64
+
+.irp op, vrev16, vrev32, vrev64
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+\op\().8 q0, q1
+
+.endr
+.endr
+
 it eq
 vrev16eq.8 q0, q1
 vrev16eq.8 q0, q1
--- a/gas/testsuite/gas/arm/mve-vrint-bad.l
+++ b/gas/testsuite/gas/arm/mve-vrint-bad.l
@@ -1,78 +1,78 @@
 [^:]*: Assembler messages:
-[^:]*:11: Error: bad type in SIMD instruction -- `vrintn.i16 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vrintn.f64 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vrintx.i16 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vrintx.f64 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vrinta.i16 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vrinta.f64 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vrintz.i16 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vrintz.f64 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vrintm.i16 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vrintm.f64 q0,q1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vrintp.i16 q0,q1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vrintp.f64 q0,q1'
-[^:]*:14: Error: VFP single, double or Neon quad precision register expected -- `vrintr.f16 q0,q1'
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vrintn.i16 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vrintn.f64 q0,q1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vrintx.i16 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vrintx.f64 q0,q1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vrinta.i16 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vrinta.f64 q0,q1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vrintz.i16 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vrintz.f64 q0,q1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vrintm.i16 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vrintm.f64 q0,q1'
+[^:]*:4: Error: bad type in SIMD instruction -- `vrintp.i16 q0,q1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vrintp.f64 q0,q1'
+[^:]*:7: Error: VFP single, double or Neon quad precision register expected -- `vrintr.f16 q0,q1'
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:18: Error: syntax error -- `vrintneq.f16 q0,q1'
 [^:]*:19: Error: syntax error -- `vrintneq.f16 q0,q1'
 [^:]*:21: Error: syntax error -- `vrintneq.f16 q0,q1'
 [^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintnt.f16 q0,q1'
 [^:]*:24: Error: instruction missing MVE vector predication code -- `vrintn.f16 q0,q1'
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:18: Error: syntax error -- `vrintxeq.f16 q0,q1'
 [^:]*:19: Error: syntax error -- `vrintxeq.f16 q0,q1'
 [^:]*:21: Error: syntax error -- `vrintxeq.f16 q0,q1'
 [^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintxt.f16 q0,q1'
 [^:]*:24: Error: instruction missing MVE vector predication code -- `vrintx.f16 q0,q1'
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:18: Error: syntax error -- `vrintaeq.f16 q0,q1'
 [^:]*:19: Error: syntax error -- `vrintaeq.f16 q0,q1'
 [^:]*:21: Error: syntax error -- `vrintaeq.f16 q0,q1'
 [^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintat.f16 q0,q1'
 [^:]*:24: Error: instruction missing MVE vector predication code -- `vrinta.f16 q0,q1'
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:18: Error: syntax error -- `vrintzeq.f16 q0,q1'
 [^:]*:19: Error: syntax error -- `vrintzeq.f16 q0,q1'
 [^:]*:21: Error: syntax error -- `vrintzeq.f16 q0,q1'
 [^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintzt.f16 q0,q1'
 [^:]*:24: Error: instruction missing MVE vector predication code -- `vrintz.f16 q0,q1'
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:18: Error: syntax error -- `vrintmeq.f16 q0,q1'
 [^:]*:19: Error: syntax error -- `vrintmeq.f16 q0,q1'
 [^:]*:21: Error: syntax error -- `vrintmeq.f16 q0,q1'
 [^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintmt.f16 q0,q1'
 [^:]*:24: Error: instruction missing MVE vector predication code -- `vrintm.f16 q0,q1'
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:18: Error: syntax error -- `vrintpeq.f16 q0,q1'
 [^:]*:19: Error: syntax error -- `vrintpeq.f16 q0,q1'
 [^:]*:21: Error: syntax error -- `vrintpeq.f16 q0,q1'
--- a/gas/testsuite/gas/arm/mve-vrint-bad.s
+++ b/gas/testsuite/gas/arm/mve-vrint-bad.s
@@ -1,10 +1,3 @@
-.macro cond, mode
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vrint\mode\().f16 q0, q1
-.endr
-.endm
-
 .syntax unified
 .thumb
 .irp mode, n, x, a, z, m, p
@@ -12,8 +5,15 @@ vrint\mode\().i16 q0, q1
 vrint\mode\().f64 q0, q1
 .endr
 vrintr.f16 q0, q1
+
 .irp mode, n, x, a, z, m, p
-cond \mode
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vrint\mode\().f16 q0, q1
+
+.endr
+
 it eq
 vrint\mode\()eq.f16 q0, q1
 vrint\mode\()eq.f16 q0, q1
--- a/gas/testsuite/gas/arm/mve-vrmlaldavh-bad.l
+++ b/gas/testsuite/gas/arm/mve-vrmlaldavh-bad.l
@@ -1,124 +1,124 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vrmlaldavh.s16 r0,r1,q2,q3'
-[^:]*:11: Error: bad type in SIMD instruction -- `vrmlaldavh.i32 r0,r1,q2,q3'
-[^:]*:12: Error: bad type in SIMD instruction -- `vrmlaldavha.s16 r0,r1,q2,q3'
-[^:]*:13: Error: bad type in SIMD instruction -- `vrmlaldavha.i32 r0,r1,q2,q3'
-[^:]*:14: Error: bad type in SIMD instruction -- `vrmlalvh.s16 r0,r1,q2,q3'
-[^:]*:15: Error: bad type in SIMD instruction -- `vrmlalvh.i32 r0,r1,q2,q3'
-[^:]*:16: Error: bad type in SIMD instruction -- `vrmlalvha.s16 r0,r1,q2,q3'
-[^:]*:17: Error: bad type in SIMD instruction -- `vrmlalvha.i32 r0,r1,q2,q3'
-[^:]*:18: Error: bad type in SIMD instruction -- `vrmlaldavhx.u32 r0,r1,q2,q3'
-[^:]*:19: Error: bad type in SIMD instruction -- `vrmlaldavhax.u32 r0,r1,q2,q3'
-[^:]*:20: Error: bad type in SIMD instruction -- `vrmlaldavhx.i32 r0,r1,q2,q3'
-[^:]*:21: Error: bad type in SIMD instruction -- `vrmlaldavhax.i32 r0,r1,q2,q3'
-[^:]*:22: Error: bad type in SIMD instruction -- `vrmlsldavh.s16 r0,r1,q2,q3'
-[^:]*:23: Error: bad type in SIMD instruction -- `vrmlsldavh.u32 r0,r1,q2,q3'
-[^:]*:24: Error: bad type in SIMD instruction -- `vrmlsldavha.s16 r0,r1,q2,q3'
-[^:]*:25: Error: bad type in SIMD instruction -- `vrmlsldavha.u32 r0,r1,q2,q3'
-[^:]*:26: Error: bad type in SIMD instruction -- `vrmlsldavhx.s16 r0,r1,q2,q3'
-[^:]*:27: Error: bad type in SIMD instruction -- `vrmlsldavhx.u32 r0,r1,q2,q3'
-[^:]*:28: Error: bad type in SIMD instruction -- `vrmlsldavhax.s16 r0,r1,q2,q3'
-[^:]*:29: Error: bad type in SIMD instruction -- `vrmlsldavhax.u32 r0,r1,q2,q3'
-[^:]*:30: Error: Odd register not allowed here -- `vrmlaldavh.s32 r1,r1,q2,q3'
-[^:]*:31: Error: Even register not allowed here -- `vrmlaldavh.s32 r0,r0,q2,q3'
-[^:]*:32: Error: r13 not allowed here -- `vrmlaldavh.s32 r0,sp,q2,q3'
-[^:]*:33: Error: r15 not allowed here -- `vrmlaldavh.s32 r0,pc,q2,q3'
-[^:]*:34: Error: Odd register not allowed here -- `vrmlaldavha.s32 r1,r1,q2,q3'
-[^:]*:35: Error: Even register not allowed here -- `vrmlaldavha.s32 r0,r0,q2,q3'
-[^:]*:36: Error: r13 not allowed here -- `vrmlaldavha.s32 r0,sp,q2,q3'
-[^:]*:37: Error: r15 not allowed here -- `vrmlaldavha.s32 r0,pc,q2,q3'
-[^:]*:38: Error: Odd register not allowed here -- `vrmlaldavhx.s32 r1,r1,q2,q3'
-[^:]*:39: Error: Even register not allowed here -- `vrmlaldavhx.s32 r0,r0,q2,q3'
-[^:]*:40: Error: r13 not allowed here -- `vrmlaldavhx.s32 r0,sp,q2,q3'
-[^:]*:41: Error: r15 not allowed here -- `vrmlaldavhx.s32 r0,pc,q2,q3'
-[^:]*:42: Error: Odd register not allowed here -- `vrmlaldavhax.s32 r1,r1,q2,q3'
-[^:]*:43: Error: Even register not allowed here -- `vrmlaldavhax.s32 r0,r0,q2,q3'
-[^:]*:44: Error: r13 not allowed here -- `vrmlaldavhax.s32 r0,sp,q2,q3'
-[^:]*:45: Error: r15 not allowed here -- `vrmlaldavhax.s32 r0,pc,q2,q3'
-[^:]*:46: Error: Odd register not allowed here -- `vrmlalvh.s32 r1,r1,q2,q3'
-[^:]*:47: Error: Even register not allowed here -- `vrmlalvh.s32 r0,r0,q2,q3'
-[^:]*:48: Error: r13 not allowed here -- `vrmlalvh.s32 r0,sp,q2,q3'
-[^:]*:49: Error: r15 not allowed here -- `vrmlalvh.s32 r0,pc,q2,q3'
-[^:]*:50: Error: Odd register not allowed here -- `vrmlalvha.s32 r1,r1,q2,q3'
-[^:]*:51: Error: Even register not allowed here -- `vrmlalvha.s32 r0,r0,q2,q3'
-[^:]*:52: Error: r13 not allowed here -- `vrmlalvha.s32 r0,sp,q2,q3'
-[^:]*:53: Error: r15 not allowed here -- `vrmlalvha.s32 r0,pc,q2,q3'
-[^:]*:54: Error: Odd register not allowed here -- `vrmlsldavh.s32 r1,r1,q2,q3'
-[^:]*:55: Error: Even register not allowed here -- `vrmlsldavh.s32 r0,r0,q2,q3'
-[^:]*:56: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:57: Error: r15 not allowed here -- `vrmlsldavh.s32 r0,pc,q2,q3'
-[^:]*:58: Error: Odd register not allowed here -- `vrmlsldavha.s32 r1,r1,q2,q3'
-[^:]*:59: Error: Even register not allowed here -- `vrmlsldavha.s32 r0,r0,q2,q3'
-[^:]*:60: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:61: Error: r15 not allowed here -- `vrmlsldavha.s32 r0,pc,q2,q3'
-[^:]*:62: Error: Odd register not allowed here -- `vrmlsldavhx.s32 r1,r1,q2,q3'
-[^:]*:63: Error: Even register not allowed here -- `vrmlsldavhx.s32 r0,r0,q2,q3'
-[^:]*:64: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:65: Error: r15 not allowed here -- `vrmlsldavhx.s32 r0,pc,q2,q3'
-[^:]*:66: Error: Odd register not allowed here -- `vrmlsldavhax.s32 r1,r1,q2,q3'
-[^:]*:67: Error: Even register not allowed here -- `vrmlsldavhax.s32 r0,r0,q2,q3'
-[^:]*:68: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:69: Error: r15 not allowed here -- `vrmlsldavhax.s32 r0,pc,q2,q3'
-[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:5: Error: bad type in SIMD instruction -- `vrmlaldavh.s16 r0,r1,q2,q3'
+[^:]*:6: Error: bad type in SIMD instruction -- `vrmlaldavh.i32 r0,r1,q2,q3'
+[^:]*:7: Error: bad type in SIMD instruction -- `vrmlaldavha.s16 r0,r1,q2,q3'
+[^:]*:8: Error: bad type in SIMD instruction -- `vrmlaldavha.i32 r0,r1,q2,q3'
+[^:]*:9: Error: bad type in SIMD instruction -- `vrmlalvh.s16 r0,r1,q2,q3'
+[^:]*:10: Error: bad type in SIMD instruction -- `vrmlalvh.i32 r0,r1,q2,q3'
+[^:]*:11: Error: bad type in SIMD instruction -- `vrmlalvha.s16 r0,r1,q2,q3'
+[^:]*:12: Error: bad type in SIMD instruction -- `vrmlalvha.i32 r0,r1,q2,q3'
+[^:]*:13: Error: bad type in SIMD instruction -- `vrmlaldavhx.u32 r0,r1,q2,q3'
+[^:]*:14: Error: bad type in SIMD instruction -- `vrmlaldavhax.u32 r0,r1,q2,q3'
+[^:]*:15: Error: bad type in SIMD instruction -- `vrmlaldavhx.i32 r0,r1,q2,q3'
+[^:]*:16: Error: bad type in SIMD instruction -- `vrmlaldavhax.i32 r0,r1,q2,q3'
+[^:]*:18: Error: bad type in SIMD instruction -- `vrmlsldavh.s16 r0,r1,q2,q3'
+[^:]*:19: Error: bad type in SIMD instruction -- `vrmlsldavh.u32 r0,r1,q2,q3'
+[^:]*:20: Error: bad type in SIMD instruction -- `vrmlsldavha.s16 r0,r1,q2,q3'
+[^:]*:21: Error: bad type in SIMD instruction -- `vrmlsldavha.u32 r0,r1,q2,q3'
+[^:]*:22: Error: bad type in SIMD instruction -- `vrmlsldavhx.s16 r0,r1,q2,q3'
+[^:]*:23: Error: bad type in SIMD instruction -- `vrmlsldavhx.u32 r0,r1,q2,q3'
+[^:]*:24: Error: bad type in SIMD instruction -- `vrmlsldavhax.s16 r0,r1,q2,q3'
+[^:]*:25: Error: bad type in SIMD instruction -- `vrmlsldavhax.u32 r0,r1,q2,q3'
+[^:]*:27: Error: Odd register not allowed here -- `vrmlaldavh.s32 r1,r1,q2,q3'
+[^:]*:28: Error: Even register not allowed here -- `vrmlaldavh.s32 r0,r0,q2,q3'
+[^:]*:29: Error: r13 not allowed here -- `vrmlaldavh.s32 r0,sp,q2,q3'
+[^:]*:30: Error: r15 not allowed here -- `vrmlaldavh.s32 r0,pc,q2,q3'
+[^:]*:31: Error: Odd register not allowed here -- `vrmlaldavha.s32 r1,r1,q2,q3'
+[^:]*:32: Error: Even register not allowed here -- `vrmlaldavha.s32 r0,r0,q2,q3'
+[^:]*:33: Error: r13 not allowed here -- `vrmlaldavha.s32 r0,sp,q2,q3'
+[^:]*:34: Error: r15 not allowed here -- `vrmlaldavha.s32 r0,pc,q2,q3'
+[^:]*:35: Error: Odd register not allowed here -- `vrmlaldavhx.s32 r1,r1,q2,q3'
+[^:]*:36: Error: Even register not allowed here -- `vrmlaldavhx.s32 r0,r0,q2,q3'
+[^:]*:37: Error: r13 not allowed here -- `vrmlaldavhx.s32 r0,sp,q2,q3'
+[^:]*:38: Error: r15 not allowed here -- `vrmlaldavhx.s32 r0,pc,q2,q3'
+[^:]*:39: Error: Odd register not allowed here -- `vrmlaldavhax.s32 r1,r1,q2,q3'
+[^:]*:40: Error: Even register not allowed here -- `vrmlaldavhax.s32 r0,r0,q2,q3'
+[^:]*:41: Error: r13 not allowed here -- `vrmlaldavhax.s32 r0,sp,q2,q3'
+[^:]*:42: Error: r15 not allowed here -- `vrmlaldavhax.s32 r0,pc,q2,q3'
+[^:]*:43: Error: Odd register not allowed here -- `vrmlalvh.s32 r1,r1,q2,q3'
+[^:]*:44: Error: Even register not allowed here -- `vrmlalvh.s32 r0,r0,q2,q3'
+[^:]*:45: Error: r13 not allowed here -- `vrmlalvh.s32 r0,sp,q2,q3'
+[^:]*:46: Error: r15 not allowed here -- `vrmlalvh.s32 r0,pc,q2,q3'
+[^:]*:47: Error: Odd register not allowed here -- `vrmlalvha.s32 r1,r1,q2,q3'
+[^:]*:48: Error: Even register not allowed here -- `vrmlalvha.s32 r0,r0,q2,q3'
+[^:]*:49: Error: r13 not allowed here -- `vrmlalvha.s32 r0,sp,q2,q3'
+[^:]*:50: Error: r15 not allowed here -- `vrmlalvha.s32 r0,pc,q2,q3'
+[^:]*:52: Error: Odd register not allowed here -- `vrmlsldavh.s32 r1,r1,q2,q3'
+[^:]*:53: Error: Even register not allowed here -- `vrmlsldavh.s32 r0,r0,q2,q3'
+[^:]*:54: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:55: Error: r15 not allowed here -- `vrmlsldavh.s32 r0,pc,q2,q3'
+[^:]*:56: Error: Odd register not allowed here -- `vrmlsldavha.s32 r1,r1,q2,q3'
+[^:]*:57: Error: Even register not allowed here -- `vrmlsldavha.s32 r0,r0,q2,q3'
+[^:]*:58: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:59: Error: r15 not allowed here -- `vrmlsldavha.s32 r0,pc,q2,q3'
+[^:]*:60: Error: Odd register not allowed here -- `vrmlsldavhx.s32 r1,r1,q2,q3'
+[^:]*:61: Error: Even register not allowed here -- `vrmlsldavhx.s32 r0,r0,q2,q3'
+[^:]*:62: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:63: Error: r15 not allowed here -- `vrmlsldavhx.s32 r0,pc,q2,q3'
+[^:]*:64: Error: Odd register not allowed here -- `vrmlsldavhax.s32 r1,r1,q2,q3'
+[^:]*:65: Error: Even register not allowed here -- `vrmlsldavhax.s32 r0,r0,q2,q3'
+[^:]*:66: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:67: Error: r15 not allowed here -- `vrmlsldavhax.s32 r0,pc,q2,q3'
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:81: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3'
 [^:]*:82: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3'
 [^:]*:84: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3'
--- a/gas/testsuite/gas/arm/mve-vrmlaldavh-bad.s
+++ b/gas/testsuite/gas/arm/mve-vrmlaldavh-bad.s
@@ -1,12 +1,7 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s32 r0, r1, q2, q3
-.endr
-.endm
 
 .syntax unified
 .thumb
+
 vrmlaldavh.s16 r0, r1, q2, q3
 vrmlaldavh.i32 r0, r1, q2, q3
 vrmlaldavha.s16 r0, r1, q2, q3
@@ -19,6 +14,7 @@ vrmlaldavhx.u32 r0, r1, q2, q3
 vrmlaldavhax.u32 r0, r1, q2, q3
 vrmlaldavhx.i32 r0, r1, q2, q3
 vrmlaldavhax.i32 r0, r1, q2, q3
+
 vrmlsldavh.s16 r0, r1, q2, q3
 vrmlsldavh.u32 r0, r1, q2, q3
 vrmlsldavha.s16 r0, r1, q2, q3
@@ -27,6 +23,7 @@ vrmlsldavhx.s16 r0, r1, q2, q3
 vrmlsldavhx.u32 r0, r1, q2, q3
 vrmlsldavhax.s16 r0, r1, q2, q3
 vrmlsldavhax.u32 r0, r1, q2, q3
+
 vrmlaldavh.s32 r1, r1, q2, q3
 vrmlaldavh.s32 r0, r0, q2, q3
 vrmlaldavh.s32 r0, sp, q2, q3
@@ -51,6 +48,7 @@ vrmlalvha.s32 r1, r1, q2, q3
 vrmlalvha.s32 r0, r0, q2, q3
 vrmlalvha.s32 r0, sp, q2, q3
 vrmlalvha.s32 r0, pc, q2, q3
+
 vrmlsldavh.s32 r1, r1, q2, q3
 vrmlsldavh.s32 r0, r0, q2, q3
 vrmlsldavh.s32 r0, sp, q2, q3
@@ -67,16 +65,18 @@ vrmlsldavhax.s32 r1, r1, q2, q3
 vrmlsldavhax.s32 r0, r0, q2, q3
 vrmlsldavhax.s32 r0, sp, q2, q3
 vrmlsldavhax.s32 r0, pc, q2, q3
-cond vrmlaldavh
-cond vrmlaldavha
-cond vrmlaldavhx
-cond vrmlaldavhax
-cond vrmlalvh
-cond vrmlalvha
-cond vrmlsldavh
-cond vrmlsldavha
-cond vrmlsldavhx
-cond vrmlsldavhax
+
+.irp op, vrmlaldavh, vrmlaldavha, vrmlaldavhx, vrmlaldavhax, vrmlalvh, vrmlalvha, vrmlsldavh, vrmlsldavha, vrmlsldavhx, vrmlsldavhax
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+\op\().s32 r0, r1, q2, q3
+
+.endr
+
+.endr
+
 it eq
 vrmlaldavheq.s32 r0, r1, q2, q3
 vrmlaldavheq.s32 r0, r1, q2, q3
--- a/gas/testsuite/gas/arm/mve-vrshl-bad.l
+++ b/gas/testsuite/gas/arm/mve-vrshl-bad.l
@@ -1,22 +1,22 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vrshl.i16 q0,q1,q2'
-[^:]*:11: Error: bad type in SIMD instruction -- `vrshl.i16 q0,r2'
-[^:]*:12: Error: bad type in SIMD instruction -- `vrshl.s64 q0,q1,q2'
-[^:]*:13: Error: bad type in SIMD instruction -- `vrshl.s64 q0,r2'
-[^:]*:14: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:15: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vrshl.i16 q0,q1,q2'
+[^:]*:5: Error: bad type in SIMD instruction -- `vrshl.i16 q0,r2'
+[^:]*:6: Error: bad type in SIMD instruction -- `vrshl.s64 q0,q1,q2'
+[^:]*:7: Error: bad type in SIMD instruction -- `vrshl.s64 q0,r2'
+[^:]*:8: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:9: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:19: Error: syntax error -- `vrshleq.s32 q0,q1,q2'
 [^:]*:20: Error: syntax error -- `vrshleq.s32 q0,q1,q2'
 [^:]*:22: Error: syntax error -- `vrshleq.s32 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vrshl-bad.s
+++ b/gas/testsuite/gas/arm/mve-vrshl-bad.s
@@ -1,20 +1,20 @@
-.macro cond lastreg
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vrshl.s32 q0, q0, \lastreg
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vrshl.i16 q0, q1, q2
 vrshl.i16 q0, r2
 vrshl.s64 q0, q1, q2
 vrshl.s64 q0, r2
 vrshl.s32 q0, sp
 vrshl.s32 q0, pc
-cond q2
-cond r2
+
+.irp lastreg, q2, r2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vrshl.s32 q0, q0, \lastreg
+.endr
+.endr
+
 it eq
 vrshleq.s32 q0, q1, q2
 vrshleq.s32 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vsbc-bad.l
+++ b/gas/testsuite/gas/arm/mve-vsbc-bad.l
@@ -1,18 +1,18 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vsbc.i16 q0,q1,q2'
-[^:]*:11: Error: bad type in SIMD instruction -- `vsbci.i16 q0,q1,q2'
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vsbc.i16 q0,q1,q2'
+[^:]*:5: Error: bad type in SIMD instruction -- `vsbci.i16 q0,q1,q2'
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:15: Error: syntax error -- `vsbceq.i32 q0,q1,q2'
 [^:]*:16: Error: syntax error -- `vsbceq.i32 q0,q1,q2'
 [^:]*:18: Error: syntax error -- `vsbceq.i32 q0,q1,q2'
--- a/gas/testsuite/gas/arm/mve-vsbc-bad.s
+++ b/gas/testsuite/gas/arm/mve-vsbc-bad.s
@@ -1,16 +1,16 @@
-.macro cond op
+.syntax unified
+.thumb
+
+vsbc.i16 q0, q1, q2
+vsbci.i16 q0, q1, q2
+
+.irp op, vsbc, vsbci
 .irp cond, eq, ne, gt, ge, lt, le
 it \cond
 \op\().i32 q0, q1, q2
 .endr
-.endm
+.endr
 
-.syntax unified
-.thumb
-vsbc.i16 q0, q1, q2
-vsbci.i16 q0, q1, q2
-cond vsbc
-cond vsbci
 it eq
 vsbceq.i32 q0, q1, q2
 vsbceq.i32 q0, q1, q2
--- a/gas/testsuite/gas/arm/mve-vshlc-bad.l
+++ b/gas/testsuite/gas/arm/mve-vshlc-bad.l
@@ -1,14 +1,14 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: immediate value out of range -- `vshlc q0,r1,#0'
-[^:]*:11: Error: immediate value out of range -- `vshlc q0,r1,#33'
-[^:]*:12: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:13: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: immediate value out of range -- `vshlc q0,r1,#0'
+[^:]*:4: Error: immediate value out of range -- `vshlc q0,r1,#33'
+[^:]*:5: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:6: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:16: Error: syntax error -- `vshlceq q0,r1,#2'
 [^:]*:17: Error: syntax error -- `vshlceq q0,r1,#2'
 [^:]*:19: Error: syntax error -- `vshlceq q0,r1,#2'
--- a/gas/testsuite/gas/arm/mve-vshlc-bad.s
+++ b/gas/testsuite/gas/arm/mve-vshlc-bad.s
@@ -1,17 +1,17 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vshlc q0, r1, #2
-.endr
-.endm
-
 .syntax unified
 .thumb
 vshlc q0, r1, #0
 vshlc q0, r1, #33
 vshlc q0, sp, #1
 vshlc q0, pc, #1
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vshlc q0, r1, #2
+
+.endr
+
 it eq
 vshlceq q0, r1, #2
 vshlceq q0, r1, #2
--- a/gas/testsuite/gas/arm/mve-vshll-bad.l
+++ b/gas/testsuite/gas/arm/mve-vshll-bad.l
@@ -1,28 +1,28 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vshllt.s32 q0,q1,#1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vshllt.i8 q0,q1,#1'
-[^:]*:12: Error: immediate value out of range -- `vshllt.u8 q0,q1,#0'
-[^:]*:13: Error: immediate value out of range -- `vshllt.u8 q0,q1,#9'
-[^:]*:14: Error: immediate value out of range -- `vshllt.s16 q0,q1,#0'
-[^:]*:15: Error: immediate value out of range -- `vshllt.s16 q0,q1,#17'
-[^:]*:16: Error: bad type in SIMD instruction -- `vshllb.s32 q0,q1,#1'
-[^:]*:17: Error: bad type in SIMD instruction -- `vshllb.i8 q0,q1,#1'
-[^:]*:18: Error: immediate value out of range -- `vshllb.u8 q0,q1,#0'
-[^:]*:19: Error: immediate value out of range -- `vshllb.u8 q0,q1,#9'
-[^:]*:20: Error: immediate value out of range -- `vshllb.s16 q0,q1,#0'
-[^:]*:21: Error: immediate value out of range -- `vshllb.s16 q0,q1,#17'
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vshllt.s32 q0,q1,#1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vshllt.i8 q0,q1,#1'
+[^:]*:6: Error: immediate value out of range -- `vshllt.u8 q0,q1,#0'
+[^:]*:7: Error: immediate value out of range -- `vshllt.u8 q0,q1,#9'
+[^:]*:8: Error: immediate value out of range -- `vshllt.s16 q0,q1,#0'
+[^:]*:9: Error: immediate value out of range -- `vshllt.s16 q0,q1,#17'
+[^:]*:10: Error: bad type in SIMD instruction -- `vshllb.s32 q0,q1,#1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vshllb.i8 q0,q1,#1'
+[^:]*:12: Error: immediate value out of range -- `vshllb.u8 q0,q1,#0'
+[^:]*:13: Error: immediate value out of range -- `vshllb.u8 q0,q1,#9'
+[^:]*:14: Error: immediate value out of range -- `vshllb.s16 q0,q1,#0'
+[^:]*:15: Error: immediate value out of range -- `vshllb.s16 q0,q1,#17'
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:25: Error: syntax error -- `vshllteq.s8 q0,q1,#1'
 [^:]*:26: Error: syntax error -- `vshllteq.s8 q0,q1,#1'
 [^:]*:28: Error: syntax error -- `vshllteq.s8 q0,q1,#1'
--- a/gas/testsuite/gas/arm/mve-vshll-bad.s
+++ b/gas/testsuite/gas/arm/mve-vshll-bad.s
@@ -1,12 +1,6 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s16 q0, q1, #4
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vshllt.s32 q0, q1, #1
 vshllt.i8 q0, q1, #1
 vshllt.u8 q0, q1, #0
@@ -19,8 +13,14 @@ vshllb.u8 q0, q1, #0
 vshllb.u8 q0, q1, #9
 vshllb.s16 q0, q1, #0
 vshllb.s16 q0, q1, #17
-cond vshllt
-cond vshllb
+
+.irp op, vshllt, vshllb
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s16 q0, q1, #4
+.endr
+.endr
+
 it eq
 vshllteq.s8 q0, q1, #1
 vshllteq.s8 q0, q1, #1
--- a/gas/testsuite/gas/arm/mve-vshr-bad.l
+++ b/gas/testsuite/gas/arm/mve-vshr-bad.l
@@ -1,26 +1,26 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vshr.s64 q0,q1,#1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vshr.i32 q0,q1,#1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vrshr.u64 q0,q1,#1'
-[^:]*:13: Error: bad type in SIMD instruction -- `vrshr.i32 q0,q1,#1'
-[^:]*:14: Error: immediate out of range for shift -- `vshr.s8 q0,q1,#9'
-[^:]*:15: Error: immediate out of range for shift -- `vshr.u8 q0,q1,#9'
-[^:]*:16: Error: immediate out of range for shift -- `vshr.s16 q0,q1,#17'
-[^:]*:17: Error: immediate out of range for shift -- `vshr.u16 q0,q1,#17'
-[^:]*:18: Error: immediate out of range for shift -- `vshr.s32 q0,q1,#33'
-[^:]*:19: Error: immediate out of range for shift -- `vshr.u32 q0,q1,#33'
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vshr.s64 q0,q1,#1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vshr.i32 q0,q1,#1'
+[^:]*:6: Error: bad type in SIMD instruction -- `vrshr.u64 q0,q1,#1'
+[^:]*:7: Error: bad type in SIMD instruction -- `vrshr.i32 q0,q1,#1'
+[^:]*:8: Error: immediate out of range for shift -- `vshr.s8 q0,q1,#9'
+[^:]*:9: Error: immediate out of range for shift -- `vshr.u8 q0,q1,#9'
+[^:]*:10: Error: immediate out of range for shift -- `vshr.s16 q0,q1,#17'
+[^:]*:11: Error: immediate out of range for shift -- `vshr.u16 q0,q1,#17'
+[^:]*:12: Error: immediate out of range for shift -- `vshr.s32 q0,q1,#33'
+[^:]*:13: Error: immediate out of range for shift -- `vshr.u32 q0,q1,#33'
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:23: Error: syntax error -- `vshreq.s32 q0,q1,#1'
 [^:]*:24: Error: syntax error -- `vshreq.s32 q0,q1,#1'
 [^:]*:26: Error: syntax error -- `vshreq.s32 q0,q1,#1'
--- a/gas/testsuite/gas/arm/mve-vshr-bad.s
+++ b/gas/testsuite/gas/arm/mve-vshr-bad.s
@@ -1,12 +1,6 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().s32 q0, q1, #1
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vshr.s64 q0, q1, #1
 vshr.i32 q0, q1, #1
 vrshr.u64 q0, q1, #1
@@ -17,8 +11,14 @@ vshr.s16 q0, q1, #17
 vshr.u16 q0, q1, #17
 vshr.s32 q0, q1, #33
 vshr.u32 q0, q1, #33
-cond vshr
-cond vrshr
+
+.irp op, vshr, vrshr
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s32 q0, q1, #1
+.endr
+.endr
+
 it eq
 vshreq.s32 q0, q1, #1
 vshreq.s32 q0, q1, #1
--- a/gas/testsuite/gas/arm/mve-vshrn-bad.l
+++ b/gas/testsuite/gas/arm/mve-vshrn-bad.l
@@ -1,40 +1,40 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vshrnt.i64 q0,q1,#1'
-[^:]*:11: Error: bad type in SIMD instruction -- `vshrnb.i64 q0,q1,#1'
-[^:]*:12: Error: bad type in SIMD instruction -- `vrshrnt.i64 q0,q1,#1'
-[^:]*:13: Error: bad type in SIMD instruction -- `vrshrnb.i64 q0,q1,#1'
-[^:]*:14: Error: immediate operand expected in the range \[1,8\] -- `vshrnt.i16 q0,q1,#0'
-[^:]*:15: Error: immediate operand expected in the range \[1,8\] -- `vshrnt.i16 q0,q1,#9'
-[^:]*:16: Error: immediate operand expected in the range \[1,16\] -- `vshrnt.i32 q0,q1,#0'
-[^:]*:17: Error: immediate operand expected in the range \[1,16\] -- `vshrnt.i32 q0,q1,#17'
-[^:]*:18: Error: immediate operand expected in the range \[1,8\] -- `vshrnb.i16 q0,q1,#0'
-[^:]*:19: Error: immediate operand expected in the range \[1,8\] -- `vshrnb.i16 q0,q1,#9'
-[^:]*:20: Error: immediate operand expected in the range \[1,16\] -- `vshrnb.i32 q0,q1,#0'
-[^:]*:21: Error: immediate operand expected in the range \[1,16\] -- `vshrnb.i32 q0,q1,#17'
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Error: bad type in SIMD instruction -- `vshrnt.i64 q0,q1,#1'
+[^:]*:5: Error: bad type in SIMD instruction -- `vshrnb.i64 q0,q1,#1'
+[^:]*:6: Error: bad type in SIMD instruction -- `vrshrnt.i64 q0,q1,#1'
+[^:]*:7: Error: bad type in SIMD instruction -- `vrshrnb.i64 q0,q1,#1'
+[^:]*:8: Error: immediate operand expected in the range \[1,8\] -- `vshrnt.i16 q0,q1,#0'
+[^:]*:9: Error: immediate operand expected in the range \[1,8\] -- `vshrnt.i16 q0,q1,#9'
+[^:]*:10: Error: immediate operand expected in the range \[1,16\] -- `vshrnt.i32 q0,q1,#0'
+[^:]*:11: Error: immediate operand expected in the range \[1,16\] -- `vshrnt.i32 q0,q1,#17'
+[^:]*:12: Error: immediate operand expected in the range \[1,8\] -- `vshrnb.i16 q0,q1,#0'
+[^:]*:13: Error: immediate operand expected in the range \[1,8\] -- `vshrnb.i16 q0,q1,#9'
+[^:]*:14: Error: immediate operand expected in the range \[1,16\] -- `vshrnb.i32 q0,q1,#0'
+[^:]*:15: Error: immediate operand expected in the range \[1,16\] -- `vshrnb.i32 q0,q1,#17'
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:27: Error: syntax error -- `vshrnteq.i32 q0,q1,#1'
 [^:]*:28: Error: syntax error -- `vshrnteq.i32 q0,q1,#1'
 [^:]*:30: Error: syntax error -- `vshrnteq.i32 q0,q1,#1'
--- a/gas/testsuite/gas/arm/mve-vshrn-bad.s
+++ b/gas/testsuite/gas/arm/mve-vshrn-bad.s
@@ -1,12 +1,6 @@
-.macro cond op
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-\op\().i32 q0, q1, #1
-.endr
-.endm
-
 .syntax unified
 .thumb
+
 vshrnt.i64 q0, q1, #1
 vshrnb.i64 q0, q1, #1
 vrshrnt.i64 q0, q1, #1
@@ -19,10 +13,16 @@ vshrnb.i16 q0, q1, #0
 vshrnb.i16 q0, q1, #9
 vshrnb.i32 q0, q1, #0
 vshrnb.i32 q0, q1, #17
-cond vshrnt
-cond vshrnb
-cond vrshrnt
-cond vrshrnb
+
+.irp op, vshrnt, vshrnb, vrshrnt, vrshrnb
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+\op\().i32 q0, q1, #1
+
+.endr
+.endr
+
 it eq
 vshrnteq.i32 q0, q1, #1
 vshrnteq.i32 q0, q1, #1
--- a/gas/testsuite/gas/arm/mve-vsli-bad.l
+++ b/gas/testsuite/gas/arm/mve-vsli-bad.l
@@ -1,14 +1,14 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vsli.64 q0,q1,#1'
-[^:]*:11: Error: immediate out of range for insert -- `vsli.8 q0,q1,#8'
-[^:]*:12: Error: immediate out of range for insert -- `vsli.16 q0,q1,#16'
-[^:]*:13: Error: immediate out of range for insert -- `vsli.32 q0,q1,#32'
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vsli.64 q0,q1,#1'
+[^:]*:4: Error: immediate out of range for insert -- `vsli.8 q0,q1,#8'
+[^:]*:5: Error: immediate out of range for insert -- `vsli.16 q0,q1,#16'
+[^:]*:6: Error: immediate out of range for insert -- `vsli.32 q0,q1,#32'
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:16: Error: syntax error -- `vslieq.8 q0,q1,#2'
 [^:]*:17: Error: syntax error -- `vslieq.8 q0,q1,#2'
 [^:]*:19: Error: syntax error -- `vslieq.8 q0,q1,#2'
--- a/gas/testsuite/gas/arm/mve-vsli-bad.s
+++ b/gas/testsuite/gas/arm/mve-vsli-bad.s
@@ -1,17 +1,17 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vsli.16 q0, q1, #4
-.endr
-.endm
-
 .syntax unified
 .thumb
 vsli.64 q0, q1, #1
 vsli.8 q0, q1, #8
 vsli.16 q0, q1, #16
 vsli.32 q0, q1, #32
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vsli.16 q0, q1, #4
+
+.endr
+
 it eq
 vslieq.8 q0, q1, #2
 vslieq.8 q0, q1, #2
--- a/gas/testsuite/gas/arm/mve-vsri-bad.l
+++ b/gas/testsuite/gas/arm/mve-vsri-bad.l
@@ -1,17 +1,17 @@
 [^:]*: Assembler messages:
-[^:]*:10: Error: bad type in SIMD instruction -- `vsri.64 q0,q1,#1'
-[^:]*:11: Error: immediate out of range for insert -- `vsri.8 q0,q1,#0'
-[^:]*:12: Error: immediate out of range for insert -- `vsri.8 q0,q1,#9'
-[^:]*:13: Error: immediate out of range for insert -- `vsri.16 q0,q1,#0'
-[^:]*:14: Error: immediate out of range for insert -- `vsri.16 q0,q1,#17'
-[^:]*:15: Error: immediate out of range for insert -- `vsri.32 q0,q1,#0'
-[^:]*:16: Error: immediate out of range for insert -- `vsri.32 q0,q1,#33'
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:3: Error: bad type in SIMD instruction -- `vsri.64 q0,q1,#1'
+[^:]*:4: Error: immediate out of range for insert -- `vsri.8 q0,q1,#0'
+[^:]*:5: Error: immediate out of range for insert -- `vsri.8 q0,q1,#9'
+[^:]*:6: Error: immediate out of range for insert -- `vsri.16 q0,q1,#0'
+[^:]*:7: Error: immediate out of range for insert -- `vsri.16 q0,q1,#17'
+[^:]*:8: Error: immediate out of range for insert -- `vsri.32 q0,q1,#0'
+[^:]*:9: Error: immediate out of range for insert -- `vsri.32 q0,q1,#33'
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
 [^:]*:19: Error: syntax error -- `vsrieq.8 q0,q1,#2'
 [^:]*:20: Error: syntax error -- `vsrieq.8 q0,q1,#2'
 [^:]*:22: Error: syntax error -- `vsrieq.8 q0,q1,#2'
--- a/gas/testsuite/gas/arm/mve-vsri-bad.s
+++ b/gas/testsuite/gas/arm/mve-vsri-bad.s
@@ -1,10 +1,3 @@
-.macro cond
-.irp cond, eq, ne, gt, ge, lt, le
-it \cond
-vsri.16 q0, q1, #4
-.endr
-.endm
-
 .syntax unified
 .thumb
 vsri.64 q0, q1, #1
@@ -14,7 +7,14 @@ vsri.16 q0, q1, #0
 vsri.16 q0, q1, #17
 vsri.32 q0, q1, #0
 vsri.32 q0, q1, #33
-cond
+
+.irp cond, eq, ne, gt, ge, lt, le
+
+it \cond
+vsri.16 q0, q1, #4
+
+.endr
+
 it eq
 vsrieq.8 q0, q1, #2
 vsrieq.8 q0, q1, #2
--- a/gas/testsuite/gas/arm/sp-usage-thumb2-relax.s
+++ b/gas/testsuite/gas/arm/sp-usage-thumb2-relax.s
@@ -1,27 +1,17 @@
-	.macro iter_addsub
+	.syntax unified
+	.text
+	.thumb
+	.global foo
+foo:
 	.irp m, add.w, sub.w, addw, subw
 	   \m sp, r7, #1
 	.endr
-	.endm
 
-	.macro iter_arith3
 	.irp m, bic, sbcs, and, eor
 	   \m r7, sp, r2
 	.endr
-	.endm
 
-	.macro iter_mla
-	.irp m, smlabb, smlatb, smlabt, smlabt
+	.irp m, smlabb, smlatb, smlabt, smlatt
 	   \m sp, sp, sp, sp
 	   \m r0, sp, r3, r11
 	.endr
-	.endm
-
-	.syntax unified
-	.text
-	.thumb
-	.global foo
-foo:
-	iter_addsub
-	iter_arith3
-	iter_mla
--- a/gas/testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l
+++ b/gas/testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l
@@ -1,17 +1,17 @@
 [^:]*: Assembler messages:
-[^:]*:25: Error: r13 not allowed here -- `add.w sp,r7,#1'
-[^:]*:25: Error: r13 not allowed here -- `sub.w sp,r7,#1'
-[^:]*:25: Error: r13 not allowed here -- `addw sp,r7,#1'
-[^:]*:25: Error: r13 not allowed here -- `subw sp,r7,#1'
-[^:]*:26: Error: r13 not allowed here -- `bic r7,sp,r2'
-[^:]*:26: Error: r13 not allowed here -- `sbcs r7,sp,r2'
-[^:]*:26: Error: r13 not allowed here -- `and r7,sp,r2'
-[^:]*:26: Error: r13 not allowed here -- `eor r7,sp,r2'
-[^:]*:27: Error: r13 not allowed here -- `smlabb sp,sp,sp,sp'
-[^:]*:27: Error: r13 not allowed here -- `smlabb r0,sp,r3,r11'
-[^:]*:27: Error: r13 not allowed here -- `smlatb sp,sp,sp,sp'
-[^:]*:27: Error: r13 not allowed here -- `smlatb r0,sp,r3,r11'
-[^:]*:27: Error: r13 not allowed here -- `smlabt sp,sp,sp,sp'
-[^:]*:27: Error: r13 not allowed here -- `smlabt r0,sp,r3,r11'
-[^:]*:27: Error: r13 not allowed here -- `smlabt sp,sp,sp,sp'
-[^:]*:27: Error: r13 not allowed here -- `smlabt r0,sp,r3,r11'
+[^:]*:7: Error: r13 not allowed here -- `add.w sp,r7,#1'
+[^:]*:7: Error: r13 not allowed here -- `sub.w sp,r7,#1'
+[^:]*:7: Error: r13 not allowed here -- `addw sp,r7,#1'
+[^:]*:7: Error: r13 not allowed here -- `subw sp,r7,#1'
+[^:]*:11: Error: r13 not allowed here -- `bic r7,sp,r2'
+[^:]*:11: Error: r13 not allowed here -- `sbcs r7,sp,r2'
+[^:]*:11: Error: r13 not allowed here -- `and r7,sp,r2'
+[^:]*:11: Error: r13 not allowed here -- `eor r7,sp,r2'
+[^:]*:15: Error: r13 not allowed here -- `smlabb sp,sp,sp,sp'
+[^:]*:16: Error: r13 not allowed here -- `smlabb r0,sp,r3,r11'
+[^:]*:15: Error: r13 not allowed here -- `smlatb sp,sp,sp,sp'
+[^:]*:16: Error: r13 not allowed here -- `smlatb r0,sp,r3,r11'
+[^:]*:15: Error: r13 not allowed here -- `smlabt sp,sp,sp,sp'
+[^:]*:16: Error: r13 not allowed here -- `smlabt r0,sp,r3,r11'
+[^:]*:15: Error: r13 not allowed here -- `smlatt sp,sp,sp,sp'
+[^:]*:16: Error: r13 not allowed here -- `smlatt r0,sp,r3,r11'
--- a/gas/testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d
+++ b/gas/testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d
@@ -21,5 +21,5 @@ Disassembly of section \.text:
 .*:	fb1d b023 	smlatb	r0, sp, r3, fp
 .*:	fb1d dd1d 	smlabt	sp, sp, sp, sp
 .*:	fb1d b013 	smlabt	r0, sp, r3, fp
-.*:	fb1d dd1d 	smlabt	sp, sp, sp, sp
-.*:	fb1d b013 	smlabt	r0, sp, r3, fp
+.*:	fb1d dd3d 	smlatt	sp, sp, sp, sp
+.*:	fb1d b033 	smlatt	r0, sp, r3, fp

[PATCH v2 2/2] gas: re-work line number tracking for macros and their expansions

[Jan Beulich]

[-- Attachment #1: Type: text/plain, Size: 15761 bytes --]

The PR gas/16908 workaround aimed at uniformly reporting line numbers
to reference macro invocation sites. As mentioned in a comment this may
be desirable for small macros, but often isn't for larger ones. As a
first step improve diagnostics to report both locations, while aiming at
leaving generated debug info unaltered.

Note that macro invocation context is lost for any diagnostics issued
only after all input was processed (or more generally for any use of
as_*_where(), as the functions can't know whether the passed in location
is related to [part of] the present stack of locations). To maintain the
intended workaround behavior for PR gas/16908, a new as_where() is
introduced to "look through" macro invocations, while the existing
as_where() is renamed (and used in only very few places for now). Down
the road as_where() will likely want to return a list of (file,line)
pairs.
---
v2: Fully cover Arm testsuite.
---
Omitting testsuite adjustments from the inline patch, for its sheer size;
please see the attachment for the full (compressed) patch.
---
Adding

      if (subseg_text_p (now_seg))
	dwarf2_emit_insn (0);

to try_macro() (alongside using as_where_top() in dwarf2_where()) would
get .debug_line contents into reasonable shape (expressing both macro
invocation site and macro definition location). But that's likely
insufficient: We may want / need to represent macros as inline
subprograms and their expansions as inlined subroutines. Which in turn
looks cumbersome especially with the relatively recently added recording
of functions (with which macro expansions then would better be
associated, when marked as such).

--- a/gas/as.h
+++ b/gas/as.h
@@ -437,6 +437,10 @@ typedef struct _pseudo_type pseudo_typeS
 #define PRINTF_WHERE_LIKE(FCN) \
   void FCN (const char *file, unsigned int line, const char *format, ...) \
     __attribute__ ((__format__ (__printf__, 3, 4)))
+#define PRINTF_INDENT_LIKE(FCN) \
+  void FCN (const char *file, unsigned int line, unsigned int indent, \
+	    const char *format, ...) \
+    __attribute__ ((__format__ (__printf__, 4, 5)))
 
 #else /* __GNUC__ < 2 || defined(VMS) */
 
@@ -444,6 +448,10 @@ typedef struct _pseudo_type pseudo_typeS
 #define PRINTF_WHERE_LIKE(FCN)	void FCN (const char *file, \
 					  unsigned int line, \
 					  const char *format, ...)
+#define PRINTF_INDENT_LIKE(FCN)	void FCN (const char *file, \
+					  unsigned int line, \
+					  unsigned int indent, \
+					  const char *format, ...)
 
 #endif /* __GNUC__ < 2 || defined(VMS) */
 
@@ -453,6 +461,7 @@ PRINTF_LIKE (as_tsktsk);
 PRINTF_LIKE (as_warn);
 PRINTF_WHERE_LIKE (as_bad_where);
 PRINTF_WHERE_LIKE (as_warn_where);
+PRINTF_INDENT_LIKE (as_info_where);
 
 void   as_abort (const char *, int, const char *) ATTRIBUTE_NORETURN;
 void   signal_init (void);
@@ -487,7 +496,9 @@ void   cond_finish_check (int);
 void   cond_exit_macro (int);
 int    seen_at_least_1_file (void);
 void   app_pop (char *);
+void   as_report_context (void);
 const char * as_where (unsigned int *);
+const char * as_where_top (unsigned int *);
 const char * as_where_physical (unsigned int *);
 void   bump_line_counters (void);
 void   do_scrub_begin (int);
--- a/gas/input-scrub.c
+++ b/gas/input-scrub.c
@@ -104,6 +104,9 @@ static const char *logical_input_file;
 static unsigned int physical_input_line;
 static unsigned int logical_input_line;
 
+/* Indicator whether the origin of an update was a .linefile directive. */
+static bool is_linefile;
+
 /* Struct used to save the state of the input handler during include files */
 struct input_save {
   char *              buffer_start;
@@ -115,6 +118,7 @@ struct input_save {
   const char *        logical_input_file;
   unsigned int        physical_input_line;
   unsigned int        logical_input_line;
+  bool                is_linefile;
   size_t              sb_index;
   sb                  from_sb;
   enum expansion      from_sb_expansion; /* Should we do a conditional check?  */
@@ -166,6 +170,7 @@ input_scrub_push (char *saved_position)
   saved->logical_input_file = logical_input_file;
   saved->physical_input_line = physical_input_line;
   saved->logical_input_line = logical_input_line;
+  saved->is_linefile = is_linefile;
   saved->sb_index = sb_index;
   saved->from_sb = from_sb;
   saved->from_sb_expansion = from_sb_expansion;
@@ -193,6 +198,7 @@ input_scrub_pop (struct input_save *save
   logical_input_file = saved->logical_input_file;
   physical_input_line = saved->physical_input_line;
   logical_input_line = saved->logical_input_line;
+  is_linefile = saved->is_linefile;
   sb_index = saved->sb_index;
   from_sb = saved->from_sb;
   from_sb_expansion = saved->from_sb_expansion;
@@ -267,8 +273,6 @@ input_scrub_include_sb (sb *from, char *
     as_fatal (_("macros nested too deeply"));
   ++macro_nest;
 
-  gas_assert (expansion < expanding_nested);
-
 #ifdef md_macro_start
   if (expansion == expanding_macro)
     {
@@ -283,8 +287,6 @@ input_scrub_include_sb (sb *from, char *
      expansion.  */
   newline = from->len >= 1 && from->ptr[0] != '\n';
   sb_build (&from_sb, from->len + newline + 2 * sizeof (".linefile") + 30);
-  if (expansion == expanding_repeat && from_sb_expansion >= expanding_macro)
-    expansion = expanding_nested;
   from_sb_expansion = expansion;
   if (newline)
     {
@@ -437,10 +439,7 @@ bump_line_counters (void)
   if (sb_index == (size_t) -1)
     ++physical_input_line;
 
-  /* PR gas/16908 workaround: Don't bump logical line numbers while
-     expanding macros, unless file (and maybe line; see as_where()) are
-     used inside the macro.  */
-  if (logical_input_line != -1u && from_sb_expansion < expanding_macro)
+  if (logical_input_line != -1u)
     ++logical_input_line;
 }
 \f
@@ -471,10 +470,6 @@ new_logical_line_flags (const char *fnam
     case 1 << 3:
       if (line_number < 0 || fname != NULL)
 	abort ();
-      /* PR gas/16908 workaround: Ignore updates when nested inside a macro
-	 expansion.  */
-      if (from_sb_expansion == expanding_nested)
-	return;
       if (next_saved_file == NULL)
 	fname = physical_input_file;
       else if (next_saved_file->logical_input_file)
@@ -486,6 +481,8 @@ new_logical_line_flags (const char *fnam
       abort ();
     }
 
+  is_linefile = flags != 1 && (flags != 0 || fname);
+
   if (line_number >= 0)
     logical_input_line = line_number;
   else if (line_number == -1 && fname && !*fname && (flags & (1 << 2)))
@@ -499,15 +496,6 @@ new_logical_line_flags (const char *fnam
       && (logical_input_file == NULL
 	  || filename_cmp (logical_input_file, fname)))
     logical_input_file = fname;
-
-  /* When encountering file or line changes inside a macro, arrange for
-     bump_line_counters() to henceforth increment the logical line number
-     again, just like it does when expanding repeats.  See as_where() for
-     why changing file or line alone doesn't alter expansion mode.  */
-  if (from_sb_expansion == expanding_macro
-      && logical_input_file != NULL
-      && logical_input_line != -1u)
-    from_sb_expansion = expanding_repeat;
 }
 
 void
@@ -516,6 +504,33 @@ new_logical_line (const char *fname, int
   new_logical_line_flags (fname, line_number, 0);
 }
 
+void
+as_report_context (void)
+{
+  const struct input_save *saved = next_saved_file;
+  enum expansion expansion = from_sb_expansion;
+  int indent = 1;
+
+  if (!macro_nest)
+    return;
+
+  do
+    {
+      if (expansion != expanding_macro)
+	/* Nothing.  */;
+      else if (saved->logical_input_file != NULL
+	       && saved->logical_input_line != -1u)
+	as_info_where (saved->logical_input_file, saved->logical_input_line,
+		       indent, _("macro invoked from here"));
+      else
+	as_info_where (saved->physical_input_file, saved->physical_input_line,
+		       indent, _("macro invoked from here"));
+
+      expansion = saved->from_sb_expansion;
+      ++indent;
+    }
+  while ((saved = saved->next_saved_file) != NULL);
+}
 \f
 /* Return the current physical input file name and line number, if known  */
 
@@ -534,11 +549,53 @@ as_where_physical (unsigned int *linep)
   return NULL;
 }
 
-/* Return the current file name and line number.  */
+/* Return the file name and line number at the top most macro
+   invocation, unless .file / .line were used inside a macro.  */
 
 const char *
 as_where (unsigned int *linep)
 {
+  const char *file = as_where_top (linep);
+
+  if (macro_nest && is_linefile)
+    {
+      const struct input_save *saved = next_saved_file;
+      enum expansion expansion = from_sb_expansion;
+
+      do
+	{
+	  if (!saved->is_linefile)
+	    break;
+
+	  if (expansion != expanding_macro)
+	    /* Nothing.  */;
+	  else if (saved->logical_input_file != NULL
+		   && (linep == NULL || saved->logical_input_line != -1u))
+	    {
+	      if (linep != NULL)
+		*linep = saved->logical_input_line;
+	      file = saved->logical_input_file;
+	    }
+	  else if (saved->physical_input_file != NULL)
+	    {
+	      if (linep != NULL)
+		*linep = saved->physical_input_line;
+	      file = saved->physical_input_file;
+	    }
+
+	  expansion = saved->from_sb_expansion;
+	}
+      while ((saved = saved->next_saved_file) != NULL);
+    }
+
+  return file;
+}
+
+/* Return the current file name and line number.  */
+
+const char *
+as_where_top (unsigned int *linep)
+{
   if (logical_input_file != NULL
       && (linep == NULL || logical_input_line != -1u))
     {
@@ -549,4 +606,3 @@ as_where (unsigned int *linep)
 
   return as_where_physical (linep);
 }
-
--- a/gas/macro.c
+++ b/gas/macro.c
@@ -131,23 +131,21 @@ buffer_and_nest (const char *from, const
   else
     from_len = strlen (from);
 
-  /* Except for macros record the present source position, such that
-     diagnostics and debug info will be properly associated with the
-     respective original lines, rather than with the line of the ending
-     directive (TO).  */
-  if (from == NULL || strcasecmp (from, "MACRO") != 0)
-    {
-      unsigned int line;
-      char *linefile;
-
-      as_where (&line);
-      if (!flag_m68k_mri)
-	linefile = xasprintf ("\t.linefile %u .", line + 1);
-      else
-	linefile = xasprintf ("\tlinefile %u .", line + 1);
-      sb_add_string (ptr, linefile);
-      xfree (linefile);
-    }
+  /* Record the present source position, such that diagnostics and debug info
+     can be properly associated with the respective original lines, rather
+     than with the line of the ending directive (TO).  */
+  {
+    unsigned int line;
+    char *linefile;
+
+    as_where_top (&line);
+    if (!flag_m68k_mri)
+      linefile = xasprintf ("\t.linefile %u .", line + 1);
+    else
+      linefile = xasprintf ("\tlinefile %u .", line + 1);
+    sb_add_string (ptr, linefile);
+    xfree (linefile);
+  }
 
   while (more)
     {
@@ -249,14 +247,8 @@ buffer_and_nest (const char *from, const
 	    }
 
 	  /* PR gas/16908
-	     Apply and discard .linefile directives that appear within
-	     the macro.  For long macros, one might want to report the
-	     line number information associated with the lines within
-	     the macro definition, but we would need more infrastructure
-	     to make that happen correctly (e.g. resetting the line
-	     number when expanding the macro), and since for short
-	     macros we clearly prefer reporting the point of expansion
-	     anyway, there's not an obviously better fix here.  */
+	     Apply .linefile directives that appear within the macro, alongside
+	     keeping them for later expansion of the macro.  */
 	  if (from != NULL && strcasecmp (from, "MACRO") == 0
 	      && len >= 8 && strncasecmp (ptr->ptr + i, "linefile", 8) == 0)
 	    {
@@ -267,7 +259,6 @@ buffer_and_nest (const char *from, const
 	      s_linefile (0);
 	      restore_ilp ();
 	      ptr->ptr[ptr->len] = saved_eol_char;
-	      ptr->len = line_start;
 	    }
 	}
 
--- a/gas/messages.c
+++ b/gas/messages.c
@@ -18,6 +18,7 @@
    02110-1301, USA.  */
 
 #include "as.h"
+#include <limits.h>
 #include <signal.h>
 
 /* If the system doesn't provide strsignal, we get it defined in
@@ -119,7 +120,7 @@ as_show_where (void)
   const char *file;
   unsigned int line;
 
-  file = as_where (&line);
+  file = as_where_top (&line);
   identify (file);
   if (file)
     {
@@ -130,6 +131,25 @@ as_show_where (void)
     }
 }
 
+/* Send to stderr a string as information, with location data passed in.
+   Note that for now this is not intended for general use.  */
+
+void
+as_info_where (const char *file, unsigned int line, unsigned int indent,
+	       const char *format, ...)
+{
+  va_list args;
+  char buffer[2000];
+
+  gas_assert (file != NULL && line > 0 && indent <= INT_MAX);
+
+  va_start (args, format);
+  vsnprintf (buffer, sizeof (buffer), format, args);
+  va_end (args);
+  fprintf (stderr, "%s:%u: %*s%s%s\n",
+	   file, line, (int)indent, "", _("Info: "), buffer);
+}
+
 /* Send to stderr a string as a warning, and locate warning
    in input file(s).
    Please only use this for when we have some recovery action.
@@ -146,6 +166,7 @@ as_tsktsk (const char *format, ...)
   vfprintf (stderr, format, args);
   va_end (args);
   (void) putc ('\n', stderr);
+  as_report_context ();
 }
 
 /* The common portion of as_warn and as_warn_where.  */
@@ -153,10 +174,15 @@ as_tsktsk (const char *format, ...)
 static void
 as_warn_internal (const char *file, unsigned int line, char *buffer)
 {
+  bool context = false;
+
   ++warning_count;
 
   if (file == NULL)
-    file = as_where (&line);
+    {
+      file = as_where_top (&line);
+      context = true;
+    }
 
   identify (file);
   if (file)
@@ -168,6 +194,10 @@ as_warn_internal (const char *file, unsi
     }
   else
     fprintf (stderr, "%s%s\n", _("Warning: "), buffer);
+
+  if (context)
+    as_report_context ();
+
 #ifndef NO_LISTING
   listing_warning (buffer);
 #endif
@@ -194,7 +224,7 @@ as_warn (const char *format, ...)
     }
 }
 
-/* Like as_bad but the file name and line number are passed in.
+/* Like as_warn but the file name and line number are passed in.
    Unfortunately, we have to repeat the function in order to handle
    the varargs correctly and portably.  */
 
@@ -218,10 +248,15 @@ as_warn_where (const char *file, unsigne
 static void
 as_bad_internal (const char *file, unsigned int line, char *buffer)
 {
+  bool context = false;
+
   ++error_count;
 
   if (file == NULL)
-    file = as_where (&line);
+    {
+      file = as_where_top (&line);
+      context = true;
+    }
 
   identify (file);
   if (file)
@@ -233,6 +268,10 @@ as_bad_internal (const char *file, unsig
     }
   else
     fprintf (stderr, "%s%s\n", _("Error: "), buffer);
+
+  if (context)
+    as_report_context ();
+
 #ifndef NO_LISTING
   listing_error (buffer);
 #endif
@@ -290,6 +329,7 @@ as_fatal (const char *format, ...)
   vfprintf (stderr, format, args);
   (void) putc ('\n', stderr);
   va_end (args);
+  as_report_context ();
   /* Delete the output file, if it exists.  This will prevent make from
      thinking that a file was created and hence does not need rebuilding.  */
   if (out_file_name != NULL)
@@ -312,6 +352,7 @@ as_abort (const char *file, int line, co
     fprintf (stderr, _("Internal error in %s at %s:%d.\n"), fn, file, line);
   else
     fprintf (stderr, _("Internal error at %s:%d.\n"), file, line);
+  as_report_context ();
 
   fprintf (stderr, _("Please report this bug.\n"));
 
--- a/gas/sb.h
+++ b/gas/sb.h
@@ -66,11 +66,9 @@ extern size_t sb_skip_comma (size_t, sb
 
 /* Actually in input-scrub.c.  */
 enum expansion {
-  /* Note: Order matters!  */
   expanding_none,
   expanding_repeat,
   expanding_macro,
-  expanding_nested, /* Only for internal use of input-scrub.c.  */
 };
 extern void input_scrub_include_sb (sb *, char *, enum expansion);
 

[-- Attachment #2: binutils-master-macro-location.patch.bz2 --]
[-- Type: application/octet-stream, Size: 28642 bytes --]

Re: [PATCH v2 2/2] gas: re-work line number tracking for macros and their expansions

[Luis Machado]

Hi,

I'm not yet sure how, but this patch has broken at least one gdb test (gdb.asm/asm-source.exp) for aarch64-linux (Ubuntu 22.04 and 20.04).

Could you please take a look at it? I can do some testing with the aarch64 machines if that's helpful.

FAIL: gdb.asm/asm-source.exp: f at main
FAIL: gdb.asm/asm-source.exp: n at main
FAIL: gdb.asm/asm-source.exp: next over macro
FAIL: gdb.asm/asm-source.exp: list
FAIL: gdb.asm/asm-source.exp: f in foo2
FAIL: gdb.asm/asm-source.exp: n in foo2
FAIL: gdb.asm/asm-source.exp: bt ALL in foo2
FAIL: gdb.asm/asm-source.exp: bt 2 in foo2
FAIL: gdb.asm/asm-source.exp: bt 3 in foo3
FAIL: gdb.asm/asm-source.exp: finish from foo3
FAIL: gdb.asm/asm-source.exp: info source asmsrc2.s
FAIL: gdb.asm/asm-source.exp: info line
FAIL: gdb.asm/asm-source.exp: next over foo3
FAIL: gdb.asm/asm-source.exp: return from foo2

                 === gdb Summary ===

# of expected passes            15
# of unexpected failures        14

On 12/9/22 10:52, Jan Beulich via Binutils wrote:
> The PR gas/16908 workaround aimed at uniformly reporting line numbers
> to reference macro invocation sites. As mentioned in a comment this may
> be desirable for small macros, but often isn't for larger ones. As a
> first step improve diagnostics to report both locations, while aiming at
> leaving generated debug info unaltered.
> 
> Note that macro invocation context is lost for any diagnostics issued
> only after all input was processed (or more generally for any use of
> as_*_where(), as the functions can't know whether the passed in location
> is related to [part of] the present stack of locations). To maintain the
> intended workaround behavior for PR gas/16908, a new as_where() is
> introduced to "look through" macro invocations, while the existing
> as_where() is renamed (and used in only very few places for now). Down
> the road as_where() will likely want to return a list of (file,line)
> pairs.
> ---
> v2: Fully cover Arm testsuite.
> ---
> Omitting testsuite adjustments from the inline patch, for its sheer size;
> please see the attachment for the full (compressed) patch.
> ---
> Adding
> 
>        if (subseg_text_p (now_seg))
> 	dwarf2_emit_insn (0);
> 
> to try_macro() (alongside using as_where_top() in dwarf2_where()) would
> get .debug_line contents into reasonable shape (expressing both macro
> invocation site and macro definition location). But that's likely
> insufficient: We may want / need to represent macros as inline
> subprograms and their expansions as inlined subroutines. Which in turn
> looks cumbersome especially with the relatively recently added recording
> of functions (with which macro expansions then would better be
> associated, when marked as such).
> 
> --- a/gas/as.h
> +++ b/gas/as.h
> @@ -437,6 +437,10 @@ typedef struct _pseudo_type pseudo_typeS
>   #define PRINTF_WHERE_LIKE(FCN) \
>     void FCN (const char *file, unsigned int line, const char *format, ...) \
>       __attribute__ ((__format__ (__printf__, 3, 4)))
> +#define PRINTF_INDENT_LIKE(FCN) \
> +  void FCN (const char *file, unsigned int line, unsigned int indent, \
> +	    const char *format, ...) \
> +    __attribute__ ((__format__ (__printf__, 4, 5)))
>   
>   #else /* __GNUC__ < 2 || defined(VMS) */
>   
> @@ -444,6 +448,10 @@ typedef struct _pseudo_type pseudo_typeS
>   #define PRINTF_WHERE_LIKE(FCN)	void FCN (const char *file, \
>   					  unsigned int line, \
>   					  const char *format, ...)
> +#define PRINTF_INDENT_LIKE(FCN)	void FCN (const char *file, \
> +					  unsigned int line, \
> +					  unsigned int indent, \
> +					  const char *format, ...)
>   
>   #endif /* __GNUC__ < 2 || defined(VMS) */
>   
> @@ -453,6 +461,7 @@ PRINTF_LIKE (as_tsktsk);
>   PRINTF_LIKE (as_warn);
>   PRINTF_WHERE_LIKE (as_bad_where);
>   PRINTF_WHERE_LIKE (as_warn_where);
> +PRINTF_INDENT_LIKE (as_info_where);
>   
>   void   as_abort (const char *, int, const char *) ATTRIBUTE_NORETURN;
>   void   signal_init (void);
> @@ -487,7 +496,9 @@ void   cond_finish_check (int);
>   void   cond_exit_macro (int);
>   int    seen_at_least_1_file (void);
>   void   app_pop (char *);
> +void   as_report_context (void);
>   const char * as_where (unsigned int *);
> +const char * as_where_top (unsigned int *);
>   const char * as_where_physical (unsigned int *);
>   void   bump_line_counters (void);
>   void   do_scrub_begin (int);
> --- a/gas/input-scrub.c
> +++ b/gas/input-scrub.c
> @@ -104,6 +104,9 @@ static const char *logical_input_file;
>   static unsigned int physical_input_line;
>   static unsigned int logical_input_line;
>   
> +/* Indicator whether the origin of an update was a .linefile directive. */
> +static bool is_linefile;
> +
>   /* Struct used to save the state of the input handler during include files */
>   struct input_save {
>     char *              buffer_start;
> @@ -115,6 +118,7 @@ struct input_save {
>     const char *        logical_input_file;
>     unsigned int        physical_input_line;
>     unsigned int        logical_input_line;
> +  bool                is_linefile;
>     size_t              sb_index;
>     sb                  from_sb;
>     enum expansion      from_sb_expansion; /* Should we do a conditional check?  */
> @@ -166,6 +170,7 @@ input_scrub_push (char *saved_position)
>     saved->logical_input_file = logical_input_file;
>     saved->physical_input_line = physical_input_line;
>     saved->logical_input_line = logical_input_line;
> +  saved->is_linefile = is_linefile;
>     saved->sb_index = sb_index;
>     saved->from_sb = from_sb;
>     saved->from_sb_expansion = from_sb_expansion;
> @@ -193,6 +198,7 @@ input_scrub_pop (struct input_save *save
>     logical_input_file = saved->logical_input_file;
>     physical_input_line = saved->physical_input_line;
>     logical_input_line = saved->logical_input_line;
> +  is_linefile = saved->is_linefile;
>     sb_index = saved->sb_index;
>     from_sb = saved->from_sb;
>     from_sb_expansion = saved->from_sb_expansion;
> @@ -267,8 +273,6 @@ input_scrub_include_sb (sb *from, char *
>       as_fatal (_("macros nested too deeply"));
>     ++macro_nest;
>   
> -  gas_assert (expansion < expanding_nested);
> -
>   #ifdef md_macro_start
>     if (expansion == expanding_macro)
>       {
> @@ -283,8 +287,6 @@ input_scrub_include_sb (sb *from, char *
>        expansion.  */
>     newline = from->len >= 1 && from->ptr[0] != '\n';
>     sb_build (&from_sb, from->len + newline + 2 * sizeof (".linefile") + 30);
> -  if (expansion == expanding_repeat && from_sb_expansion >= expanding_macro)
> -    expansion = expanding_nested;
>     from_sb_expansion = expansion;
>     if (newline)
>       {
> @@ -437,10 +439,7 @@ bump_line_counters (void)
>     if (sb_index == (size_t) -1)
>       ++physical_input_line;
>   
> -  /* PR gas/16908 workaround: Don't bump logical line numbers while
> -     expanding macros, unless file (and maybe line; see as_where()) are
> -     used inside the macro.  */
> -  if (logical_input_line != -1u && from_sb_expansion < expanding_macro)
> +  if (logical_input_line != -1u)
>       ++logical_input_line;
>   }
>   \f
> @@ -471,10 +470,6 @@ new_logical_line_flags (const char *fnam
>       case 1 << 3:
>         if (line_number < 0 || fname != NULL)
>   	abort ();
> -      /* PR gas/16908 workaround: Ignore updates when nested inside a macro
> -	 expansion.  */
> -      if (from_sb_expansion == expanding_nested)
> -	return;
>         if (next_saved_file == NULL)
>   	fname = physical_input_file;
>         else if (next_saved_file->logical_input_file)
> @@ -486,6 +481,8 @@ new_logical_line_flags (const char *fnam
>         abort ();
>       }
>   
> +  is_linefile = flags != 1 && (flags != 0 || fname);
> +
>     if (line_number >= 0)
>       logical_input_line = line_number;
>     else if (line_number == -1 && fname && !*fname && (flags & (1 << 2)))
> @@ -499,15 +496,6 @@ new_logical_line_flags (const char *fnam
>         && (logical_input_file == NULL
>   	  || filename_cmp (logical_input_file, fname)))
>       logical_input_file = fname;
> -
> -  /* When encountering file or line changes inside a macro, arrange for
> -     bump_line_counters() to henceforth increment the logical line number
> -     again, just like it does when expanding repeats.  See as_where() for
> -     why changing file or line alone doesn't alter expansion mode.  */
> -  if (from_sb_expansion == expanding_macro
> -      && logical_input_file != NULL
> -      && logical_input_line != -1u)
> -    from_sb_expansion = expanding_repeat;
>   }
>   
>   void
> @@ -516,6 +504,33 @@ new_logical_line (const char *fname, int
>     new_logical_line_flags (fname, line_number, 0);
>   }
>   
> +void
> +as_report_context (void)
> +{
> +  const struct input_save *saved = next_saved_file;
> +  enum expansion expansion = from_sb_expansion;
> +  int indent = 1;
> +
> +  if (!macro_nest)
> +    return;
> +
> +  do
> +    {
> +      if (expansion != expanding_macro)
> +	/* Nothing.  */;
> +      else if (saved->logical_input_file != NULL
> +	       && saved->logical_input_line != -1u)
> +	as_info_where (saved->logical_input_file, saved->logical_input_line,
> +		       indent, _("macro invoked from here"));
> +      else
> +	as_info_where (saved->physical_input_file, saved->physical_input_line,
> +		       indent, _("macro invoked from here"));
> +
> +      expansion = saved->from_sb_expansion;
> +      ++indent;
> +    }
> +  while ((saved = saved->next_saved_file) != NULL);
> +}
>   \f
>   /* Return the current physical input file name and line number, if known  */
>   
> @@ -534,11 +549,53 @@ as_where_physical (unsigned int *linep)
>     return NULL;
>   }
>   
> -/* Return the current file name and line number.  */
> +/* Return the file name and line number at the top most macro
> +   invocation, unless .file / .line were used inside a macro.  */
>   
>   const char *
>   as_where (unsigned int *linep)
>   {
> +  const char *file = as_where_top (linep);
> +
> +  if (macro_nest && is_linefile)
> +    {
> +      const struct input_save *saved = next_saved_file;
> +      enum expansion expansion = from_sb_expansion;
> +
> +      do
> +	{
> +	  if (!saved->is_linefile)
> +	    break;
> +
> +	  if (expansion != expanding_macro)
> +	    /* Nothing.  */;
> +	  else if (saved->logical_input_file != NULL
> +		   && (linep == NULL || saved->logical_input_line != -1u))
> +	    {
> +	      if (linep != NULL)
> +		*linep = saved->logical_input_line;
> +	      file = saved->logical_input_file;
> +	    }
> +	  else if (saved->physical_input_file != NULL)
> +	    {
> +	      if (linep != NULL)
> +		*linep = saved->physical_input_line;
> +	      file = saved->physical_input_file;
> +	    }
> +
> +	  expansion = saved->from_sb_expansion;
> +	}
> +      while ((saved = saved->next_saved_file) != NULL);
> +    }
> +
> +  return file;
> +}
> +
> +/* Return the current file name and line number.  */
> +
> +const char *
> +as_where_top (unsigned int *linep)
> +{
>     if (logical_input_file != NULL
>         && (linep == NULL || logical_input_line != -1u))
>       {
> @@ -549,4 +606,3 @@ as_where (unsigned int *linep)
>   
>     return as_where_physical (linep);
>   }
> -
> --- a/gas/macro.c
> +++ b/gas/macro.c
> @@ -131,23 +131,21 @@ buffer_and_nest (const char *from, const
>     else
>       from_len = strlen (from);
>   
> -  /* Except for macros record the present source position, such that
> -     diagnostics and debug info will be properly associated with the
> -     respective original lines, rather than with the line of the ending
> -     directive (TO).  */
> -  if (from == NULL || strcasecmp (from, "MACRO") != 0)
> -    {
> -      unsigned int line;
> -      char *linefile;
> -
> -      as_where (&line);
> -      if (!flag_m68k_mri)
> -	linefile = xasprintf ("\t.linefile %u .", line + 1);
> -      else
> -	linefile = xasprintf ("\tlinefile %u .", line + 1);
> -      sb_add_string (ptr, linefile);
> -      xfree (linefile);
> -    }
> +  /* Record the present source position, such that diagnostics and debug info
> +     can be properly associated with the respective original lines, rather
> +     than with the line of the ending directive (TO).  */
> +  {
> +    unsigned int line;
> +    char *linefile;
> +
> +    as_where_top (&line);
> +    if (!flag_m68k_mri)
> +      linefile = xasprintf ("\t.linefile %u .", line + 1);
> +    else
> +      linefile = xasprintf ("\tlinefile %u .", line + 1);
> +    sb_add_string (ptr, linefile);
> +    xfree (linefile);
> +  }
>   
>     while (more)
>       {
> @@ -249,14 +247,8 @@ buffer_and_nest (const char *from, const
>   	    }
>   
>   	  /* PR gas/16908
> -	     Apply and discard .linefile directives that appear within
> -	     the macro.  For long macros, one might want to report the
> -	     line number information associated with the lines within
> -	     the macro definition, but we would need more infrastructure
> -	     to make that happen correctly (e.g. resetting the line
> -	     number when expanding the macro), and since for short
> -	     macros we clearly prefer reporting the point of expansion
> -	     anyway, there's not an obviously better fix here.  */
> +	     Apply .linefile directives that appear within the macro, alongside
> +	     keeping them for later expansion of the macro.  */
>   	  if (from != NULL && strcasecmp (from, "MACRO") == 0
>   	      && len >= 8 && strncasecmp (ptr->ptr + i, "linefile", 8) == 0)
>   	    {
> @@ -267,7 +259,6 @@ buffer_and_nest (const char *from, const
>   	      s_linefile (0);
>   	      restore_ilp ();
>   	      ptr->ptr[ptr->len] = saved_eol_char;
> -	      ptr->len = line_start;
>   	    }
>   	}
>   
> --- a/gas/messages.c
> +++ b/gas/messages.c
> @@ -18,6 +18,7 @@
>      02110-1301, USA.  */
>   
>   #include "as.h"
> +#include <limits.h>
>   #include <signal.h>
>   
>   /* If the system doesn't provide strsignal, we get it defined in
> @@ -119,7 +120,7 @@ as_show_where (void)
>     const char *file;
>     unsigned int line;
>   
> -  file = as_where (&line);
> +  file = as_where_top (&line);
>     identify (file);
>     if (file)
>       {
> @@ -130,6 +131,25 @@ as_show_where (void)
>       }
>   }
>   
> +/* Send to stderr a string as information, with location data passed in.
> +   Note that for now this is not intended for general use.  */
> +
> +void
> +as_info_where (const char *file, unsigned int line, unsigned int indent,
> +	       const char *format, ...)
> +{
> +  va_list args;
> +  char buffer[2000];
> +
> +  gas_assert (file != NULL && line > 0 && indent <= INT_MAX);
> +
> +  va_start (args, format);
> +  vsnprintf (buffer, sizeof (buffer), format, args);
> +  va_end (args);
> +  fprintf (stderr, "%s:%u: %*s%s%s\n",
> +	   file, line, (int)indent, "", _("Info: "), buffer);
> +}
> +
>   /* Send to stderr a string as a warning, and locate warning
>      in input file(s).
>      Please only use this for when we have some recovery action.
> @@ -146,6 +166,7 @@ as_tsktsk (const char *format, ...)
>     vfprintf (stderr, format, args);
>     va_end (args);
>     (void) putc ('\n', stderr);
> +  as_report_context ();
>   }
>   
>   /* The common portion of as_warn and as_warn_where.  */
> @@ -153,10 +174,15 @@ as_tsktsk (const char *format, ...)
>   static void
>   as_warn_internal (const char *file, unsigned int line, char *buffer)
>   {
> +  bool context = false;
> +
>     ++warning_count;
>   
>     if (file == NULL)
> -    file = as_where (&line);
> +    {
> +      file = as_where_top (&line);
> +      context = true;
> +    }
>   
>     identify (file);
>     if (file)
> @@ -168,6 +194,10 @@ as_warn_internal (const char *file, unsi
>       }
>     else
>       fprintf (stderr, "%s%s\n", _("Warning: "), buffer);
> +
> +  if (context)
> +    as_report_context ();
> +
>   #ifndef NO_LISTING
>     listing_warning (buffer);
>   #endif
> @@ -194,7 +224,7 @@ as_warn (const char *format, ...)
>       }
>   }
>   
> -/* Like as_bad but the file name and line number are passed in.
> +/* Like as_warn but the file name and line number are passed in.
>      Unfortunately, we have to repeat the function in order to handle
>      the varargs correctly and portably.  */
>   
> @@ -218,10 +248,15 @@ as_warn_where (const char *file, unsigne
>   static void
>   as_bad_internal (const char *file, unsigned int line, char *buffer)
>   {
> +  bool context = false;
> +
>     ++error_count;
>   
>     if (file == NULL)
> -    file = as_where (&line);
> +    {
> +      file = as_where_top (&line);
> +      context = true;
> +    }
>   
>     identify (file);
>     if (file)
> @@ -233,6 +268,10 @@ as_bad_internal (const char *file, unsig
>       }
>     else
>       fprintf (stderr, "%s%s\n", _("Error: "), buffer);
> +
> +  if (context)
> +    as_report_context ();
> +
>   #ifndef NO_LISTING
>     listing_error (buffer);
>   #endif
> @@ -290,6 +329,7 @@ as_fatal (const char *format, ...)
>     vfprintf (stderr, format, args);
>     (void) putc ('\n', stderr);
>     va_end (args);
> +  as_report_context ();
>     /* Delete the output file, if it exists.  This will prevent make from
>        thinking that a file was created and hence does not need rebuilding.  */
>     if (out_file_name != NULL)
> @@ -312,6 +352,7 @@ as_abort (const char *file, int line, co
>       fprintf (stderr, _("Internal error in %s at %s:%d.\n"), fn, file, line);
>     else
>       fprintf (stderr, _("Internal error at %s:%d.\n"), file, line);
> +  as_report_context ();
>   
>     fprintf (stderr, _("Please report this bug.\n"));
>   
> --- a/gas/sb.h
> +++ b/gas/sb.h
> @@ -66,11 +66,9 @@ extern size_t sb_skip_comma (size_t, sb
>   
>   /* Actually in input-scrub.c.  */
>   enum expansion {
> -  /* Note: Order matters!  */
>     expanding_none,
>     expanding_repeat,
>     expanding_macro,
> -  expanding_nested, /* Only for internal use of input-scrub.c.  */
>   };
>   extern void input_scrub_include_sb (sb *, char *, enum expansion);
>   

Re: [PATCH v2 2/2] gas: re-work line number tracking for macros and their expansions

[Luis Machado]

On 12/14/22 14:03, Luis Machado via Binutils wrote:
> Hi,
> 
> I'm not yet sure how, but this patch has broken at least one gdb test (gdb.asm/asm-source.exp) for aarch64-linux (Ubuntu 22.04 and 20.04).
> 
> Could you please take a look at it? I can do some testing with the aarch64 machines if that's helpful.
> 
> FAIL: gdb.asm/asm-source.exp: f at main
> FAIL: gdb.asm/asm-source.exp: n at main
> FAIL: gdb.asm/asm-source.exp: next over macro
> FAIL: gdb.asm/asm-source.exp: list
> FAIL: gdb.asm/asm-source.exp: f in foo2
> FAIL: gdb.asm/asm-source.exp: n in foo2
> FAIL: gdb.asm/asm-source.exp: bt ALL in foo2
> FAIL: gdb.asm/asm-source.exp: bt 2 in foo2
> FAIL: gdb.asm/asm-source.exp: bt 3 in foo3
> FAIL: gdb.asm/asm-source.exp: finish from foo3
> FAIL: gdb.asm/asm-source.exp: info source asmsrc2.s
> FAIL: gdb.asm/asm-source.exp: info line
> FAIL: gdb.asm/asm-source.exp: next over foo3
> FAIL: gdb.asm/asm-source.exp: return from foo2
> 
>                  === gdb Summary ===
> 
> # of expected passes            15
> # of unexpected failures        14
> 

I'm guessing if we build gas alongside gdb, then the gdb testsuite will use that new gas binary.

If something has changed in the format/structure of the output, we may need to adjust the testcase to match.

Re: [PATCH v2 2/2] gas: re-work line number tracking for macros and their expansions

[Andrew Burgess]

Luis Machado via Binutils <binutils@sourceware.org> writes:

> Hi,
>
> I'm not yet sure how, but this patch has broken at least one gdb test (gdb.asm/asm-source.exp) for aarch64-linux (Ubuntu 22.04 and 20.04).
>
> Could you please take a look at it? I can do some testing with the aarch64 machines if that's helpful.
>
> FAIL: gdb.asm/asm-source.exp: f at main
> FAIL: gdb.asm/asm-source.exp: n at main
> FAIL: gdb.asm/asm-source.exp: next over macro
> FAIL: gdb.asm/asm-source.exp: list
> FAIL: gdb.asm/asm-source.exp: f in foo2
> FAIL: gdb.asm/asm-source.exp: n in foo2
> FAIL: gdb.asm/asm-source.exp: bt ALL in foo2
> FAIL: gdb.asm/asm-source.exp: bt 2 in foo2
> FAIL: gdb.asm/asm-source.exp: bt 3 in foo3
> FAIL: gdb.asm/asm-source.exp: finish from foo3
> FAIL: gdb.asm/asm-source.exp: info source asmsrc2.s
> FAIL: gdb.asm/asm-source.exp: info line
> FAIL: gdb.asm/asm-source.exp: next over foo3
> FAIL: gdb.asm/asm-source.exp: return from foo2

Can confirm I'm seeing the same set of failures on x86-64 gdb when using
gas that includes this patch.

Thanks,
Andrew


>
>                  === gdb Summary ===
>
> # of expected passes            15
> # of unexpected failures        14
>
> On 12/9/22 10:52, Jan Beulich via Binutils wrote:
>> The PR gas/16908 workaround aimed at uniformly reporting line numbers
>> to reference macro invocation sites. As mentioned in a comment this may
>> be desirable for small macros, but often isn't for larger ones. As a
>> first step improve diagnostics to report both locations, while aiming at
>> leaving generated debug info unaltered.
>> 
>> Note that macro invocation context is lost for any diagnostics issued
>> only after all input was processed (or more generally for any use of
>> as_*_where(), as the functions can't know whether the passed in location
>> is related to [part of] the present stack of locations). To maintain the
>> intended workaround behavior for PR gas/16908, a new as_where() is
>> introduced to "look through" macro invocations, while the existing
>> as_where() is renamed (and used in only very few places for now). Down
>> the road as_where() will likely want to return a list of (file,line)
>> pairs.
>> ---
>> v2: Fully cover Arm testsuite.
>> ---
>> Omitting testsuite adjustments from the inline patch, for its sheer size;
>> please see the attachment for the full (compressed) patch.
>> ---
>> Adding
>> 
>>        if (subseg_text_p (now_seg))
>> 	dwarf2_emit_insn (0);
>> 
>> to try_macro() (alongside using as_where_top() in dwarf2_where()) would
>> get .debug_line contents into reasonable shape (expressing both macro
>> invocation site and macro definition location). But that's likely
>> insufficient: We may want / need to represent macros as inline
>> subprograms and their expansions as inlined subroutines. Which in turn
>> looks cumbersome especially with the relatively recently added recording
>> of functions (with which macro expansions then would better be
>> associated, when marked as such).
>> 
>> --- a/gas/as.h
>> +++ b/gas/as.h
>> @@ -437,6 +437,10 @@ typedef struct _pseudo_type pseudo_typeS
>>   #define PRINTF_WHERE_LIKE(FCN) \
>>     void FCN (const char *file, unsigned int line, const char *format, ...) \
>>       __attribute__ ((__format__ (__printf__, 3, 4)))
>> +#define PRINTF_INDENT_LIKE(FCN) \
>> +  void FCN (const char *file, unsigned int line, unsigned int indent, \
>> +	    const char *format, ...) \
>> +    __attribute__ ((__format__ (__printf__, 4, 5)))
>>   
>>   #else /* __GNUC__ < 2 || defined(VMS) */
>>   
>> @@ -444,6 +448,10 @@ typedef struct _pseudo_type pseudo_typeS
>>   #define PRINTF_WHERE_LIKE(FCN)	void FCN (const char *file, \
>>   					  unsigned int line, \
>>   					  const char *format, ...)
>> +#define PRINTF_INDENT_LIKE(FCN)	void FCN (const char *file, \
>> +					  unsigned int line, \
>> +					  unsigned int indent, \
>> +					  const char *format, ...)
>>   
>>   #endif /* __GNUC__ < 2 || defined(VMS) */
>>   
>> @@ -453,6 +461,7 @@ PRINTF_LIKE (as_tsktsk);
>>   PRINTF_LIKE (as_warn);
>>   PRINTF_WHERE_LIKE (as_bad_where);
>>   PRINTF_WHERE_LIKE (as_warn_where);
>> +PRINTF_INDENT_LIKE (as_info_where);
>>   
>>   void   as_abort (const char *, int, const char *) ATTRIBUTE_NORETURN;
>>   void   signal_init (void);
>> @@ -487,7 +496,9 @@ void   cond_finish_check (int);
>>   void   cond_exit_macro (int);
>>   int    seen_at_least_1_file (void);
>>   void   app_pop (char *);
>> +void   as_report_context (void);
>>   const char * as_where (unsigned int *);
>> +const char * as_where_top (unsigned int *);
>>   const char * as_where_physical (unsigned int *);
>>   void   bump_line_counters (void);
>>   void   do_scrub_begin (int);
>> --- a/gas/input-scrub.c
>> +++ b/gas/input-scrub.c
>> @@ -104,6 +104,9 @@ static const char *logical_input_file;
>>   static unsigned int physical_input_line;
>>   static unsigned int logical_input_line;
>>   
>> +/* Indicator whether the origin of an update was a .linefile directive. */
>> +static bool is_linefile;
>> +
>>   /* Struct used to save the state of the input handler during include files */
>>   struct input_save {
>>     char *              buffer_start;
>> @@ -115,6 +118,7 @@ struct input_save {
>>     const char *        logical_input_file;
>>     unsigned int        physical_input_line;
>>     unsigned int        logical_input_line;
>> +  bool                is_linefile;
>>     size_t              sb_index;
>>     sb                  from_sb;
>>     enum expansion      from_sb_expansion; /* Should we do a conditional check?  */
>> @@ -166,6 +170,7 @@ input_scrub_push (char *saved_position)
>>     saved->logical_input_file = logical_input_file;
>>     saved->physical_input_line = physical_input_line;
>>     saved->logical_input_line = logical_input_line;
>> +  saved->is_linefile = is_linefile;
>>     saved->sb_index = sb_index;
>>     saved->from_sb = from_sb;
>>     saved->from_sb_expansion = from_sb_expansion;
>> @@ -193,6 +198,7 @@ input_scrub_pop (struct input_save *save
>>     logical_input_file = saved->logical_input_file;
>>     physical_input_line = saved->physical_input_line;
>>     logical_input_line = saved->logical_input_line;
>> +  is_linefile = saved->is_linefile;
>>     sb_index = saved->sb_index;
>>     from_sb = saved->from_sb;
>>     from_sb_expansion = saved->from_sb_expansion;
>> @@ -267,8 +273,6 @@ input_scrub_include_sb (sb *from, char *
>>       as_fatal (_("macros nested too deeply"));
>>     ++macro_nest;
>>   
>> -  gas_assert (expansion < expanding_nested);
>> -
>>   #ifdef md_macro_start
>>     if (expansion == expanding_macro)
>>       {
>> @@ -283,8 +287,6 @@ input_scrub_include_sb (sb *from, char *
>>        expansion.  */
>>     newline = from->len >= 1 && from->ptr[0] != '\n';
>>     sb_build (&from_sb, from->len + newline + 2 * sizeof (".linefile") + 30);
>> -  if (expansion == expanding_repeat && from_sb_expansion >= expanding_macro)
>> -    expansion = expanding_nested;
>>     from_sb_expansion = expansion;
>>     if (newline)
>>       {
>> @@ -437,10 +439,7 @@ bump_line_counters (void)
>>     if (sb_index == (size_t) -1)
>>       ++physical_input_line;
>>   
>> -  /* PR gas/16908 workaround: Don't bump logical line numbers while
>> -     expanding macros, unless file (and maybe line; see as_where()) are
>> -     used inside the macro.  */
>> -  if (logical_input_line != -1u && from_sb_expansion < expanding_macro)
>> +  if (logical_input_line != -1u)
>>       ++logical_input_line;
>>   }
>>   \f
>> @@ -471,10 +470,6 @@ new_logical_line_flags (const char *fnam
>>       case 1 << 3:
>>         if (line_number < 0 || fname != NULL)
>>   	abort ();
>> -      /* PR gas/16908 workaround: Ignore updates when nested inside a macro
>> -	 expansion.  */
>> -      if (from_sb_expansion == expanding_nested)
>> -	return;
>>         if (next_saved_file == NULL)
>>   	fname = physical_input_file;
>>         else if (next_saved_file->logical_input_file)
>> @@ -486,6 +481,8 @@ new_logical_line_flags (const char *fnam
>>         abort ();
>>       }
>>   
>> +  is_linefile = flags != 1 && (flags != 0 || fname);
>> +
>>     if (line_number >= 0)
>>       logical_input_line = line_number;
>>     else if (line_number == -1 && fname && !*fname && (flags & (1 << 2)))
>> @@ -499,15 +496,6 @@ new_logical_line_flags (const char *fnam
>>         && (logical_input_file == NULL
>>   	  || filename_cmp (logical_input_file, fname)))
>>       logical_input_file = fname;
>> -
>> -  /* When encountering file or line changes inside a macro, arrange for
>> -     bump_line_counters() to henceforth increment the logical line number
>> -     again, just like it does when expanding repeats.  See as_where() for
>> -     why changing file or line alone doesn't alter expansion mode.  */
>> -  if (from_sb_expansion == expanding_macro
>> -      && logical_input_file != NULL
>> -      && logical_input_line != -1u)
>> -    from_sb_expansion = expanding_repeat;
>>   }
>>   
>>   void
>> @@ -516,6 +504,33 @@ new_logical_line (const char *fname, int
>>     new_logical_line_flags (fname, line_number, 0);
>>   }
>>   
>> +void
>> +as_report_context (void)
>> +{
>> +  const struct input_save *saved = next_saved_file;
>> +  enum expansion expansion = from_sb_expansion;
>> +  int indent = 1;
>> +
>> +  if (!macro_nest)
>> +    return;
>> +
>> +  do
>> +    {
>> +      if (expansion != expanding_macro)
>> +	/* Nothing.  */;
>> +      else if (saved->logical_input_file != NULL
>> +	       && saved->logical_input_line != -1u)
>> +	as_info_where (saved->logical_input_file, saved->logical_input_line,
>> +		       indent, _("macro invoked from here"));
>> +      else
>> +	as_info_where (saved->physical_input_file, saved->physical_input_line,
>> +		       indent, _("macro invoked from here"));
>> +
>> +      expansion = saved->from_sb_expansion;
>> +      ++indent;
>> +    }
>> +  while ((saved = saved->next_saved_file) != NULL);
>> +}
>>   \f
>>   /* Return the current physical input file name and line number, if known  */
>>   
>> @@ -534,11 +549,53 @@ as_where_physical (unsigned int *linep)
>>     return NULL;
>>   }
>>   
>> -/* Return the current file name and line number.  */
>> +/* Return the file name and line number at the top most macro
>> +   invocation, unless .file / .line were used inside a macro.  */
>>   
>>   const char *
>>   as_where (unsigned int *linep)
>>   {
>> +  const char *file = as_where_top (linep);
>> +
>> +  if (macro_nest && is_linefile)
>> +    {
>> +      const struct input_save *saved = next_saved_file;
>> +      enum expansion expansion = from_sb_expansion;
>> +
>> +      do
>> +	{
>> +	  if (!saved->is_linefile)
>> +	    break;
>> +
>> +	  if (expansion != expanding_macro)
>> +	    /* Nothing.  */;
>> +	  else if (saved->logical_input_file != NULL
>> +		   && (linep == NULL || saved->logical_input_line != -1u))
>> +	    {
>> +	      if (linep != NULL)
>> +		*linep = saved->logical_input_line;
>> +	      file = saved->logical_input_file;
>> +	    }
>> +	  else if (saved->physical_input_file != NULL)
>> +	    {
>> +	      if (linep != NULL)
>> +		*linep = saved->physical_input_line;
>> +	      file = saved->physical_input_file;
>> +	    }
>> +
>> +	  expansion = saved->from_sb_expansion;
>> +	}
>> +      while ((saved = saved->next_saved_file) != NULL);
>> +    }
>> +
>> +  return file;
>> +}
>> +
>> +/* Return the current file name and line number.  */
>> +
>> +const char *
>> +as_where_top (unsigned int *linep)
>> +{
>>     if (logical_input_file != NULL
>>         && (linep == NULL || logical_input_line != -1u))
>>       {
>> @@ -549,4 +606,3 @@ as_where (unsigned int *linep)
>>   
>>     return as_where_physical (linep);
>>   }
>> -
>> --- a/gas/macro.c
>> +++ b/gas/macro.c
>> @@ -131,23 +131,21 @@ buffer_and_nest (const char *from, const
>>     else
>>       from_len = strlen (from);
>>   
>> -  /* Except for macros record the present source position, such that
>> -     diagnostics and debug info will be properly associated with the
>> -     respective original lines, rather than with the line of the ending
>> -     directive (TO).  */
>> -  if (from == NULL || strcasecmp (from, "MACRO") != 0)
>> -    {
>> -      unsigned int line;
>> -      char *linefile;
>> -
>> -      as_where (&line);
>> -      if (!flag_m68k_mri)
>> -	linefile = xasprintf ("\t.linefile %u .", line + 1);
>> -      else
>> -	linefile = xasprintf ("\tlinefile %u .", line + 1);
>> -      sb_add_string (ptr, linefile);
>> -      xfree (linefile);
>> -    }
>> +  /* Record the present source position, such that diagnostics and debug info
>> +     can be properly associated with the respective original lines, rather
>> +     than with the line of the ending directive (TO).  */
>> +  {
>> +    unsigned int line;
>> +    char *linefile;
>> +
>> +    as_where_top (&line);
>> +    if (!flag_m68k_mri)
>> +      linefile = xasprintf ("\t.linefile %u .", line + 1);
>> +    else
>> +      linefile = xasprintf ("\tlinefile %u .", line + 1);
>> +    sb_add_string (ptr, linefile);
>> +    xfree (linefile);
>> +  }
>>   
>>     while (more)
>>       {
>> @@ -249,14 +247,8 @@ buffer_and_nest (const char *from, const
>>   	    }
>>   
>>   	  /* PR gas/16908
>> -	     Apply and discard .linefile directives that appear within
>> -	     the macro.  For long macros, one might want to report the
>> -	     line number information associated with the lines within
>> -	     the macro definition, but we would need more infrastructure
>> -	     to make that happen correctly (e.g. resetting the line
>> -	     number when expanding the macro), and since for short
>> -	     macros we clearly prefer reporting the point of expansion
>> -	     anyway, there's not an obviously better fix here.  */
>> +	     Apply .linefile directives that appear within the macro, alongside
>> +	     keeping them for later expansion of the macro.  */
>>   	  if (from != NULL && strcasecmp (from, "MACRO") == 0
>>   	      && len >= 8 && strncasecmp (ptr->ptr + i, "linefile", 8) == 0)
>>   	    {
>> @@ -267,7 +259,6 @@ buffer_and_nest (const char *from, const
>>   	      s_linefile (0);
>>   	      restore_ilp ();
>>   	      ptr->ptr[ptr->len] = saved_eol_char;
>> -	      ptr->len = line_start;
>>   	    }
>>   	}
>>   
>> --- a/gas/messages.c
>> +++ b/gas/messages.c
>> @@ -18,6 +18,7 @@
>>      02110-1301, USA.  */
>>   
>>   #include "as.h"
>> +#include <limits.h>
>>   #include <signal.h>
>>   
>>   /* If the system doesn't provide strsignal, we get it defined in
>> @@ -119,7 +120,7 @@ as_show_where (void)
>>     const char *file;
>>     unsigned int line;
>>   
>> -  file = as_where (&line);
>> +  file = as_where_top (&line);
>>     identify (file);
>>     if (file)
>>       {
>> @@ -130,6 +131,25 @@ as_show_where (void)
>>       }
>>   }
>>   
>> +/* Send to stderr a string as information, with location data passed in.
>> +   Note that for now this is not intended for general use.  */
>> +
>> +void
>> +as_info_where (const char *file, unsigned int line, unsigned int indent,
>> +	       const char *format, ...)
>> +{
>> +  va_list args;
>> +  char buffer[2000];
>> +
>> +  gas_assert (file != NULL && line > 0 && indent <= INT_MAX);
>> +
>> +  va_start (args, format);
>> +  vsnprintf (buffer, sizeof (buffer), format, args);
>> +  va_end (args);
>> +  fprintf (stderr, "%s:%u: %*s%s%s\n",
>> +	   file, line, (int)indent, "", _("Info: "), buffer);
>> +}
>> +
>>   /* Send to stderr a string as a warning, and locate warning
>>      in input file(s).
>>      Please only use this for when we have some recovery action.
>> @@ -146,6 +166,7 @@ as_tsktsk (const char *format, ...)
>>     vfprintf (stderr, format, args);
>>     va_end (args);
>>     (void) putc ('\n', stderr);
>> +  as_report_context ();
>>   }
>>   
>>   /* The common portion of as_warn and as_warn_where.  */
>> @@ -153,10 +174,15 @@ as_tsktsk (const char *format, ...)
>>   static void
>>   as_warn_internal (const char *file, unsigned int line, char *buffer)
>>   {
>> +  bool context = false;
>> +
>>     ++warning_count;
>>   
>>     if (file == NULL)
>> -    file = as_where (&line);
>> +    {
>> +      file = as_where_top (&line);
>> +      context = true;
>> +    }
>>   
>>     identify (file);
>>     if (file)
>> @@ -168,6 +194,10 @@ as_warn_internal (const char *file, unsi
>>       }
>>     else
>>       fprintf (stderr, "%s%s\n", _("Warning: "), buffer);
>> +
>> +  if (context)
>> +    as_report_context ();
>> +
>>   #ifndef NO_LISTING
>>     listing_warning (buffer);
>>   #endif
>> @@ -194,7 +224,7 @@ as_warn (const char *format, ...)
>>       }
>>   }
>>   
>> -/* Like as_bad but the file name and line number are passed in.
>> +/* Like as_warn but the file name and line number are passed in.
>>      Unfortunately, we have to repeat the function in order to handle
>>      the varargs correctly and portably.  */
>>   
>> @@ -218,10 +248,15 @@ as_warn_where (const char *file, unsigne
>>   static void
>>   as_bad_internal (const char *file, unsigned int line, char *buffer)
>>   {
>> +  bool context = false;
>> +
>>     ++error_count;
>>   
>>     if (file == NULL)
>> -    file = as_where (&line);
>> +    {
>> +      file = as_where_top (&line);
>> +      context = true;
>> +    }
>>   
>>     identify (file);
>>     if (file)
>> @@ -233,6 +268,10 @@ as_bad_internal (const char *file, unsig
>>       }
>>     else
>>       fprintf (stderr, "%s%s\n", _("Error: "), buffer);
>> +
>> +  if (context)
>> +    as_report_context ();
>> +
>>   #ifndef NO_LISTING
>>     listing_error (buffer);
>>   #endif
>> @@ -290,6 +329,7 @@ as_fatal (const char *format, ...)
>>     vfprintf (stderr, format, args);
>>     (void) putc ('\n', stderr);
>>     va_end (args);
>> +  as_report_context ();
>>     /* Delete the output file, if it exists.  This will prevent make from
>>        thinking that a file was created and hence does not need rebuilding.  */
>>     if (out_file_name != NULL)
>> @@ -312,6 +352,7 @@ as_abort (const char *file, int line, co
>>       fprintf (stderr, _("Internal error in %s at %s:%d.\n"), fn, file, line);
>>     else
>>       fprintf (stderr, _("Internal error at %s:%d.\n"), file, line);
>> +  as_report_context ();
>>   
>>     fprintf (stderr, _("Please report this bug.\n"));
>>   
>> --- a/gas/sb.h
>> +++ b/gas/sb.h
>> @@ -66,11 +66,9 @@ extern size_t sb_skip_comma (size_t, sb
>>   
>>   /* Actually in input-scrub.c.  */
>>   enum expansion {
>> -  /* Note: Order matters!  */
>>     expanding_none,
>>     expanding_repeat,
>>     expanding_macro,
>> -  expanding_nested, /* Only for internal use of input-scrub.c.  */
>>   };
>>   extern void input_scrub_include_sb (sb *, char *, enum expansion);
>>   

Re: [PATCH v2 2/2] gas: re-work line number tracking for macros and their expansions

[Andrew Burgess]

Andrew Burgess <aburgess@redhat.com> writes:

> Luis Machado via Binutils <binutils@sourceware.org> writes:
>
>> Hi,
>>
>> I'm not yet sure how, but this patch has broken at least one gdb test (gdb.asm/asm-source.exp) for aarch64-linux (Ubuntu 22.04 and 20.04).
>>
>> Could you please take a look at it? I can do some testing with the aarch64 machines if that's helpful.
>>
>> FAIL: gdb.asm/asm-source.exp: f at main
>> FAIL: gdb.asm/asm-source.exp: n at main
>> FAIL: gdb.asm/asm-source.exp: next over macro
>> FAIL: gdb.asm/asm-source.exp: list
>> FAIL: gdb.asm/asm-source.exp: f in foo2
>> FAIL: gdb.asm/asm-source.exp: n in foo2
>> FAIL: gdb.asm/asm-source.exp: bt ALL in foo2
>> FAIL: gdb.asm/asm-source.exp: bt 2 in foo2
>> FAIL: gdb.asm/asm-source.exp: bt 3 in foo3
>> FAIL: gdb.asm/asm-source.exp: finish from foo3
>> FAIL: gdb.asm/asm-source.exp: info source asmsrc2.s
>> FAIL: gdb.asm/asm-source.exp: info line
>> FAIL: gdb.asm/asm-source.exp: next over foo3
>> FAIL: gdb.asm/asm-source.exp: return from foo2
>
> Can confirm I'm seeing the same set of failures on x86-64 gdb when using
> gas that includes this patch.

I think I understand the issue a little more now.  I have a simple
reproducer which can be run outside the gdb testsuite (see below).

It appears that the DWARF for macros now tries to associate the
instructions within the macro the source location within the macro
definition, rather than the macro use site.  I'm not entirely convinced
this is a good idea (as a macro could be used multiple times), or even
if this was an intended change of this series.

If this is the direction gas is moving in then I guess we will need to
update the GDB test, but there is, I think, a bug in the generated
DWARF, in that it appears that the wrong file name is being used.

Here's my steps to reproduce:

  $ cat test.s 
          .include "other.inc"
  
          .global _start
  _start:
          xor	%rbp, %rbp
          call    main
          hlt
  
          .global main
  main:
          gdbasm_enter
          hlt
  $ cat other.inc 
  	.macro gdbasm_enter
  	push	%rbp
  	mov	%rsp,%rbp
  	.endm
  $ cat Makefile 
  all:
  	$(AS) --gdwarf-2 -o test.o test.s
  	$(LD) -o test test.o
  
  clean:
  	-rm -f test.o test
  
  $ make AS=/path/to/recent/build/of/gas/as-new
  /path/to/recent/build/of/gas/as-new --gdwarf-2 -o test.o test.s
  ld -o test test.o
  $ cat cmd.gdb 
  set height 0
  set trace-commands on
  start
  frame
  
  $ gdb -q -x cmd.gdb test
  Reading symbols from test...
  +start
  Temporary breakpoint 1 at 0x401009: file test.s, line 2.
  
  Temporary breakpoint 1, main () at test.s:2
  2	
  +frame
  #0  main () at test.s:2
  2	
  (gdb)

Notice that when we stopped at 'main' in gdb the location was reported
as test.s:2.  The '2' here is correctly indicating line 2, but the file
should be 'other.inc', not 'test.s'.

If I rebuild using an older version of gas, then repeat the gdb step,
the old behaviour was:

  $ make
  as --gdwarf-2 -o test.o test.s
  ld -o test test.o
  $ gdb -q -x cmd.gdb test
  Reading symbols from test...
  +start
  Temporary breakpoint 1 at 0x401009: file test.s, line 11.
  
  Temporary breakpoint 1, main () at test.s:11
  11	        gdbasm_enter
  +frame
  #0  main () at test.s:11
  11	        gdbasm_enter
  (gdb) 

Now the location is 'test.s:11', pointing at the macro invocation.  To
me, this seems more helpful, but that's just my $0.02 worth.

As a separate idea from the above, I wonder if we could have gas
generate the DWARF required to represent the macro expansion as an
inlined function.  This might solve the problem of whether the DWARF
should point at the location of the macro definition, or the macro
invocation...

Anyway, hopefully the reproducer helps track down the problem.

Thanks,
Andrew

Re: [PATCH v2 2/2] gas: re-work line number tracking for macros and their expansions

[Jan Beulich]

On 14.12.2022 17:58, Andrew Burgess wrote:
> I think I understand the issue a little more now.  I have a simple
> reproducer which can be run outside the gdb testsuite (see below).
> 
> It appears that the DWARF for macros now tries to associate the
> instructions within the macro the source location within the macro
> definition, rather than the macro use site.  I'm not entirely convinced
> this is a good idea (as a macro could be used multiple times), or even
> if this was an intended change of this series.

No, there was no intention to alter generated Dwarf. In fact I had put in
place a test ahead of this change here (commit 6fdb723799e2) to have at
least some proof of that. Quite likely that wasn't elaborate enough a test
then.

> If this is the direction gas is moving in then I guess we will need to
> update the GDB test, but there is, I think, a bug in the generated
> DWARF, in that it appears that the wrong file name is being used.

While I would like to improve representation of .macro expansions, we
first need to determine what the best way is for representing them. See
also the post-commit-message remark in the submission of the patch here.

Jan

Re: [PATCH v2 2/2] gas: re-work line number tracking for macros and their expansions

[Jan Beulich]

On 14.12.2022 17:58, Andrew Burgess wrote:
> Anyway, hopefully the reproducer helps track down the problem.

It did indeed. Below the patch that addresses the issue for me,
but before committing I will want to run this through the full set
of tests (after extending the testcase which didn't catch the issue).

Jan

gas: restore Dwarf info generation after macro diagnostic adjustments

While 6fdb723799e2 ("gas: re-work line number tracking for macros and
their expansions") was meant to leave generated Dwarf as is, it really
didn't (and the testcase intended to catch that wasn't covering the case
which broke). Its adjustment to buffer_and_nest() didn't go far enough,
leading to the "linefile" directive inserted at the top to also be
processed later in the PR gas/16908 workaround (which clearly isn't
intended - it's being put there for processing during macro expansion
only). That unnoticed flaw in turn led me to worked around it by a
(suspicious to me already at the time) conditional in as_where().

--- a/gas/input-scrub.c
+++ b/gas/input-scrub.c
@@ -564,9 +564,6 @@ as_where (unsigned int *linep)
 
       do
 	{
-	  if (!saved->is_linefile)
-	    break;
-
 	  if (expansion != expanding_macro)
 	    /* Nothing.  */;
 	  else if (saved->logical_input_file != NULL
--- a/gas/macro.c
+++ b/gas/macro.c
@@ -120,8 +120,7 @@ buffer_and_nest (const char *from, const
   size_t from_len;
   size_t to_len = strlen (to);
   int depth = 1;
-  size_t line_start = ptr->len;
-  size_t more = get_line (ptr);
+  size_t line_start, more;
 
   if (to_len == 4 && strcasecmp (to, "ENDR") == 0)
     {
@@ -147,6 +146,8 @@ buffer_and_nest (const char *from, const
     xfree (linefile);
   }
 
+  line_start = ptr->len;
+  more = get_line (ptr);
   while (more)
     {
       /* Try to find the first pseudo op on the line.  */

Re: [PATCH v2 2/2] gas: re-work line number tracking for macros and their expansions

[Andrew Burgess]

Jan Beulich <jbeulich@suse.com> writes:

> On 14.12.2022 17:58, Andrew Burgess wrote:
>> Anyway, hopefully the reproducer helps track down the problem.
>
> It did indeed. Below the patch that addresses the issue for me,
> but before committing I will want to run this through the full set
> of tests (after extending the testcase which didn't catch the issue).
>
> Jan

Can confirm that the patch below fixes the gdb.asm/asm-source.exp test
failure that I was seeing.

Thanks,
Andrew

>
> gas: restore Dwarf info generation after macro diagnostic adjustments
>
> While 6fdb723799e2 ("gas: re-work line number tracking for macros and
> their expansions") was meant to leave generated Dwarf as is, it really
> didn't (and the testcase intended to catch that wasn't covering the case
> which broke). Its adjustment to buffer_and_nest() didn't go far enough,
> leading to the "linefile" directive inserted at the top to also be
> processed later in the PR gas/16908 workaround (which clearly isn't
> intended - it's being put there for processing during macro expansion
> only). That unnoticed flaw in turn led me to worked around it by a
> (suspicious to me already at the time) conditional in as_where().
>
> --- a/gas/input-scrub.c
> +++ b/gas/input-scrub.c
> @@ -564,9 +564,6 @@ as_where (unsigned int *linep)
>  
>        do
>  	{
> -	  if (!saved->is_linefile)
> -	    break;
> -
>  	  if (expansion != expanding_macro)
>  	    /* Nothing.  */;
>  	  else if (saved->logical_input_file != NULL
> --- a/gas/macro.c
> +++ b/gas/macro.c
> @@ -120,8 +120,7 @@ buffer_and_nest (const char *from, const
>    size_t from_len;
>    size_t to_len = strlen (to);
>    int depth = 1;
> -  size_t line_start = ptr->len;
> -  size_t more = get_line (ptr);
> +  size_t line_start, more;
>  
>    if (to_len == 4 && strcasecmp (to, "ENDR") == 0)
>      {
> @@ -147,6 +146,8 @@ buffer_and_nest (const char *from, const
>      xfree (linefile);
>    }
>  
> +  line_start = ptr->len;
> +  more = get_line (ptr);
>    while (more)
>      {
>        /* Try to find the first pseudo op on the line.  */