From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [PATCH v3 7/7] x86: move bad-use-of-TLS-reloc check
Date: Wed, 12 Oct 2022 10:02:15 -0700 [thread overview]
Message-ID: <CAMe9rOoD-aCGnLjVRAX+tR9M3ZF=coRgYNL0jTzwTdhpZ9ipFg@mail.gmail.com> (raw)
In-Reply-To: <13901424-7999-aeac-c1a2-52baedaa593c@suse.com>
On Wed, Oct 12, 2022 at 12:13 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 11.10.2022 19:57, H.J. Lu wrote:
> > On Wed, Oct 5, 2022 at 12:25 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> Having it in match_template() is unhelpful. Neither does looking for the
> >> next template to possibly match make any sense in that case, nor is the
> >> resulting diagnostic making clear what the problem is.
> >>
> >> While moving the check, also generalize it to include all SIMD and VEX-
> >> encoded insns. This way an existing conditional can be re-used in
> >> md_assemble(). Note though that this still leaves a lof of insns which
> >> are also wrong to use with these relocations.
> >
> > These TLS instruction sequences are generated by compilers.
> > The check is only meant to check for invalid master registers.
>
> The sequence involving a mask register was generated (aiui) by mistake.
> Why would it not be possible to see another similar mistake involve an
> XMM register, with a legacy, VEX-, or EVEX-encoded insn?
We haven't seen it yet.
> Anyway - thanks for approving the patch.
>
> Jan
--
H.J.
prev parent reply other threads:[~2022-10-12 17:02 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-05 7:19 [PATCH v3 0/7] x86: suffix handling changes Jan Beulich
2022-10-05 7:20 ` [PATCH v3 1/7] x86: constify parse_insn()'s input Jan Beulich
2022-10-05 7:22 ` [PATCH v3 2/7] x86: introduce Pass2 insn attribute Jan Beulich
2022-10-05 7:23 ` [PATCH v3 3/7] x86: re-work insn/suffix recognition Jan Beulich
2022-10-05 23:52 ` H.J. Lu
2022-10-06 6:15 ` Jan Beulich
2022-10-06 6:58 ` Jan Beulich
2022-10-06 15:28 ` H.J. Lu
2022-10-06 16:12 ` Jan Beulich
2022-10-06 18:41 ` H.J. Lu
2022-10-07 13:03 ` Jan Beulich
2022-10-05 7:24 ` [PATCH v3 4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL Jan Beulich
2022-10-11 17:44 ` H.J. Lu
2022-10-12 7:08 ` Jan Beulich
2022-10-12 17:10 ` H.J. Lu
2022-10-13 6:08 ` Jan Beulich
2022-10-13 17:00 ` H.J. Lu
2022-10-14 7:03 ` Jan Beulich
2022-10-14 17:07 ` H.J. Lu
2022-10-17 7:02 ` Jan Beulich
2022-10-17 22:36 ` H.J. Lu
2022-10-18 6:31 ` Jan Beulich
2022-10-18 21:48 ` H.J. Lu
2022-10-19 6:08 ` Jan Beulich
2022-10-19 21:46 ` H.J. Lu
2022-10-20 10:12 ` Jan Beulich
2022-10-05 7:24 ` [PATCH v3 5/7] ix86: don't recognize/derive Q suffix in the common case Jan Beulich
2022-10-11 17:49 ` H.J. Lu
2022-10-05 7:25 ` [PATCH v3 6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address Jan Beulich
2022-10-11 17:50 ` H.J. Lu
2022-10-05 7:25 ` [PATCH v3 7/7] x86: move bad-use-of-TLS-reloc check Jan Beulich
2022-10-11 17:57 ` H.J. Lu
2022-10-12 7:13 ` Jan Beulich
2022-10-12 17:02 ` H.J. Lu [this message]
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