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From: Nelson Chu <>
To: Jeff Law <>
Subject: Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
Date: Mon, 3 Oct 2022 09:36:21 +0800	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

On Sun, Oct 2, 2022 at 11:59 PM Jeff Law via Binutils
<> wrote:
> On 10/1/22 14:27, Andrew Burgess via Binutils wrote:
> > I can't approve binutils patches, but as this mentioned RISC-V and
> > DWARF, both of which I'm interested in, I took a look :)
> >
> > Both these patches look good to me.  The register numbers align with the
> > spec, and the test makes sense.
> Well, that's the key property -- they align with the spec.
> I'm also not sure if I can approve for binutils, but if I can, OK for
> the trunk ;-)

Thanks for your help, Andrew and Jeff!

Hi Jeff,

Of course!  You are a global maintainer of both gcc and binutils.
Welcome and please feel free to approve any RISC-V binutils patch if
you are free and the patch looks good to you :-)


  parent reply	other threads:[~2022-10-03  1:36 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-22  6:32 Tsukasa OI
2022-09-22  6:32 ` [PATCH v3 1/2] RISC-V: Assign DWARF " Tsukasa OI
2022-09-22  6:32 ` [PATCH v3 2/2] RISC-V: Add testcase for DWARF register numbers Tsukasa OI
2022-10-01 20:27 ` [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Andrew Burgess
2022-10-02 15:58   ` Jeff Law
2022-10-02 19:35     ` Palmer Dabbelt
2022-10-03  1:36     ` Nelson Chu [this message]
2022-10-03  4:04       ` Jeff Law
2022-10-03  4:31       ` Tsukasa OI

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