From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Nelson Chu <nelson@rivosinc.com>,
Jeff Law <jeffreyalaw@gmail.com>,
Andrew Burgess <aburgess@redhat.com>
Cc: binutils@sourceware.org
Subject: Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
Date: Mon, 3 Oct 2022 13:31:14 +0900 [thread overview]
Message-ID: <9f63bceb-5536-5b17-3248-1dc17fa2e834@irq.a4lg.com> (raw)
In-Reply-To: <CAPpQWtA0KHRfXBERaP9mLwE44WSoDH4YVyCau76zZaRCDz_Osg@mail.gmail.com>
Many thanks to all of you!
Though I have to report that the exact changes you approved are merged
but two commits are splitted differently (due to technical mistake I
made; I mistakenly chose a "working" branch to push).
Approved PATCH v3:
- PATCH 1: Assign DWARF register numbers to vector ones
- PATCH 2: Add DWARF register number testcases (GPRs/FPRs/vector)
Merged commits:
- COMMIT 1: Add DWARF register number testcases (GPRs/FPRs)
- COMMIT 2: Assign DWARF register numbers to vector ones
and add them to "existing" tests
I repeat that changes (COMMIT 1+2) are the _exactly_ the same as PATCH
1+2 but splitted differently. Despite that this is functionally the
same, this is clearly not obvious and I should have checked. I'll
submit the remaining part (to add "fp" to DWARF register number
testcases) as a separate patch but feel free to revert those two
commits. In the event, I'll submit PATCH v4 of it.
Regards,
Tsukasa
On 2022/10/03 10:36, Nelson Chu wrote:
> On Sun, Oct 2, 2022 at 11:59 PM Jeff Law via Binutils
> <binutils@sourceware.org> wrote:
>>
>> On 10/1/22 14:27, Andrew Burgess via Binutils wrote:
>>> I can't approve binutils patches, but as this mentioned RISC-V and
>>> DWARF, both of which I'm interested in, I took a look :)
>>>
>>> Both these patches look good to me. The register numbers align with the
>>> spec, and the test makes sense.
>>
>> Well, that's the key property -- they align with the spec.
>>
>>
>> I'm also not sure if I can approve for binutils, but if I can, OK for
>> the trunk ;-)
>
> Thanks for your help, Andrew and Jeff!
>
> Hi Jeff,
>
> Of course! You are a global maintainer of both gcc and binutils.
> Welcome and please feel free to approve any RISC-V binutils patch if
> you are free and the patch looks good to you :-)
>
> Thanks!
> Nelson
>
prev parent reply other threads:[~2022-10-03 4:31 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 6:32 Tsukasa OI
2022-09-22 6:32 ` [PATCH v3 1/2] RISC-V: Assign DWARF " Tsukasa OI
2022-09-22 6:32 ` [PATCH v3 2/2] RISC-V: Add testcase for DWARF register numbers Tsukasa OI
2022-10-01 20:27 ` [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Andrew Burgess
2022-10-02 15:58 ` Jeff Law
2022-10-02 19:35 ` Palmer Dabbelt
2022-10-03 1:36 ` Nelson Chu
2022-10-03 4:04 ` Jeff Law
2022-10-03 4:31 ` Tsukasa OI [this message]
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