From: Andrew Burgess <aburgess@redhat.com>
To: Tsukasa OI via Binutils <binutils@sourceware.org>,
Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
Date: Sat, 01 Oct 2022 21:27:40 +0100 [thread overview]
Message-ID: <874jwni91f.fsf@redhat.com> (raw)
In-Reply-To: <cover.1663828349.git.research_trasio@irq.a4lg.com>
Tsukasa OI via Binutils <binutils@sourceware.org> writes:
> Hello,
>
> Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF
> register numbers. RISC-V ABIs Specification (riscv-elf-psabi-doc) is not
> ratified yet but at least frozen. So, I consider it's stable to upstream
> it. According to the documentation, it has register numbers 96 (v0) -
> 127 (v31).
>
> [Changes: v1 -> v2]
> Remove invented word "VPRs" (at least it has no consistent uses in the
> RISC-V ecosystem) and replaced with "Vector registers"
>
> [Changes: v2 -> v3]
> Changed reference (v1.0-rc3 -> v1.0-rc4).
>
> Tracker on GitHub:
> <https://github.com/a4lg/binutils-gdb/wiki/riscv_psabi_dwarf_vector_regs>
>
> RISC-V ABIs Specification Version 1.0-rc4: Frozen
> <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4>
>
>
> I also added DWARF register number tests not just for CSRs (existing) and
> vector registers (I just added), but also for GPRs (0-31) and FPRs
> (32-63).
Hi Tsukasa,
I can't approve binutils patches, but as this mentioned RISC-V and
DWARF, both of which I'm interested in, I took a look :)
Both these patches look good to me. The register numbers align with the
spec, and the test makes sense.
Thanks for the patch.
Andrew
>
>
> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (2):
> RISC-V: Assign DWARF numbers to vector registers
> RISC-V: Add testcase for DWARF register numbers
>
> binutils/dwarf.c | 28 ++--
> gas/config/tc-riscv.c | 3 +
> gas/testsuite/gas/riscv/dw-regnums.d | 180 ++++++++++++++++++++++++++
> gas/testsuite/gas/riscv/dw-regnums.s | 184 +++++++++++++++++++++++++++
> 4 files changed, 385 insertions(+), 10 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d
> create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s
>
>
> base-commit: 90eca7111355e4c6683c1ab10fd07107ea10f6d1
> --
> 2.34.1
next prev parent reply other threads:[~2022-10-01 20:27 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 6:32 Tsukasa OI
2022-09-22 6:32 ` [PATCH v3 1/2] RISC-V: Assign DWARF " Tsukasa OI
2022-09-22 6:32 ` [PATCH v3 2/2] RISC-V: Add testcase for DWARF register numbers Tsukasa OI
2022-10-01 20:27 ` Andrew Burgess [this message]
2022-10-02 15:58 ` [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Jeff Law
2022-10-02 19:35 ` Palmer Dabbelt
2022-10-03 1:36 ` Nelson Chu
2022-10-03 4:04 ` Jeff Law
2022-10-03 4:31 ` Tsukasa OI
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