From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v3 1/2] RISC-V: Assign DWARF numbers to vector registers
Date: Thu, 22 Sep 2022 06:32:33 +0000 [thread overview]
Message-ID: <df12c82543a2a2d7edfc65fb8ac613d6c7b6aaa0.1663828349.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1663828349.git.research_trasio@irq.a4lg.com>
This commit is to comply RISC-V DWARF Specification version 1.0-rc4
(in the frozen state):
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4
binutils/ChangeLog:
* dwarf.c (dwarf_regnames_riscv): Assign DWARF register numbers
96..127 to vector registers v0-v31.
gas/ChangeLog:
* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Support
vector registers.
---
binutils/dwarf.c | 28 ++++++++++++++++++----------
gas/config/tc-riscv.c | 3 +++
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/binutils/dwarf.c b/binutils/dwarf.c
index aef0f77eab6..c6340a28906 100644
--- a/binutils/dwarf.c
+++ b/binutils/dwarf.c
@@ -8540,16 +8540,24 @@ init_dwarf_regnames_s390 (void)
static const char *const dwarf_regnames_riscv[] =
{
- "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", /* 0 - 7 */
- "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", /* 8 - 15 */
- "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", /* 16 - 23 */
- "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", /* 24 - 31 */
- "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", /* 32 - 39 */
- "fs0", "fs1", /* 40 - 41 */
- "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", /* 42 - 49 */
- "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", /* 50 - 57 */
- "fs10", "fs11", /* 58 - 59 */
- "ft8", "ft9", "ft10", "ft11" /* 60 - 63 */
+ "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", /* 0 - 7 */
+ "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", /* 8 - 15 */
+ "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", /* 16 - 23 */
+ "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", /* 24 - 31 */
+ "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", /* 32 - 39 */
+ "fs0", "fs1", /* 40 - 41 */
+ "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", /* 42 - 49 */
+ "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", /* 50 - 57 */
+ "fs10", "fs11", /* 58 - 59 */
+ "ft8", "ft9", "ft10", "ft11", /* 60 - 63 */
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 64 - 71 */
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 72 - 79 */
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 80 - 87 */
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 88 - 95 */
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", /* 96 - 103 */
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", /* 104 - 111 */
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", /* 112 - 119 */
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", /* 120 - 127 */
};
/* A RISC-V replacement for REGNAME_INTERNAL_BY_TABLE_ONLY which handles
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5411d68a401..bc36625311a 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -4319,6 +4319,9 @@ tc_riscv_regname_to_dw2regnum (char *regname)
if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
return reg + 32;
+ if ((reg = reg_lookup_internal (regname, RCLASS_VECR)) >= 0)
+ return reg + 96;
+
/* CSRs are numbered 4096 -> 8191. */
if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
return reg + 4096;
--
2.34.1
next prev parent reply other threads:[~2022-09-22 6:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 6:32 [PATCH v3 0/2] RISC-V psABI: Assign DWARF register " Tsukasa OI
2022-09-22 6:32 ` Tsukasa OI [this message]
2022-09-22 6:32 ` [PATCH v3 2/2] RISC-V: Add testcase for DWARF register numbers Tsukasa OI
2022-10-01 20:27 ` [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Andrew Burgess
2022-10-02 15:58 ` Jeff Law
2022-10-02 19:35 ` Palmer Dabbelt
2022-10-03 1:36 ` Nelson Chu
2022-10-03 4:04 ` Jeff Law
2022-10-03 4:31 ` Tsukasa OI
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