* [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak.
@ 2023-04-21 8:28 Nelson Chu
2023-04-21 8:28 ` [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp Nelson Chu
2023-04-28 6:28 ` [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak Nelson Chu
0 siblings, 2 replies; 6+ messages in thread
From: Nelson Chu @ 2023-04-21 8:28 UTC (permalink / raw)
To: binutils, jim.wilson.gcc, palmer, kito.cheng; +Cc: nelson
bfd/
*elfnn-riscv.c (_bfd_riscv_relax_lui): For undefined weak symbol,
just relax the R_RISCV_LO12_I/S to R_RISCV_GPREL_I/S, and then don't
update the rs1 to zero until relocate_section.
(_bfd_riscv_relax_pc): Likewise, but for R_RISCV_PCREL_LO12_I/S.
---
bfd/elfnn-riscv.c | 55 ++++++-----------------------------------------
1 file changed, 6 insertions(+), 49 deletions(-)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index e90e36b58bb..499f51ee857 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -4552,27 +4552,11 @@ _bfd_riscv_relax_lui (bfd *abfd,
switch (ELFNN_R_TYPE (rel->r_info))
{
case R_RISCV_LO12_I:
- if (undefined_weak)
- {
- /* Change the RS1 to zero. */
- bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
- insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
- bfd_putl32 (insn, contents + rel->r_offset);
- }
- else
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
+ rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
return true;
case R_RISCV_LO12_S:
- if (undefined_weak)
- {
- /* Change the RS1 to zero. */
- bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
- insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
- bfd_putl32 (insn, contents + rel->r_offset);
- }
- else
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
+ rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
return true;
case R_RISCV_HI20:
@@ -4737,7 +4721,6 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
bool undefined_weak)
{
struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (link_info);
- bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
bfd_vma gp = riscv_global_pointer_value (link_info);
BFD_ASSERT (rel->r_offset + 4 <= sec->size);
@@ -4830,39 +4813,13 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
switch (ELFNN_R_TYPE (rel->r_info))
{
case R_RISCV_PCREL_LO12_I:
- if (undefined_weak)
- {
- /* Change the RS1 to zero, and then modify the relocation
- type to R_RISCV_LO12_I. */
- bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
- insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
- bfd_putl32 (insn, contents + rel->r_offset);
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_LO12_I);
- rel->r_addend = hi_reloc.hi_addend;
- }
- else
- {
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
- rel->r_addend += hi_reloc.hi_addend;
- }
+ rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
+ rel->r_addend += hi_reloc.hi_addend;
return true;
case R_RISCV_PCREL_LO12_S:
- if (undefined_weak)
- {
- /* Change the RS1 to zero, and then modify the relocation
- type to R_RISCV_LO12_S. */
- bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
- insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
- bfd_putl32 (insn, contents + rel->r_offset);
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_LO12_S);
- rel->r_addend = hi_reloc.hi_addend;
- }
- else
- {
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
- rel->r_addend += hi_reloc.hi_addend;
- }
+ rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
+ rel->r_addend += hi_reloc.hi_addend;
return true;
case R_RISCV_PCREL_HI20:
--
2.39.2 (Apple Git-143)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp.
2023-04-21 8:28 [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak Nelson Chu
@ 2023-04-21 8:28 ` Nelson Chu
2023-04-28 6:29 ` Nelson Chu
2023-04-28 6:28 ` [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak Nelson Chu
1 sibling, 1 reply; 6+ messages in thread
From: Nelson Chu @ 2023-04-21 8:28 UTC (permalink / raw)
To: binutils, jim.wilson.gcc, palmer, kito.cheng; +Cc: nelson
Let --no-relax-gp only disable the gp relaxation for lui and pcrel
relaxations, since x0 base and gp relaxations are different optimizations
in fact, but just use the same function to handle.
bfd/
* elfnn-riscv.c (_bfd_riscv_relax_pc): Like _bfd_riscv_relax_lui,
set gp to zero when --no-relax-gp, then we should still keep the
x0 base relaxation.
(_bfd_riscv_relax_section): Enable _bfd_riscv_relax_pc when
--no-relax-gp, we will disable the gp relaxation in the
_bfd_riscv_relax_pc.
---
bfd/elfnn-riscv.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 499f51ee857..77a732b6a08 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -4721,7 +4721,9 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
bool undefined_weak)
{
struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (link_info);
- bfd_vma gp = riscv_global_pointer_value (link_info);
+ bfd_vma gp = htab->params->relax_gp
+ ? riscv_global_pointer_value (link_info)
+ : 0;
BFD_ASSERT (rel->r_offset + 4 <= sec->size);
@@ -4942,7 +4944,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
|| type == R_RISCV_TPREL_LO12_I
|| type == R_RISCV_TPREL_LO12_S)
relax_func = _bfd_riscv_relax_tls_le;
- else if (!bfd_link_pic (info) && htab->params->relax_gp
+ else if (!bfd_link_pic (info)
&& (type == R_RISCV_PCREL_HI20
|| type == R_RISCV_PCREL_LO12_I
|| type == R_RISCV_PCREL_LO12_S))
--
2.39.2 (Apple Git-143)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak.
2023-04-21 8:28 [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak Nelson Chu
2023-04-21 8:28 ` [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp Nelson Chu
@ 2023-04-28 6:28 ` Nelson Chu
1 sibling, 0 replies; 6+ messages in thread
From: Nelson Chu @ 2023-04-28 6:28 UTC (permalink / raw)
To: binutils, jim.wilson.gcc, palmer, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 4174 bytes --]
Committed, thanks.
Nelson
On Fri, Apr 21, 2023 at 4:28 PM Nelson Chu <nelson@rivosinc.com> wrote:
> bfd/
> *elfnn-riscv.c (_bfd_riscv_relax_lui): For undefined weak symbol,
> just relax the R_RISCV_LO12_I/S to R_RISCV_GPREL_I/S, and then
> don't
> update the rs1 to zero until relocate_section.
> (_bfd_riscv_relax_pc): Likewise, but for R_RISCV_PCREL_LO12_I/S.
> ---
> bfd/elfnn-riscv.c | 55 ++++++-----------------------------------------
> 1 file changed, 6 insertions(+), 49 deletions(-)
>
> diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> index e90e36b58bb..499f51ee857 100644
> --- a/bfd/elfnn-riscv.c
> +++ b/bfd/elfnn-riscv.c
> @@ -4552,27 +4552,11 @@ _bfd_riscv_relax_lui (bfd *abfd,
> switch (ELFNN_R_TYPE (rel->r_info))
> {
> case R_RISCV_LO12_I:
> - if (undefined_weak)
> - {
> - /* Change the RS1 to zero. */
> - bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
> - insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
> - bfd_putl32 (insn, contents + rel->r_offset);
> - }
> - else
> - rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
> + rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
> return true;
>
> case R_RISCV_LO12_S:
> - if (undefined_weak)
> - {
> - /* Change the RS1 to zero. */
> - bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
> - insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
> - bfd_putl32 (insn, contents + rel->r_offset);
> - }
> - else
> - rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
> + rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
> return true;
>
> case R_RISCV_HI20:
> @@ -4737,7 +4721,6 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
> bool undefined_weak)
> {
> struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table
> (link_info);
> - bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
> bfd_vma gp = riscv_global_pointer_value (link_info);
>
> BFD_ASSERT (rel->r_offset + 4 <= sec->size);
> @@ -4830,39 +4813,13 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
> switch (ELFNN_R_TYPE (rel->r_info))
> {
> case R_RISCV_PCREL_LO12_I:
> - if (undefined_weak)
> - {
> - /* Change the RS1 to zero, and then modify the relocation
> - type to R_RISCV_LO12_I. */
> - bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
> - insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
> - bfd_putl32 (insn, contents + rel->r_offset);
> - rel->r_info = ELFNN_R_INFO (sym, R_RISCV_LO12_I);
> - rel->r_addend = hi_reloc.hi_addend;
> - }
> - else
> - {
> - rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
> - rel->r_addend += hi_reloc.hi_addend;
> - }
> + rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
> + rel->r_addend += hi_reloc.hi_addend;
> return true;
>
> case R_RISCV_PCREL_LO12_S:
> - if (undefined_weak)
> - {
> - /* Change the RS1 to zero, and then modify the relocation
> - type to R_RISCV_LO12_S. */
> - bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
> - insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
> - bfd_putl32 (insn, contents + rel->r_offset);
> - rel->r_info = ELFNN_R_INFO (sym, R_RISCV_LO12_S);
> - rel->r_addend = hi_reloc.hi_addend;
> - }
> - else
> - {
> - rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
> - rel->r_addend += hi_reloc.hi_addend;
> - }
> + rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
> + rel->r_addend += hi_reloc.hi_addend;
> return true;
>
> case R_RISCV_PCREL_HI20:
> --
> 2.39.2 (Apple Git-143)
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp.
2023-04-21 8:28 ` [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp Nelson Chu
@ 2023-04-28 6:29 ` Nelson Chu
2023-04-28 7:09 ` Fangrui Song
0 siblings, 1 reply; 6+ messages in thread
From: Nelson Chu @ 2023-04-28 6:29 UTC (permalink / raw)
To: binutils, jim.wilson.gcc, palmer, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 1928 bytes --]
Committed, thanks.
Nelson
On Fri, Apr 21, 2023 at 4:28 PM Nelson Chu <nelson@rivosinc.com> wrote:
> Let --no-relax-gp only disable the gp relaxation for lui and pcrel
> relaxations, since x0 base and gp relaxations are different optimizations
> in fact, but just use the same function to handle.
>
> bfd/
> * elfnn-riscv.c (_bfd_riscv_relax_pc): Like _bfd_riscv_relax_lui,
> set gp to zero when --no-relax-gp, then we should still keep the
> x0 base relaxation.
> (_bfd_riscv_relax_section): Enable _bfd_riscv_relax_pc when
> --no-relax-gp, we will disable the gp relaxation in the
> _bfd_riscv_relax_pc.
> ---
> bfd/elfnn-riscv.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> index 499f51ee857..77a732b6a08 100644
> --- a/bfd/elfnn-riscv.c
> +++ b/bfd/elfnn-riscv.c
> @@ -4721,7 +4721,9 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
> bool undefined_weak)
> {
> struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table
> (link_info);
> - bfd_vma gp = riscv_global_pointer_value (link_info);
> + bfd_vma gp = htab->params->relax_gp
> + ? riscv_global_pointer_value (link_info)
> + : 0;
>
> BFD_ASSERT (rel->r_offset + 4 <= sec->size);
>
> @@ -4942,7 +4944,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
> || type == R_RISCV_TPREL_LO12_I
> || type == R_RISCV_TPREL_LO12_S)
> relax_func = _bfd_riscv_relax_tls_le;
> - else if (!bfd_link_pic (info) && htab->params->relax_gp
> + else if (!bfd_link_pic (info)
> && (type == R_RISCV_PCREL_HI20
> || type == R_RISCV_PCREL_LO12_I
> || type == R_RISCV_PCREL_LO12_S))
> --
> 2.39.2 (Apple Git-143)
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp.
2023-04-28 6:29 ` Nelson Chu
@ 2023-04-28 7:09 ` Fangrui Song
2023-04-28 7:14 ` Kito Cheng
0 siblings, 1 reply; 6+ messages in thread
From: Fangrui Song @ 2023-04-28 7:09 UTC (permalink / raw)
To: Nelson Chu; +Cc: binutils, jim.wilson.gcc, palmer, kito.cheng
On Thu, Apr 27, 2023 at 11:29 PM Nelson Chu <nelson@rivosinc.com> wrote:
>
> Committed, thanks.
>
> Nelson
Thanks. I cannot find any information about "x0 base relaxation" on
the Internet.
It is worth a test: if I force `bfd_vma gp = 0;`, check-ld
RUNTESTFLAGS='ld-riscv-elf.exp' will still pass :)
> On Fri, Apr 21, 2023 at 4:28 PM Nelson Chu <nelson@rivosinc.com> wrote:
>
> > Let --no-relax-gp only disable the gp relaxation for lui and pcrel
> > relaxations, since x0 base and gp relaxations are different optimizations
> > in fact, but just use the same function to handle.
> >
> > bfd/
> > * elfnn-riscv.c (_bfd_riscv_relax_pc): Like _bfd_riscv_relax_lui,
> > set gp to zero when --no-relax-gp, then we should still keep the
> > x0 base relaxation.
> > (_bfd_riscv_relax_section): Enable _bfd_riscv_relax_pc when
> > --no-relax-gp, we will disable the gp relaxation in the
> > _bfd_riscv_relax_pc.
> > ---
> > bfd/elfnn-riscv.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> > index 499f51ee857..77a732b6a08 100644
> > --- a/bfd/elfnn-riscv.c
> > +++ b/bfd/elfnn-riscv.c
> > @@ -4721,7 +4721,9 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
> > bool undefined_weak)
> > {
> > struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table
> > (link_info);
> > - bfd_vma gp = riscv_global_pointer_value (link_info);
> > + bfd_vma gp = htab->params->relax_gp
> > + ? riscv_global_pointer_value (link_info)
> > + : 0;
> >
> > BFD_ASSERT (rel->r_offset + 4 <= sec->size);
> >
> > @@ -4942,7 +4944,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
> > || type == R_RISCV_TPREL_LO12_I
> > || type == R_RISCV_TPREL_LO12_S)
> > relax_func = _bfd_riscv_relax_tls_le;
> > - else if (!bfd_link_pic (info) && htab->params->relax_gp
> > + else if (!bfd_link_pic (info)
> > && (type == R_RISCV_PCREL_HI20
> > || type == R_RISCV_PCREL_LO12_I
> > || type == R_RISCV_PCREL_LO12_S))
> > --
> > 2.39.2 (Apple Git-143)
> >
> >
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp.
2023-04-28 7:09 ` Fangrui Song
@ 2023-04-28 7:14 ` Kito Cheng
0 siblings, 0 replies; 6+ messages in thread
From: Kito Cheng @ 2023-04-28 7:14 UTC (permalink / raw)
To: Fangrui Song; +Cc: Nelson Chu, binutils, jim.wilson.gcc, palmer, kito.cheng
it called Zero-page Relaxation on psABI spec
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#zero-page-relaxation
On Fri, Apr 28, 2023 at 3:11 PM Fangrui Song <i@maskray.me> wrote:
>
> On Thu, Apr 27, 2023 at 11:29 PM Nelson Chu <nelson@rivosinc.com> wrote:
> >
> > Committed, thanks.
> >
> > Nelson
>
> Thanks. I cannot find any information about "x0 base relaxation" on
> the Internet.
> It is worth a test: if I force `bfd_vma gp = 0;`, check-ld
> RUNTESTFLAGS='ld-riscv-elf.exp' will still pass :)
>
> > On Fri, Apr 21, 2023 at 4:28 PM Nelson Chu <nelson@rivosinc.com> wrote:
> >
> > > Let --no-relax-gp only disable the gp relaxation for lui and pcrel
> > > relaxations, since x0 base and gp relaxations are different optimizations
> > > in fact, but just use the same function to handle.
> > >
> > > bfd/
> > > * elfnn-riscv.c (_bfd_riscv_relax_pc): Like _bfd_riscv_relax_lui,
> > > set gp to zero when --no-relax-gp, then we should still keep the
> > > x0 base relaxation.
> > > (_bfd_riscv_relax_section): Enable _bfd_riscv_relax_pc when
> > > --no-relax-gp, we will disable the gp relaxation in the
> > > _bfd_riscv_relax_pc.
> > > ---
> > > bfd/elfnn-riscv.c | 6 ++++--
> > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> > > index 499f51ee857..77a732b6a08 100644
> > > --- a/bfd/elfnn-riscv.c
> > > +++ b/bfd/elfnn-riscv.c
> > > @@ -4721,7 +4721,9 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
> > > bool undefined_weak)
> > > {
> > > struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table
> > > (link_info);
> > > - bfd_vma gp = riscv_global_pointer_value (link_info);
> > > + bfd_vma gp = htab->params->relax_gp
> > > + ? riscv_global_pointer_value (link_info)
> > > + : 0;
> > >
> > > BFD_ASSERT (rel->r_offset + 4 <= sec->size);
> > >
> > > @@ -4942,7 +4944,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
> > > || type == R_RISCV_TPREL_LO12_I
> > > || type == R_RISCV_TPREL_LO12_S)
> > > relax_func = _bfd_riscv_relax_tls_le;
> > > - else if (!bfd_link_pic (info) && htab->params->relax_gp
> > > + else if (!bfd_link_pic (info)
> > > && (type == R_RISCV_PCREL_HI20
> > > || type == R_RISCV_PCREL_LO12_I
> > > || type == R_RISCV_PCREL_LO12_S))
> > > --
> > > 2.39.2 (Apple Git-143)
> > >
> > >
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-04-28 7:14 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-21 8:28 [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak Nelson Chu
2023-04-21 8:28 ` [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp Nelson Chu
2023-04-28 6:29 ` Nelson Chu
2023-04-28 7:09 ` Fangrui Song
2023-04-28 7:14 ` Kito Cheng
2023-04-28 6:28 ` [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak Nelson Chu
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