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* x86 ISA v3 / v4 coverage
@ 2022-06-02 14:31 Jan Beulich
  2022-06-02 15:29 ` H.J. Lu
  0 siblings, 1 reply; 5+ messages in thread
From: Jan Beulich @ 2022-06-02 14:31 UTC (permalink / raw)
  To: H.J. Lu; +Cc: Binutils

H.J.,

the other day I came to notice two apparent anomalies:

Shouldn't XOP and FMA4 be excluded from v3, just like LWP and TBM are?

Shouldn't AVX512_4FMAPS be excluded from v4, just like AVX512_4VNNIW is?

And is it correct for new ISA additions (like not so long ago AVX512-FP16)
to become part of what is covered by v3 or v4? AMX, for example, was
excluded from v3 when it was added to the code base. And e.g. GFNI is not
part of v2 because there no "umbrella property" (VEX for v3, EVEX for v4)
is checked, but it's strictly a white-listing of Cpu* flags.

I'm afraid all of this once again is unobvious because the specification
is not clear enough.

Jan


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: x86 ISA v3 / v4 coverage
  2022-06-02 14:31 x86 ISA v3 / v4 coverage Jan Beulich
@ 2022-06-02 15:29 ` H.J. Lu
  2022-06-07 13:13   ` Michael Matz
  0 siblings, 1 reply; 5+ messages in thread
From: H.J. Lu @ 2022-06-02 15:29 UTC (permalink / raw)
  To: Jan Beulich; +Cc: Binutils

On Thu, Jun 2, 2022 at 7:31 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> H.J.,
>
> the other day I came to notice two apparent anomalies:
>
> Shouldn't XOP and FMA4 be excluded from v3, just like LWP and TBM are?

Yes, they should be excluded since they don't require v3.

> Shouldn't AVX512_4FMAPS be excluded from v4, just like AVX512_4VNNIW is?

Yes, it should be since it doesn't require v4.

> And is it correct for new ISA additions (like not so long ago AVX512-FP16)
> to become part of what is covered by v3 or v4? AMX, for example, was

AVX512_FP16 requires v4.

> excluded from v3 when it was added to the code base. And e.g. GFNI is not
> part of v2 because there no "umbrella property" (VEX for v3, EVEX for v4)
> is checked, but it's strictly a white-listing of Cpu* flags.
>
> I'm afraid all of this once again is unobvious because the specification
> is not clear enough.

The ISA level is the minimum requirement.  All ISAs listed in the level can
be freely used.

-- 
H.J.

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: x86 ISA v3 / v4 coverage
  2022-06-02 15:29 ` H.J. Lu
@ 2022-06-07 13:13   ` Michael Matz
  2022-06-07 21:39     ` H.J. Lu
  0 siblings, 1 reply; 5+ messages in thread
From: Michael Matz @ 2022-06-07 13:13 UTC (permalink / raw)
  To: H.J. Lu; +Cc: Jan Beulich, Binutils

Hello,

On Thu, 2 Jun 2022, H.J. Lu via Binutils wrote:

> On Thu, Jun 2, 2022 at 7:31 AM Jan Beulich <jbeulich@suse.com> wrote:
> >
> > H.J.,
> >
> > the other day I came to notice two apparent anomalies:
> >
> > Shouldn't XOP and FMA4 be excluded from v3, just like LWP and TBM are?
> 
> Yes, they should be excluded since they don't require v3.
> 
> > Shouldn't AVX512_4FMAPS be excluded from v4, just like AVX512_4VNNIW is?
> 
> Yes, it should be since it doesn't require v4.
> 
> > And is it correct for new ISA additions (like not so long ago AVX512-FP16)
> > to become part of what is covered by v3 or v4? AMX, for example, was
> 
> AVX512_FP16 requires v4.

But it can't be part of v3 or v4.  New ISA additions never can become 
part of an existing ISA level, once it's released it's fixated.  I just 
wanted to state this explicitely because it seems Jan used "part of vX" 
to mean "binaries stating to require vX can use ISA feature so-and-so", 
whereas you seem to mean "ISA feature so-and-so requires at least vX".


Ciao,
Michael.

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: x86 ISA v3 / v4 coverage
  2022-06-07 13:13   ` Michael Matz
@ 2022-06-07 21:39     ` H.J. Lu
  2022-06-08 11:09       ` Michael Matz
  0 siblings, 1 reply; 5+ messages in thread
From: H.J. Lu @ 2022-06-07 21:39 UTC (permalink / raw)
  To: Michael Matz; +Cc: Jan Beulich, Binutils

On Tue, Jun 7, 2022 at 6:13 AM Michael Matz <matz@suse.de> wrote:
>
> Hello,
>
> On Thu, 2 Jun 2022, H.J. Lu via Binutils wrote:
>
> > On Thu, Jun 2, 2022 at 7:31 AM Jan Beulich <jbeulich@suse.com> wrote:
> > >
> > > H.J.,
> > >
> > > the other day I came to notice two apparent anomalies:
> > >
> > > Shouldn't XOP and FMA4 be excluded from v3, just like LWP and TBM are?
> >
> > Yes, they should be excluded since they don't require v3.
> >
> > > Shouldn't AVX512_4FMAPS be excluded from v4, just like AVX512_4VNNIW is?
> >
> > Yes, it should be since it doesn't require v4.
> >
> > > And is it correct for new ISA additions (like not so long ago AVX512-FP16)
> > > to become part of what is covered by v3 or v4? AMX, for example, was
> >
> > AVX512_FP16 requires v4.
>
> But it can't be part of v3 or v4.  New ISA additions never can become
> part of an existing ISA level, once it's released it's fixated.  I just
> wanted to state this explicitely because it seems Jan used "part of vX"
> to mean "binaries stating to require vX can use ISA feature so-and-so",
> whereas you seem to mean "ISA feature so-and-so requires at least vX".
>

This is because the ISA level marker is a minimum requirement.


-- 
H.J.

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: x86 ISA v3 / v4 coverage
  2022-06-07 21:39     ` H.J. Lu
@ 2022-06-08 11:09       ` Michael Matz
  0 siblings, 0 replies; 5+ messages in thread
From: Michael Matz @ 2022-06-08 11:09 UTC (permalink / raw)
  To: H.J. Lu; +Cc: Jan Beulich, Binutils

Hello,

On Tue, 7 Jun 2022, H.J. Lu wrote:

> > > > Shouldn't AVX512_4FMAPS be excluded from v4, just like AVX512_4VNNIW is?
> > >
> > > Yes, it should be since it doesn't require v4.
> > >
> > > > And is it correct for new ISA additions (like not so long ago AVX512-FP16)
> > > > to become part of what is covered by v3 or v4? AMX, for example, was
> > >
> > > AVX512_FP16 requires v4.
> >
> > But it can't be part of v3 or v4.  New ISA additions never can become
> > part of an existing ISA level, once it's released it's fixated.  I just
> > wanted to state this explicitely because it seems Jan used "part of vX"
> > to mean "binaries stating to require vX can use ISA feature so-and-so",
> > whereas you seem to mean "ISA feature so-and-so requires at least vX".
> 
> This is because the ISA level marker is a minimum requirement.

Then we are in agreement.  I merely wouldn't call that "be part of", like 
I wouldn't call AVX to be a part of SSE2.


Ciao,
Michael.

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2022-06-08 11:09 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-02 14:31 x86 ISA v3 / v4 coverage Jan Beulich
2022-06-02 15:29 ` H.J. Lu
2022-06-07 13:13   ` Michael Matz
2022-06-07 21:39     ` H.J. Lu
2022-06-08 11:09       ` Michael Matz

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