[PATCH 0/2] RISC-V: QUICK fix on Li's Zhinx implementation

[Tsukasa OI <research_trasio@irq.a4lg.com>]

Hello,

I understand that my Zfinx fixes + Zfhmin/Zhinxmin patchset requires
some time to review.

Meanwhile, there's a quick fix to Li's Zhinx implementation.  My
patchset already contains equivalent fix but I extracted the most
important one (that should definately be fixed before 2.39).

My combined float patchset:
<https://sourceware.org/pipermail/binutils/2022-June/121138.html>

Li Weiwei's Zhinx implementation:
<https://sourceware.org/pipermail/binutils/2022-May/121038.html>



PATCH 1:

Again, this is a duplicate of:
<https://sourceware.org/pipermail/binutils/2022-June/121115.html>
<https://sourceware.org/pipermail/binutils/2022-June/121139.html> (in my combined fixes)

PATCH 2 required a test to give -march including **both** Zqinx and
Zhinx.  As a result, this patch is mandatory for the next patch is to be
applied.  Otherwise, it would need likely non-canonical ordering on
-march.



PATCH 2:

Following instructions have INSN_CLASS_D_AND_ZFH_INX:

-   fcvt.h.d
-   fcvt.d.h

Following instructions have INSN_CLASS_Q_AND_ZFH_INX:

-   fcvt.h.q
-   fcvt.q.h

I noticed that feature gates on those instruction classes are most
likely incorrect.

Quoting ISA Manual 24.5 "Zhinxmin":
> If the Zdinx extension is present, the FCVT.D.H and FCVT.H.D
> instructions are also included.

Although no such limitation is explicitly specified on "Zhinx" itself,
it's very unlikely that FCVT.D.H and FCVT.H.D can be supported without
Zdinx extension.

Quoting Manual 16.3 "Half-Precision Conversion and Move Instructions" from Zfh:
> If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-
> precision floating-point number to a double-precision floating-point
> number, or vice-versa, respectively. If the Q extension is present,
> FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number
> to a quad-precision floating-point number, or vice-versa,
> respectively.

And 24.4 "Zhinx":
> The Zhinx extension adds all of the instructions that the Zfh
> extension adds, except for the transfer instructions FLH, FSH,
> FMV.H.X, and FMV.X.H. The Zhinx variants of these Zfh-extension
> instructions have the same semantics, except that (cont...)


On INSN_CLASS_D_AND_ZFH_INX:

Li's implementation        : (D && Zfh) || Zhinx
This patch                 : (D && Zfh) || (Zdinx && Zhinx)
My combined float patchset : (D && Zfhmin) || (Zdinx && Zhinxmin)

This commit fixes feature gates and their diagnostics.



Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Add 'H' to canonical extension ordering
  RISC-V: Fix requirement handling on Zhinx+{D,Q}

 bfd/elfxx-riscv.c                        | 32 +++++++++++++++++++-----
 gas/testsuite/gas/riscv/fp-zhinx-insns.d |  2 +-
 2 files changed, 27 insertions(+), 7 deletions(-)


base-commit: c8eab1d7c92ad72089c98e5753ebc96419e3674a
-- 
2.34.1