[PATCH v2 0/1] RISC-V: QUICK fix on Li's Zhinx implementation

[Tsukasa OI <research_trasio@irq.a4lg.com>]

This is a backup plan if my main Zfinx fixes will not make it to
Binutils 2.39 and contains the most important fix (to most likely wrong
feature gate) to Li's Zhinx implementation.

Because of this, this is incompatible with my main patchset
("RISC-V: Combined floating point enhancements") which contains all of
Zfinx/Zhinx fixes.

v1:
<https://sourceware.org/pipermail/binutils/2022-June/121170.html>
CURRENT (GitHub):
<https://github.com/a4lg/binutils-gdb/tree/riscv-zhinx-quick-fix>


This is functionally equivalent to v1 but contains a minor change.

[CHANGES: v1 -> v2]
-   Change error message to enable i18n.
-   Removed original PATCH 1 because it is merged.
    <https://sourceware.org/pipermail/binutils/2022-June/121342.html>




Tsukasa OI (1):
  RISC-V: Fix requirement handling on Zhinx+{D,Q}

 bfd/elfxx-riscv.c                        | 30 ++++++++++++++++++++----
 gas/testsuite/gas/riscv/fp-zhinx-insns.d |  2 +-
 2 files changed, 26 insertions(+), 6 deletions(-)


base-commit: 54603ee2aeaf248220f0f440c322ff02e98cd403
-- 
2.34.1