From: Nelson Chu <nelson.chu@sifive.com>
To: Kito Cheng <kito.cheng@gmail.com>
Cc: Tsukasa OI <research_trasio@irq.a4lg.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Kito Cheng <kito.cheng@sifive.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Binutils <binutils@sourceware.org>
Subject: Re: [PATCH v3 1/2] RISC-V: Fix requirement handling on Zhinx+{D,Q}
Date: Thu, 7 Jul 2022 12:25:08 +0800 [thread overview]
Message-ID: <CAJYME4FSNTXBeXPGQNOwD1J9iA6F+wcXz8+MnWvmtfjGAC0X5Q@mail.gmail.com> (raw)
In-Reply-To: <CA+yXCZC8-Stq0U9U8gSXR_FS_1TDJtx1LNQxD9EVdF=zFAT8ug@mail.gmail.com>
OK, regressions passed so committed.
Thanks
Nelson
On Thu, Jul 7, 2022 at 11:02 AM Kito Cheng <kito.cheng@gmail.com> wrote:
>
> LGTM
>
> On Fri, Jun 24, 2022 at 11:52 AM Tsukasa OI via Binutils
> <binutils@sourceware.org> wrote:
> >
> > This commit fixes how instructions are masked on Zhinx+Z{d,q}inx.
> > fcvt.h.d and fcvt.d.h require ((D&&Zfh)||(Zdinx&&Zhinx)) and
> > fcvt.h.q and fcvt.q.h require ((Q&&Zfh)||(Zqinx&&Zhinx)).
> >
> > bfd/ChangeLog:
> >
> > * elfxx-riscv.c (riscv_multi_subset_supports): Fix feature gate
> > on INSN_CLASS_{D,Q}_AND_ZFH_INX.
> > (riscv_multi_subset_supports_ext): Fix feature gate diagnostics
> > on INSN_CLASS_{D,Q}_AND_ZFH_INX.
> >
> > gas/ChangeLog:
> >
> > * testsuite/gas/riscv/fp-zhinx-insns.d: Add Zqinx to -march
> > for proper testing.
> > ---
> > bfd/elfxx-riscv.c | 30 ++++++++++++++++++++----
> > gas/testsuite/gas/riscv/fp-zhinx-insns.d | 2 +-
> > 2 files changed, 26 insertions(+), 6 deletions(-)
> >
> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > index f920e0ce9ff..308516c3e60 100644
> > --- a/bfd/elfxx-riscv.c
> > +++ b/bfd/elfxx-riscv.c
> > @@ -2337,15 +2337,17 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
> > return riscv_subset_supports (rps, "zfh");
> > case INSN_CLASS_ZFH_OR_ZHINX:
> > return riscv_subset_supports (rps, "zfh")
> > - || riscv_subset_supports (rps, "zhinx");
> > + || riscv_subset_supports (rps, "zhinx");
> > case INSN_CLASS_D_AND_ZFH_INX:
> > return (riscv_subset_supports (rps, "d")
> > && riscv_subset_supports (rps, "zfh"))
> > - || riscv_subset_supports (rps, "zhinx");
> > + || (riscv_subset_supports (rps, "zdinx")
> > + && riscv_subset_supports (rps, "zhinx"));
> > case INSN_CLASS_Q_AND_ZFH_INX:
> > return (riscv_subset_supports (rps, "q")
> > && riscv_subset_supports (rps, "zfh"))
> > - || riscv_subset_supports (rps, "zhinx");
> > + || (riscv_subset_supports (rps, "zqinx")
> > + && riscv_subset_supports (rps, "zhinx"));
> > case INSN_CLASS_ZBA:
> > return riscv_subset_supports (rps, "zba");
> > case INSN_CLASS_ZBB:
> > @@ -2492,9 +2494,27 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
> > case INSN_CLASS_ZFH_OR_ZHINX:
> > return _("zfh' or 'zhinx");
> > case INSN_CLASS_D_AND_ZFH_INX:
> > - return _("('d' and 'zfh') or 'zhinx");
> > + if (riscv_subset_supports (rps, "zfh"))
> > + return "d";
> > + else if (riscv_subset_supports (rps, "d"))
> > + return "zfh";
> > + else if (riscv_subset_supports (rps, "zhinx"))
> > + return "zdinx";
> > + else if (riscv_subset_supports (rps, "zdinx"))
> > + return "zhinx";
> > + else
> > + return _("zfh' and `d', or `zhinx' and `zdinx");
> > case INSN_CLASS_Q_AND_ZFH_INX:
> > - return _("('q' and 'zfh') or 'zhinx");
> > + if (riscv_subset_supports (rps, "zfh"))
> > + return "q";
> > + else if (riscv_subset_supports (rps, "q"))
> > + return "zfh";
> > + else if (riscv_subset_supports (rps, "zhinx"))
> > + return "zqinx";
> > + else if (riscv_subset_supports (rps, "zqinx"))
> > + return "zhinx";
> > + else
> > + return _("zfh' and `q', or `zhinx' and `zqinx");
> > case INSN_CLASS_H:
> > return _("h");
> > default:
> > diff --git a/gas/testsuite/gas/riscv/fp-zhinx-insns.d b/gas/testsuite/gas/riscv/fp-zhinx-insns.d
> > index 6e1c40e65f5..2592d8c74e2 100644
> > --- a/gas/testsuite/gas/riscv/fp-zhinx-insns.d
> > +++ b/gas/testsuite/gas/riscv/fp-zhinx-insns.d
> > @@ -1,4 +1,4 @@
> > -#as: -march=rv64ima_zhinx
> > +#as: -march=rv64ima_zqinx_zhinx
> > #source: fp-zhinx-insns.s
> > #objdump: -dr
> >
> > --
> > 2.34.1
> >
next prev parent reply other threads:[~2022-07-07 4:25 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-05 4:43 [PATCH 0/2] RISC-V: QUICK fix on Li's Zhinx implementation Tsukasa OI
2022-06-05 4:43 ` [PATCH 1/2] RISC-V: Add 'H' to canonical extension ordering Tsukasa OI
2022-06-22 10:39 ` Nelson Chu
2022-06-22 11:08 ` Tsukasa OI
2022-06-05 4:43 ` [PATCH 2/2] RISC-V: Fix requirement handling on Zhinx+{D,Q} Tsukasa OI
2022-06-24 2:59 ` [PATCH v2 0/1] RISC-V: QUICK fix on Li's Zhinx implementation Tsukasa OI
2022-06-24 2:59 ` [PATCH v2 1/1] RISC-V: Fix requirement handling on Zhinx+{D,Q} Tsukasa OI
2022-06-24 3:51 ` [PATCH v3 0/2] RISC-V: QUICK fix on Li's Zhinx implementation Tsukasa OI
2022-06-24 3:51 ` [PATCH v3 1/2] RISC-V: Fix requirement handling on Zhinx+{D,Q} Tsukasa OI
2022-07-07 3:02 ` Kito Cheng
2022-07-07 4:25 ` Nelson Chu [this message]
2022-06-24 3:51 ` [PATCH v3 2/2] RISC-V: Reorder Zhinx extension Tsukasa OI
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