* [PATCH 1/2] RISC-V: Make `zip'/`unzip' on Zbkb non-aliases
2022-07-09 3:50 [PATCH 0/2] RISC-V: Make some instruction non-aliases to fix a disassembler issue Tsukasa OI
@ 2022-07-09 3:50 ` Tsukasa OI
2022-07-09 3:50 ` [PATCH 2/2] RISC-V: Make `fence.tso' a non-alias Tsukasa OI
1 sibling, 0 replies; 3+ messages in thread
From: Tsukasa OI @ 2022-07-09 3:50 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
`zip'/`unzip' are specialized forms of `shfli'/`unshfli' instructions
respectively. However, because both `shfli' and `unshfli' are not
ratified (in generalized forms), disassembling `zip'/`unzip' on
RV32_Zbkb with `-M no-aliases' option makes disassembly dumps with
`.4byte' (an unrecognized instruction), not `zip'/`unzip'.
This commit makes `zip'/`unzip' non-aliases until generalized forms of
`shfli' and `unshfli' are ratified.
gas/ChangeLog:
* testsuite/gas/riscv/zbkb-32.d: Make sure that all instructions
in RV32_Zbkb are non-aliases and disassembled correctly.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Make `zip'/`unzip' instructions
on RV32_Zbkb non-aliases to fix a disassembler issue.
---
gas/testsuite/gas/riscv/zbkb-32.d | 2 +-
opcodes/riscv-opc.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gas/testsuite/gas/riscv/zbkb-32.d b/gas/testsuite/gas/riscv/zbkb-32.d
index c2718a0965a..c3fd09f9274 100644
--- a/gas/testsuite/gas/riscv/zbkb-32.d
+++ b/gas/testsuite/gas/riscv/zbkb-32.d
@@ -1,6 +1,6 @@
#as: -march=rv32i_zbkb
#source: zbkb-32.s
-#objdump: -d
+#objdump: -d -M no-aliases
.*:[ ]+file format .*
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2f9945aa930..6c5b2eaf524 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -942,8 +942,8 @@ const struct riscv_opcode riscv_opcodes[] =
{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
{"brev8", 32, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
{"brev8", 64, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
-{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
-{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
{"pack", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
{"packh", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
{"packw", 64, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH 2/2] RISC-V: Make `fence.tso' a non-alias
2022-07-09 3:50 [PATCH 0/2] RISC-V: Make some instruction non-aliases to fix a disassembler issue Tsukasa OI
2022-07-09 3:50 ` [PATCH 1/2] RISC-V: Make `zip'/`unzip' on Zbkb non-aliases Tsukasa OI
@ 2022-07-09 3:50 ` Tsukasa OI
1 sibling, 0 replies; 3+ messages in thread
From: Tsukasa OI @ 2022-07-09 3:50 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
While `fence.tso' is a subset of original `FENCE' instruction in RISC-V
ISA, `fence' instruction as defined in the GNU Binutils (constrained to
fm=0b0000) is not a superset of `fence.tso'. As a result, it resulted
in `.4byte' when disassembled with `no-aliases` option.
This commit makes `fence.tso' instruction a non-alias.
gas/ChangeLog:
* testsuite/gas/riscv/fence-tso.d: Make sure that `fence.tso'
is currently not an alias.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Make `fence.tso' instruction
a non-alias.
---
gas/testsuite/gas/riscv/fence-tso.d | 2 +-
opcodes/riscv-opc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gas/testsuite/gas/riscv/fence-tso.d b/gas/testsuite/gas/riscv/fence-tso.d
index ef8a4cdd1c9..00170f1259e 100644
--- a/gas/testsuite/gas/riscv/fence-tso.d
+++ b/gas/testsuite/gas/riscv/fence-tso.d
@@ -1,5 +1,5 @@
#as: -march=rv32ic
-#objdump: -dr
+#objdump: -dr -M no-aliases
.*:[ ]+file format .*
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6c5b2eaf524..50a51b40d69 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -421,7 +421,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"fence", 0, INSN_CLASS_I, "", MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS },
{"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
{"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 },
-{"fence.tso", 0, INSN_CLASS_I, "", MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, INSN_ALIAS },
+{"fence.tso", 0, INSN_CLASS_I, "", MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, 0 },
{"rdcycle", 0, INSN_CLASS_I, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
{"rdinstret", 0, INSN_CLASS_I, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
{"rdtime", 0, INSN_CLASS_I, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread