* [PATCH 0/1] RISC-V: Fix RV32Q conflict
@ 2022-02-07 3:31 Tsukasa OI
2022-02-07 3:31 ` [PATCH 1/1] " Tsukasa OI
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Tsukasa OI @ 2022-02-07 3:31 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit allows combination of RV32 + 'Q' extension (IEEE 754
binary128 floating point number support).
This combination is no longer prohibited by the ISA Manual.
This restriction is introduced in binutils' RV32E support commit
7f99954970001cfc1b155d877ac2966d77e2c647. At that time,
the latest ratified version of the RISC-V ISA Manual (version 2.2)
stated that 'Q' extension requires RV64IFD.
However, the next ratified version of the RISC-V ISA Manual
(20190608-Base-Ratified) removed such limitation.
I did check the version of 'Q' extension (RV32Q is allowed on 'Q'
extension version 2.2 or later) but it may be too pedant.
This is because change (removal of RV64IFD dependency) seemed irrevant
to version changes but only a part of "embellishment" process as
described by riscv-isa-manual commit
013ba6dc8a504ee4ad7bee42554fecaef7ba797f.
Quoting preface of 20190608-Base-Ratified (would analogously to 'Q'),
> Incremented the version numbers of the F and D extensions to 2.2,
> reflecting that version 2.1 changed the canonical NaN, and version 2.2
> defined the NaN-boxing scheme and changed the definition of the FMIN
> and FMAX instructions.
Not checking the version number (just allowing RV32Q entirely) may be
an option.
References:
GNU Binutils:
Commit 7f99954970001cfc1b155d877ac2966d77e2c647
<https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=7f99954970001cfc1b155d877ac2966d77e2c647>
The RISC-V ISA Manual:
version 2.2
<https://github.com/riscv/riscv-isa-manual/releases?q=2.2>
version 20190608-Base-Ratified
<https://github.com/riscv/riscv-isa-manual/releases?q=Ratified-IMFDQC-and-Priv-v1.11>
commit 013ba6dc8a504ee4ad7bee42554fecaef7ba797f:
<https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f>
Tsukasa OI (1):
RISC-V: Fix RV32Q conflict
bfd/elfxx-riscv.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
base-commit: 6a9d08661b361e497baa76dd6d8685f2cb593adb
--
2.32.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/1] RISC-V: Fix RV32Q conflict
2022-02-07 3:31 [PATCH 0/1] RISC-V: Fix RV32Q conflict Tsukasa OI
@ 2022-02-07 3:31 ` Tsukasa OI
2022-02-07 7:48 ` [PATCH 0/1] " Jan Beulich
2022-02-27 8:51 ` [PATCH v2 " Tsukasa OI
2 siblings, 0 replies; 9+ messages in thread
From: Tsukasa OI @ 2022-02-07 3:31 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit makes RV32 + 'Q' extension (version 2.2 or later) not
conflicting since this combination is no longer prohibited by the
specification.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Remove conflict
detection that prohibits RV32Q on 'Q' version 2.2 or later.
---
bfd/elfxx-riscv.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9f52bb545ac..ca4aa8ce5cc 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1892,10 +1892,11 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
no_conflict = false;
}
if (riscv_lookup_subset (rps->subset_list, "q", &subset)
+ && (subset->major_version < 2 || (subset->major_version == 2
+ && subset->minor_version < 2))
&& xlen < 64)
{
- rps->error_handler
- (_("rv%d does not support the `q' extension"), xlen);
+ rps->error_handler (_("rv%d does not support the `q' extension"), xlen);
no_conflict = false;
}
if (riscv_lookup_subset (rps->subset_list, "e", &subset)
--
2.32.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/1] RISC-V: Fix RV32Q conflict
2022-02-07 3:31 [PATCH 0/1] RISC-V: Fix RV32Q conflict Tsukasa OI
2022-02-07 3:31 ` [PATCH 1/1] " Tsukasa OI
@ 2022-02-07 7:48 ` Jan Beulich
2022-02-07 10:17 ` Tsukasa OI
2022-02-27 8:51 ` [PATCH v2 " Tsukasa OI
2 siblings, 1 reply; 9+ messages in thread
From: Jan Beulich @ 2022-02-07 7:48 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
On 07.02.2022 04:31, Tsukasa OI via Binutils wrote:
> This commit allows combination of RV32 + 'Q' extension (IEEE 754
> binary128 floating point number support).
>
> This combination is no longer prohibited by the ISA Manual.
>
> This restriction is introduced in binutils' RV32E support commit
> 7f99954970001cfc1b155d877ac2966d77e2c647. At that time,
> the latest ratified version of the RISC-V ISA Manual (version 2.2)
> stated that 'Q' extension requires RV64IFD.
>
> However, the next ratified version of the RISC-V ISA Manual
> (20190608-Base-Ratified) removed such limitation.
Ah yes, one of the anomalies I did notice a while ago and didn't get
around to writing mail about, yet. A related anomaly looks to be that
RV32E excludes F, without me being able to find respective wording in
the spec.
Jan
> I did check the version of 'Q' extension (RV32Q is allowed on 'Q'
> extension version 2.2 or later) but it may be too pedant.
>
> This is because change (removal of RV64IFD dependency) seemed irrevant
> to version changes but only a part of "embellishment" process as
> described by riscv-isa-manual commit
> 013ba6dc8a504ee4ad7bee42554fecaef7ba797f.
>
> Quoting preface of 20190608-Base-Ratified (would analogously to 'Q'),
>
>> Incremented the version numbers of the F and D extensions to 2.2,
>> reflecting that version 2.1 changed the canonical NaN, and version 2.2
>> defined the NaN-boxing scheme and changed the definition of the FMIN
>> and FMAX instructions.
>
> Not checking the version number (just allowing RV32Q entirely) may be
> an option.
>
>
> References:
>
> GNU Binutils:
> Commit 7f99954970001cfc1b155d877ac2966d77e2c647
> <https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=7f99954970001cfc1b155d877ac2966d77e2c647>
>
> The RISC-V ISA Manual:
> version 2.2
> <https://github.com/riscv/riscv-isa-manual/releases?q=2.2>
> version 20190608-Base-Ratified
> <https://github.com/riscv/riscv-isa-manual/releases?q=Ratified-IMFDQC-and-Priv-v1.11>
> commit 013ba6dc8a504ee4ad7bee42554fecaef7ba797f:
> <https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f>
>
>
>
>
> Tsukasa OI (1):
> RISC-V: Fix RV32Q conflict
>
> bfd/elfxx-riscv.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
>
> base-commit: 6a9d08661b361e497baa76dd6d8685f2cb593adb
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/1] RISC-V: Fix RV32Q conflict
2022-02-07 7:48 ` [PATCH 0/1] " Jan Beulich
@ 2022-02-07 10:17 ` Tsukasa OI
0 siblings, 0 replies; 9+ messages in thread
From: Tsukasa OI @ 2022-02-07 10:17 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On 2022/02/07 16:48, Jan Beulich wrote:
> On 07.02.2022 04:31, Tsukasa OI via Binutils wrote:
>> This commit allows combination of RV32 + 'Q' extension (IEEE 754
>> binary128 floating point number support).
>>
>> This combination is no longer prohibited by the ISA Manual.
>>
>> This restriction is introduced in binutils' RV32E support commit
>> 7f99954970001cfc1b155d877ac2966d77e2c647. At that time,
>> the latest ratified version of the RISC-V ISA Manual (version 2.2)
>> stated that 'Q' extension requires RV64IFD.
>>
>> However, the next ratified version of the RISC-V ISA Manual
>> (20190608-Base-Ratified) removed such limitation.
>
> Ah yes, one of the anomalies I did notice a while ago and didn't get
> around to writing mail about, yet. A related anomaly looks to be that
> RV32E excludes F, without me being able to find respective wording in
> the spec.
ISA Manual, version 2.2 (3.3. RV32E Extensions):
> RV32E can be extended with the M, A, and C user-level standard
> extensions.
Yes, it prohibits (not only but including) F standard extension.
ISA Manual, version 20190608-Base-Ratified (4.2. RV32E Instruction Set):
> RV32E can be combined with all current standard extensions. Defining
> the F, D, and Q extensions as having a 16-entry floating point
> register file when combined with RV32E was considered but decided
> against. To support systems with reduced floating-point register
> state, we intend to define a “Zfinx” extension (...cont...)
It seems... not intended but not directly prohibited either?
Still, there is an ABI conflict between RV32E and use of floating point
registers so (even if not prohibited) it wouldn't be the same as this
patchset (cf. riscv_set_abi_by_arch function in gas/config/tc-riscv.c).
Tsukasa
>
> Jan
>
>> I did check the version of 'Q' extension (RV32Q is allowed on 'Q'
>> extension version 2.2 or later) but it may be too pedant.
>>
>> This is because change (removal of RV64IFD dependency) seemed irrevant
>> to version changes but only a part of "embellishment" process as
>> described by riscv-isa-manual commit
>> 013ba6dc8a504ee4ad7bee42554fecaef7ba797f.
>>
>> Quoting preface of 20190608-Base-Ratified (would analogously to 'Q'),
>>
>>> Incremented the version numbers of the F and D extensions to 2.2,
>>> reflecting that version 2.1 changed the canonical NaN, and version 2.2
>>> defined the NaN-boxing scheme and changed the definition of the FMIN
>>> and FMAX instructions.
>>
>> Not checking the version number (just allowing RV32Q entirely) may be
>> an option.
>>
>>
>> References:
>>
>> GNU Binutils:
>> Commit 7f99954970001cfc1b155d877ac2966d77e2c647
>> <https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=7f99954970001cfc1b155d877ac2966d77e2c647>
>>
>> The RISC-V ISA Manual:
>> version 2.2
>> <https://github.com/riscv/riscv-isa-manual/releases?q=2.2>
>> version 20190608-Base-Ratified
>> <https://github.com/riscv/riscv-isa-manual/releases?q=Ratified-IMFDQC-and-Priv-v1.11>
>> commit 013ba6dc8a504ee4ad7bee42554fecaef7ba797f:
>> <https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f>
>>
>>
>>
>>
>> Tsukasa OI (1):
>> RISC-V: Fix RV32Q conflict
>>
>> bfd/elfxx-riscv.c | 5 +++--
>> 1 file changed, 3 insertions(+), 2 deletions(-)
>>
>>
>> base-commit: 6a9d08661b361e497baa76dd6d8685f2cb593adb
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 0/1] RISC-V: Fix RV32Q conflict
2022-02-07 3:31 [PATCH 0/1] RISC-V: Fix RV32Q conflict Tsukasa OI
2022-02-07 3:31 ` [PATCH 1/1] " Tsukasa OI
2022-02-07 7:48 ` [PATCH 0/1] " Jan Beulich
@ 2022-02-27 8:51 ` Tsukasa OI
2022-02-27 8:51 ` [PATCH v2 1/1] " Tsukasa OI
2022-05-24 9:48 ` [PING][PATCH v2 0/1] " Tsukasa OI
2 siblings, 2 replies; 9+ messages in thread
From: Tsukasa OI @ 2022-02-27 8:51 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Nelson Chu, Jan Beulich; +Cc: binutils
[v2]
This commit allows combination of RV32 + 'Q' extension (IEEE 754
binary128 floating point number support), version 2.2 or later.
This combination is no longer prohibited by the specification.
v1:
<https://sourceware.org/pipermail/binutils/2022-February/119655.html>
Changes: v1 -> v2
- Changed/renamed testcase so that no failure occurs.
RV32IQ with old ISA (version 2.2 w/ 'Q' 2.0) is prohibited.
- Added testcase so that RV32IQ with recent ISA succeeds.
RV32IQ with new ISA (version 20190608 w/ 'Q' 2.2) is allowed.
- Added testcases for RV32I + 'Q' per extension version
- 'Q' extension version 2.0 with RV32I is prohibited.
("rv32iq2" means RV32I + Q version 2".0" so also prohibited.)
- 'Q' extension version 2.2 with RV32I is allowed.
As I noted in v1, this implementation might be too pedantic.
An option is to allow RV32IQ entirely (regardless of version numbers).
Tsukasa OI (1):
RISC-V: Fix RV32Q conflict
bfd/elfxx-riscv.c | 5 +++--
gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d | 3 +++
gas/testsuite/gas/riscv/march-fail-rv32iq.d | 3 ---
gas/testsuite/gas/riscv/march-fail-rv32iq2.d | 3 +++
gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d | 3 +++
.../riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} | 0
gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d | 5 +++++
gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d | 5 +++++
8 files changed, 22 insertions(+), 5 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq.d
create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2.d
create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
rename gas/testsuite/gas/riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} (100%)
create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
base-commit: b275570803cefba388595bc42b75b68403eb86f1
--
2.32.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/1] RISC-V: Fix RV32Q conflict
2022-02-27 8:51 ` [PATCH v2 " Tsukasa OI
@ 2022-02-27 8:51 ` Tsukasa OI
2022-05-24 12:04 ` Kito Cheng
2022-05-25 3:23 ` Nelson Chu
2022-05-24 9:48 ` [PING][PATCH v2 0/1] " Tsukasa OI
1 sibling, 2 replies; 9+ messages in thread
From: Tsukasa OI @ 2022-02-27 8:51 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Nelson Chu, Jan Beulich; +Cc: binutils
This commit makes RV32 + 'Q' extension (version 2.2 or later) not
conflicting since this combination is no longer prohibited by the
specification.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Remove conflict
detection that prohibits RV32Q on 'Q' version 2.2 or later.
gas/ChangeLog:
* testsuite/gas/riscv/march-fail-rv32iq.d: Removed.
* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq2p0.d: New test
showing RV32IQ fails on 'Q' extension version 2.0.
* testsuite/gas/riscv/march-fail-rv32iq2p0.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq2.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d: New test
showing RV32IQ fails on ISA specification version 2.2.
* testsuite/gas/riscv/march-ok-rv32iq2p2.d: New test
showing RV32IQ succesds on 'Q' extension version 2.2.
* testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d: New test
showing RV32IQ succesds on ISA specification 20190608.
---
bfd/elfxx-riscv.c | 5 +++--
gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d | 3 +++
gas/testsuite/gas/riscv/march-fail-rv32iq.d | 3 ---
gas/testsuite/gas/riscv/march-fail-rv32iq2.d | 3 +++
gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d | 3 +++
.../riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} | 0
gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d | 5 +++++
gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d | 5 +++++
8 files changed, 22 insertions(+), 5 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq.d
create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2.d
create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
rename gas/testsuite/gas/riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} (100%)
create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 2915b74dd0f..17567b2af54 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1880,10 +1880,11 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
no_conflict = false;
}
if (riscv_lookup_subset (rps->subset_list, "q", &subset)
+ && (subset->major_version < 2 || (subset->major_version == 2
+ && subset->minor_version < 2))
&& xlen < 64)
{
- rps->error_handler
- (_("rv%d does not support the `q' extension"), xlen);
+ rps->error_handler (_("rv%d does not support the `q' extension"), xlen);
no_conflict = false;
}
if (riscv_lookup_subset (rps->subset_list, "e", &subset)
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d b/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
new file mode 100644
index 00000000000..16451b0f43f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
@@ -0,0 +1,3 @@
+#as: -misa-spec=2.2 -march=rv32iq
+#source: empty.s
+#error_output: march-fail-rv32iq2p0.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.d b/gas/testsuite/gas/riscv/march-fail-rv32iq.d
deleted file mode 100644
index c289c695cad..00000000000
--- a/gas/testsuite/gas/riscv/march-fail-rv32iq.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32iq
-#source: empty.s
-#error_output: march-fail-rv32iq.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq2.d b/gas/testsuite/gas/riscv/march-fail-rv32iq2.d
new file mode 100644
index 00000000000..34fce730ce5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-fail-rv32iq2.d
@@ -0,0 +1,3 @@
+#as: -march=rv32iq2
+#source: empty.s
+#error_output: march-fail-rv32iq2p0.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
new file mode 100644
index 00000000000..916f845a970
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
@@ -0,0 +1,3 @@
+#as: -march=rv32iq2p0
+#source: empty.s
+#error_output: march-fail-rv32iq2p0.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.l b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.l
similarity index 100%
rename from gas/testsuite/gas/riscv/march-fail-rv32iq.l
rename to gas/testsuite/gas/riscv/march-fail-rv32iq2p0.l
diff --git a/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d b/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
new file mode 100644
index 00000000000..8322957948d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
@@ -0,0 +1,5 @@
+#as: -misa-spec=20190608 -march=rv32iq
+#objdump: -dr
+#source: empty.s
+
+.*: file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d b/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
new file mode 100644
index 00000000000..1a922bfaa4d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
@@ -0,0 +1,5 @@
+#as: -march=rv32iq2p2
+#objdump: -dr
+#source: empty.s
+
+.*: file format elf32-(little|big)riscv
--
2.32.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PING][PATCH v2 0/1] RISC-V: Fix RV32Q conflict
2022-02-27 8:51 ` [PATCH v2 " Tsukasa OI
2022-02-27 8:51 ` [PATCH v2 1/1] " Tsukasa OI
@ 2022-05-24 9:48 ` Tsukasa OI
1 sibling, 0 replies; 9+ messages in thread
From: Tsukasa OI @ 2022-05-24 9:48 UTC (permalink / raw)
To: Kito Cheng, Palmer Dabbelt, Nelson Chu; +Cc: Binutils
On 2022/02/27 17:51, Tsukasa OI wrote:
> [v2]
>
> This commit allows combination of RV32 + 'Q' extension (IEEE 754
> binary128 floating point number support), version 2.2 or later.
>
> This combination is no longer prohibited by the specification.
>
> v1:
> <https://sourceware.org/pipermail/binutils/2022-February/119655.html>
>
> Changes: v1 -> v2
> - Changed/renamed testcase so that no failure occurs.
> RV32IQ with old ISA (version 2.2 w/ 'Q' 2.0) is prohibited.
> - Added testcase so that RV32IQ with recent ISA succeeds.
> RV32IQ with new ISA (version 20190608 w/ 'Q' 2.2) is allowed.
> - Added testcases for RV32I + 'Q' per extension version
> - 'Q' extension version 2.0 with RV32I is prohibited.
> ("rv32iq2" means RV32I + Q version 2".0" so also prohibited.)
> - 'Q' extension version 2.2 with RV32I is allowed.
>
> As I noted in v1, this implementation might be too pedantic.
> An option is to allow RV32IQ entirely (regardless of version numbers).
>
>
>
>
> Tsukasa OI (1):
> RISC-V: Fix RV32Q conflict
>
> bfd/elfxx-riscv.c | 5 +++--
> gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d | 3 +++
> gas/testsuite/gas/riscv/march-fail-rv32iq.d | 3 ---
> gas/testsuite/gas/riscv/march-fail-rv32iq2.d | 3 +++
> gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d | 3 +++
> .../riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} | 0
> gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d | 5 +++++
> gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d | 5 +++++
> 8 files changed, 22 insertions(+), 5 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
> delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq.d
> create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2.d
> create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
> rename gas/testsuite/gas/riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} (100%)
> create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
> create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
>
>
> base-commit: b275570803cefba388595bc42b75b68403eb86f1
Let me allow to send a ping.
Original:
https://sourceware.org/pipermail/binutils/2022-February/119893.html
I completely understand that my other fixes (except this and
Zihintpause) are relatively large and needs some time to review.
I think this (and Zihintpause patch) are completely safe to merge.
Thanks,
Tsukasa
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/1] RISC-V: Fix RV32Q conflict
2022-02-27 8:51 ` [PATCH v2 1/1] " Tsukasa OI
@ 2022-05-24 12:04 ` Kito Cheng
2022-05-25 3:23 ` Nelson Chu
1 sibling, 0 replies; 9+ messages in thread
From: Kito Cheng @ 2022-05-24 12:04 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Palmer Dabbelt, Nelson Chu, Jan Beulich, Binutils
LGTM.
On Sun, Feb 27, 2022 at 4:52 PM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>
> This commit makes RV32 + 'Q' extension (version 2.2 or later) not
> conflicting since this combination is no longer prohibited by the
> specification.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_parse_check_conflicts): Remove conflict
> detection that prohibits RV32Q on 'Q' version 2.2 or later.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/march-fail-rv32iq.d: Removed.
> * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
> * testsuite/gas/riscv/march-fail-rv32iq2p0.d: New test
> showing RV32IQ fails on 'Q' extension version 2.0.
> * testsuite/gas/riscv/march-fail-rv32iq2p0.l: Likewise.
> * testsuite/gas/riscv/march-fail-rv32iq2.d: Likewise.
> * testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d: New test
> showing RV32IQ fails on ISA specification version 2.2.
> * testsuite/gas/riscv/march-ok-rv32iq2p2.d: New test
> showing RV32IQ succesds on 'Q' extension version 2.2.
> * testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d: New test
> showing RV32IQ succesds on ISA specification 20190608.
> ---
> bfd/elfxx-riscv.c | 5 +++--
> gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d | 3 +++
> gas/testsuite/gas/riscv/march-fail-rv32iq.d | 3 ---
> gas/testsuite/gas/riscv/march-fail-rv32iq2.d | 3 +++
> gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d | 3 +++
> .../riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} | 0
> gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d | 5 +++++
> gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d | 5 +++++
> 8 files changed, 22 insertions(+), 5 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
> delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq.d
> create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2.d
> create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
> rename gas/testsuite/gas/riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} (100%)
> create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
> create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 2915b74dd0f..17567b2af54 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1880,10 +1880,11 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
> no_conflict = false;
> }
> if (riscv_lookup_subset (rps->subset_list, "q", &subset)
> + && (subset->major_version < 2 || (subset->major_version == 2
> + && subset->minor_version < 2))
> && xlen < 64)
> {
> - rps->error_handler
> - (_("rv%d does not support the `q' extension"), xlen);
> + rps->error_handler (_("rv%d does not support the `q' extension"), xlen);
> no_conflict = false;
> }
> if (riscv_lookup_subset (rps->subset_list, "e", &subset)
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d b/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
> new file mode 100644
> index 00000000000..16451b0f43f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
> @@ -0,0 +1,3 @@
> +#as: -misa-spec=2.2 -march=rv32iq
> +#source: empty.s
> +#error_output: march-fail-rv32iq2p0.l
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.d b/gas/testsuite/gas/riscv/march-fail-rv32iq.d
> deleted file mode 100644
> index c289c695cad..00000000000
> --- a/gas/testsuite/gas/riscv/march-fail-rv32iq.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv32iq
> -#source: empty.s
> -#error_output: march-fail-rv32iq.l
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq2.d b/gas/testsuite/gas/riscv/march-fail-rv32iq2.d
> new file mode 100644
> index 00000000000..34fce730ce5
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-fail-rv32iq2.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32iq2
> +#source: empty.s
> +#error_output: march-fail-rv32iq2p0.l
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
> new file mode 100644
> index 00000000000..916f845a970
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32iq2p0
> +#source: empty.s
> +#error_output: march-fail-rv32iq2p0.l
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.l b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.l
> similarity index 100%
> rename from gas/testsuite/gas/riscv/march-fail-rv32iq.l
> rename to gas/testsuite/gas/riscv/march-fail-rv32iq2p0.l
> diff --git a/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d b/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
> new file mode 100644
> index 00000000000..8322957948d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
> @@ -0,0 +1,5 @@
> +#as: -misa-spec=20190608 -march=rv32iq
> +#objdump: -dr
> +#source: empty.s
> +
> +.*: file format elf32-(little|big)riscv
> diff --git a/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d b/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
> new file mode 100644
> index 00000000000..1a922bfaa4d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
> @@ -0,0 +1,5 @@
> +#as: -march=rv32iq2p2
> +#objdump: -dr
> +#source: empty.s
> +
> +.*: file format elf32-(little|big)riscv
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/1] RISC-V: Fix RV32Q conflict
2022-02-27 8:51 ` [PATCH v2 1/1] " Tsukasa OI
2022-05-24 12:04 ` Kito Cheng
@ 2022-05-25 3:23 ` Nelson Chu
1 sibling, 0 replies; 9+ messages in thread
From: Nelson Chu @ 2022-05-25 3:23 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Palmer Dabbelt, Jan Beulich, Binutils
On Sun, Feb 27, 2022 at 4:51 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit makes RV32 + 'Q' extension (version 2.2 or later) not
> conflicting since this combination is no longer prohibited by the
> specification.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_parse_check_conflicts): Remove conflict
> detection that prohibits RV32Q on 'Q' version 2.2 or later.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/march-fail-rv32iq.d: Removed.
> * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
> * testsuite/gas/riscv/march-fail-rv32iq2p0.d: New test
> showing RV32IQ fails on 'Q' extension version 2.0.
> * testsuite/gas/riscv/march-fail-rv32iq2p0.l: Likewise.
> * testsuite/gas/riscv/march-fail-rv32iq2.d: Likewise.
> * testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d: New test
> showing RV32IQ fails on ISA specification version 2.2.
> * testsuite/gas/riscv/march-ok-rv32iq2p2.d: New test
> showing RV32IQ succesds on 'Q' extension version 2.2.
> * testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d: New test
> showing RV32IQ succesds on ISA specification 20190608.
Most of these testcases seems redundant, just test two of them should
be enough - rv32iq2p0 and rv32iq2p2. Test ISA spec version here is
unnecessary, since they don't really related to this patch. Anyway,
we could scale them down in the future patches, so committed for now.
Thanks
Nelson
> ---
> bfd/elfxx-riscv.c | 5 +++--
> gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d | 3 +++
> gas/testsuite/gas/riscv/march-fail-rv32iq.d | 3 ---
> gas/testsuite/gas/riscv/march-fail-rv32iq2.d | 3 +++
> gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d | 3 +++
> .../riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} | 0
> gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d | 5 +++++
> gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d | 5 +++++
> 8 files changed, 22 insertions(+), 5 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
> delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq.d
> create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2.d
> create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
> rename gas/testsuite/gas/riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} (100%)
> create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
> create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 2915b74dd0f..17567b2af54 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1880,10 +1880,11 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
> no_conflict = false;
> }
> if (riscv_lookup_subset (rps->subset_list, "q", &subset)
> + && (subset->major_version < 2 || (subset->major_version == 2
> + && subset->minor_version < 2))
> && xlen < 64)
> {
> - rps->error_handler
> - (_("rv%d does not support the `q' extension"), xlen);
> + rps->error_handler (_("rv%d does not support the `q' extension"), xlen);
> no_conflict = false;
> }
> if (riscv_lookup_subset (rps->subset_list, "e", &subset)
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d b/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
> new file mode 100644
> index 00000000000..16451b0f43f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
> @@ -0,0 +1,3 @@
> +#as: -misa-spec=2.2 -march=rv32iq
> +#source: empty.s
> +#error_output: march-fail-rv32iq2p0.l
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.d b/gas/testsuite/gas/riscv/march-fail-rv32iq.d
> deleted file mode 100644
> index c289c695cad..00000000000
> --- a/gas/testsuite/gas/riscv/march-fail-rv32iq.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv32iq
> -#source: empty.s
> -#error_output: march-fail-rv32iq.l
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq2.d b/gas/testsuite/gas/riscv/march-fail-rv32iq2.d
> new file mode 100644
> index 00000000000..34fce730ce5
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-fail-rv32iq2.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32iq2
> +#source: empty.s
> +#error_output: march-fail-rv32iq2p0.l
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
> new file mode 100644
> index 00000000000..916f845a970
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32iq2p0
> +#source: empty.s
> +#error_output: march-fail-rv32iq2p0.l
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.l b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.l
> similarity index 100%
> rename from gas/testsuite/gas/riscv/march-fail-rv32iq.l
> rename to gas/testsuite/gas/riscv/march-fail-rv32iq2p0.l
> diff --git a/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d b/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
> new file mode 100644
> index 00000000000..8322957948d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
> @@ -0,0 +1,5 @@
> +#as: -misa-spec=20190608 -march=rv32iq
> +#objdump: -dr
> +#source: empty.s
> +
> +.*: file format elf32-(little|big)riscv
> diff --git a/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d b/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
> new file mode 100644
> index 00000000000..1a922bfaa4d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
> @@ -0,0 +1,5 @@
> +#as: -march=rv32iq2p2
> +#objdump: -dr
> +#source: empty.s
> +
> +.*: file format elf32-(little|big)riscv
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-05-25 3:23 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-07 3:31 [PATCH 0/1] RISC-V: Fix RV32Q conflict Tsukasa OI
2022-02-07 3:31 ` [PATCH 1/1] " Tsukasa OI
2022-02-07 7:48 ` [PATCH 0/1] " Jan Beulich
2022-02-07 10:17 ` Tsukasa OI
2022-02-27 8:51 ` [PATCH v2 " Tsukasa OI
2022-02-27 8:51 ` [PATCH v2 1/1] " Tsukasa OI
2022-05-24 12:04 ` Kito Cheng
2022-05-25 3:23 ` Nelson Chu
2022-05-24 9:48 ` [PING][PATCH v2 0/1] " Tsukasa OI
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