Re: [PATCH v6 1/2] opcodes: microblaze: Add new bit-field instructions

[Michael Eager <eager@eagercon.com>]

Neal --

When I run the test suite I see many segfaults.

Take a look at
gas/config/tc-microblaze.c +418:
md_begin() ...
   /* Insert unique names into hash table.  */
   for (opcode = microblaze_opcodes; opcode->name; opcode ++)
     str_hash_insert (opcode_hash_control, opcode->name, opcode, 0);

compare the end of the microblaze_opcodes table:
binutils/opcodes/microblaze-opc.h +427
microblaze_opcodes[] ...
   {"", 0, 0, 0, 0, 0, 0, 0, 0},

It looks like there is a mismatch on termination condition.

I changed this to
   {NULL, 0, 0, 0, 0, 0, 0, 0, 0},

I'm at a loss to explain why this did not fail earlier.

On 10/13/23 00:28, Neal Frager wrote:
> This patches adds new bsefi and bsifi instructions.
> BSEFI- The instruction shall extract a bit field from a
> register and place it right-adjusted in the destination register.
> The other bits in the destination register shall be set to zero.
> BSIFI- The instruction shall insert a right-adjusted bit field
> from a register at another position in the destination register.
> The rest of the bits in the destination register shall be unchanged.

...

> diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
> index 12981abfea1..b2d3f19337c 100644
> --- a/opcodes/microblaze-dis.c
> +++ b/opcodes/microblaze-dis.c
> @@ -427,6 +442,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
>   	  /* For mbar 16 or sleep insn.  */
>   	case INST_TYPE_NONE:
>   	  break;
> +	  /* For bit field insns.  */
> +	case INST_TYPE_RD_R1_IMMW_IMMS:
> +	  print_func (stream, "\t%s, %s, %s, %s",
> +			get_field_rd (&buf, inst),
> +			get_field_r1 (&buf, inst),
> +			get_field_immw (&buf, inst),
> +			get_field_imm5 (&buf, inst));
> +	  break;

Fixed indent.

Trimmed commit message.

Committed.

-- 
Michael Eager